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TDA9103
DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
TDA9103DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
May 1996
SHRINK42(Plastic Package)
ORDER CODE: TDA9103
HORIZONTAL. DUAL PLL CONCEPT. 150kHz MAXIMUM FREQUENCY. SELF-ADAPTIVE (EX:30 TO85kHz). X-RAY PROTECTION INPUT. DC ADJUSTABLEDUTY-CYCLE. INTERNAL 1st PLL LOCK/UNLOCK IDENTIFICA-
TION.4 OUTPUTS FOR S-CORRECTION. WIDE RANGE DC CONTROLLED H-POSITION. ON/OFF SWITCH (FOR PWR MANAGEMENT). TWO H-DRIVE POLARITIES
VERTICAL. VERTICAL RAMP GENERATOR.50TO 150Hz AGC LOOP. DC CONTROLLED V-AMP, V-POS, S-AMP ANDS-
CENTERING. ON/OFF SWITCH
REGULATOR. INTERNAL PWM GENERATOR FORB+ CURRENT
MODE STEP-UPCONVERTER. DC ADJUSTABLEB+ VOLTAGE. OUTPUT PULSES SYNCHRONISED ON HORIZON-
TAL FREQUENCY. INTERNAL MAXIMUM CURRENT LIMITATION
EWPCC. VERTICAL PARABOLA GENERATOR WITH DC
CONTROLLED KEYSTONE AND AMPLITUDE
GENERAL. ACCEPT POS. OR NEG.H ANDV SYNC POLARI-
TIES. SEPARATEDH ANDV TTL INPUT. SAFETY BLANKING OUTPUT
DESCRIPTIONThe TDA9103isa monolithic integrated circuit assembleda42 pins shrunk dualin line plastic package.
ThisIC controlsall the functions relatedto the horizontal
and verticaldeflectioninmultimodes ormultisyncmonitors. canbeseeninthe blockdiagram,the TDA9103includes
the following functions: Positiveor Negative sync polarities, Auto-sync horizontal processing, H-PLL lock/unlock identification, Auto-sync Vertical processing, East/West signal processing block, B+ controller, Safety blanking output.
This IC, combined with TDA9205 (RGB preamp),
STV9420/21or22 (O.S.D. processor), ST7271 (micro
controller) and TDA8172 (vertical booster), allowsto real-
ize very simple and high quality multimodesor multisync
monitors.
ISENSE
COMP
REGIN
B+-ADJ
KEYST
E/W-AMP
E/WOUT
PLL1INHIB
VSYNC
V-POS DCOUT
V-AMP
VOUT
VS-CENT
VS-AMP
VCAP
VREF
VAGCCAP
VGND
SBLKOUT
B+OUT
PLL2C
H-DUTY
HFLY
HGND
HREF
S4
S3
S2
S1
C0
R0
PLL1F
HLOCK-CAP
FH-MIN
H-POS
XRAY-IN
HSYNC CC
GND
H-OUTEM
H-OUTCOL
9103-01.AI
PIN CONNECTIONS1/27
PIN-OUT DESCRIPTION
PinN° Name Function PLL2C Second PLL Loop Filter H-DUTY Controlof HorizontalDrive Output Pulse Duty-cycle. this pinis grounded,the horizontal and vertical outputs are inhibited.By connectinga
capacitoron thispina soft-start function maybe realizedon h-drive output. H-FLY Horizontal Flyback Input (positive Polarity) H-GND Horizontal Section Ground. Must beconnected onlyto components relatedtoH blocks. H-REF Horizontal Section Reference Voltage. Mustbe filteredby capacitorto Pin4 S4 Hor S-CAP Switching S3 Hor S-CAP Switching S2 Hor S-CAP Switching S1 Hor S-CAP Switching C0 Horizontal Oscillator Capacitor.Tobe connectedto Pin4. R0 Horizontal Oscillator Resistor.Tobe connectedto Pin4. PLL1F First PLL Loop Filter.Tobe connectedto Pin4. HLOCK-CAP
First PLL Lock/Unlock TimeConstant Capacitor. Capacitor filteringthe frequency change
detectedon Pin13. Whenfrequencyis changing,a blanking pulseis generatedonPin23,the
durationof this pulseis proportionnaltothe capacitoronPin13.Tobe connected toPin4. FH-MIN DC Controlfor Free Running Frequency Setting. Comming from DAC outputor DC voltage
generatedbya resistor bridge connected between Pin5 and4. H-POS DC Controlfor Horizontal Centering XRAY-IN X-RAY Protection Input (with internal latch function) H-SYNC TTL Horizontal Sync Input VCC Supply Voltage (12V Typical) GND Ground H-OUTEM Horizontal Drive Output (emiterof internal transistor). See descriptionon pages 15-16. H-OUTCOL Horizontal Drive Output (open collectorof internal transistor). See descriptionon pages 15-16. B+ OUT B+ PWM Regulator Output SBLK OUT Safety Blanking Output. Activated during frequency changes, when X-RAY inputis
triggeredor whenVSis too low. VGND Vertical Section Signal Ground VAGCCAP Memory Capacitorfor Automatic Gain Control Loopin Vertical Ramp Generator VREF Vertical Section Reference Voltage VCAP Vertical Sawtooth Generator Capacitor VS-AMP DC Controlof VerticalS Shape Amplitude VS-CENT DC Controlof VerticalS Centering VOUT Vertical Ramp Output (with frequency independant amplitude and S-correction) V-AMP DC Controlof Vertical Amplitude Adjustment VDCOUT Vertical Position Reference Voltage Output Temperature Matched with V-AMP Output V-POS DC Controlof Vertical Position Adjustment VSYNC Vertical TTL Sync Input PLL1INHIB TTL Inputfor PLL1 Output Current Inhibition (Tobe usedin caseof comp sync input signal) E/WOUT East/West Pincushion Correction Parabola Output E/W-AMP DC Controlof East/West Pincushion Correction Amplitude KEYST DC Controlof Keystone Correction B+ ADJ DC ControlofB+ Adjustment REGIN Regulation InputofB+ Control Loop COMP B+ Error Amplifier Outputfor Frequency Compensation and Gain Setting ISENSE Sensingof ExternalB+ Switching Transistor Emiter Current
9103-01.TBL
TDA91032/27
31019 2829 303812 131415 21 31 3233INPUT
INTERFACE
VERTICAL
OSCILLATOR
CORRECTION
PARABOLA
GENERATOR
INPUT
INTERFACE
1st PHASE
COMP7
FREQUENCY
OUTPUT
BUFFER
PULSE
SHAPER
2nd PHASE
COMP
LOCK
DETECT
SAFETY
PROCESSOR26
BANDGAP
Outputs
Inhibition
VCC R
VREF
TDA9103
VCO
H-VREF
V-VREF
SBLKOUT
B+-ADJ
ISENSE
B+OUT
COMP
REGIN
E/WOUT
VSYNC
VGND
HREF
VREF
HGND
XRAY-IN
GND
VAGCCAP
VS-CENT
VS-AMP
V-POS
V-AMP
VOUT
DCOUT
KEYST
E/W-AMP
VCAP
PLL1INHIB H-POSPLL1FR0C0FH-MINHLOCK-CAP HFLY PLL2C H-DUTY H-OUTEM H-OUTCOL S4S3S2S1
HSYNC
9103-02.EPS
BLOCK DIAGRAM
TDA91033/27
QUICK REFERENCE DATA
Parameter Value UnitHorizontal Frequency Range 15to 150 kHz
Autosynch Frequency Range (for Given R0, C0) 1to3.7 FH Hor Sync Polarity Input YES
Compatibility with Composite Syncon H-SYNC Input YES(1)
Lock/Unlock Identificationon1st PLL YES Controlfor H-Position YES
X-RAY Protection YES
Hor DUTY Adjust YES
Stand-by Function YES
Hor S-CAP Switching Control YES
Two Polarities H-Drive Outputs YES
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility YES
Safety Blanking Output YES
Vertical Frequency Range 35to 200 Hz
Vertical Autosync Range (fora Given Capacitor Value) 50to 150 Hz
Vertical-S- Correction YES
Vertical-C- Correction YES
Vertical Amplitude Adjustment YES
Vertical Position Adjustment YES
AutomaticB+ Adjustment Control Loop YES Adjustment YES
East/West Parabola Output YES
PCC (Pin Cushion Correction) Amplitude Adjustment YES
Keystone Adjustment YES
Reference Voltage YES(2)
Mode Detection NO
Dynamic Focus NO
Blanking Output NO
Notes:1. See applicationdiagram. Onefor Horizontal sectionand onefor Vertical section.
9103-02.TBL
TDA91034/27
HORIZONTAL SECTION
Operating conditions
Symbol Parameter Test conditions Min. Typ. Max. UnitVCO
R0min Oscillator Resistor Min Value Pin11 6 kΩ
C0min Oscillator Capacitor Min Value Pin10 390 pF
Fmax Maximum Oscillator Frequency 150 kHz
HsVR Horizontal Sync Input Voltage Range Pin17 0 5.5 V
INPUT SECTION
MinD Minimum Input Pulses Duration Pin17 0.7 μS
Mduty Maximum Input Signal Duty Cycle Pin17 25 %
OUTPUT SECTION
I3m Maximum Input Peak Currenton Pin3 2 mA
IS1to IS4 Maximum CurrentonS1toS4 Outputs Pins6to9 0.5 mA
VS1to VS4 Maximum VoltageonS1toS4 Outputs Pins6to9 VCC V
HOI1 Horizontal Drive Output Max Current Pin20, sourced current 20 mA
HOI2 Horizontal Drive Output Max Current Pin21, sunk current 20 mA CONTROL VOLTAGES
DCadj DC Voltage Rangeon DC Controls VREF-H= 8V, Pins 2-14-15 2 6 V
9103-05.TBL
ABSOLUTE MAX RATING
Symbol Parameter Value UnitVCC Supply Voltage (Pin18) 13.5 V
VIN Max Voltageon Pins2,14, 15,28,29, 31,33,37, 38,39
Pin3
Pins 17,34
Pin40
Pin42
Pin16
VESD ESD Succeptibility
Human Body Model, 100pFDischarge through 1.5kΩ
EIAJ Norm, 200pF Discharge through0Ω
Tstg Storage Temperature -40, +150 °C Max Operating Junction Temperature 150 °C
Toper Operating Temperature 0, +70 °C
9103-03.TBL
THERMAL DATA
Symbol Parameter Value UnitRth(j-a) Junction-Ambient Thermal Resistance Max. 65 °C/W
9103-04.TBL
TDA91035/27
Electrical Characteristics (VCC= 12V, Tamb =25°C)
Symbol Parameter Test conditions Min. Typ. Max. UnitSUPPLY AND REFERENCE VOLTAGES
VCC Supply Voltage Pin18 10.8 12 13.2 V
ICC Supply Current Pin 18, See Figure1 40 60 mA
VREF-H Reference Voltagefor Horizontal Section Pin5,I= 2mA 7.4 8 8.6 V
IREF-H Max Sourced Currenton VREF-H Pin5 5 mA
VREF-V Reference Voltagefor Vertical Section Pin 26,I= 2mA 7.4 8 8.6 V
IREF-V Max Sourced Currenton VREF-V Pin26 5 mA
INPUT SECTION/PLL1
VINTH Hor Input Threshold Voltage Pin17 Low level voltage
Highlevel voltage 2
0.8 V
VVCO VCO Control Voltage Range VREF-H= 8V, Pin12 1.6 6.2 V
VCOG VCO Gain, dF/dV Pin12 R0= 6.49kΩ,C0= 680pF 15 kHz/V
Hph Horizontal Phase Adj Range (Pin 15) %of Hor period ±12.5 %
FFadj Free Running Frequency Adj Range (Pin 14) Without H-sync Signal ±20 %
S1th VCO Input VoltageforS1 Switching Pin12 voltage, VREF-H=8V 1.85 2 2.25 V
S2th VCO Input VoltageforS2 Switching Pin12 voltage, VREF-H=8V 2.25 2.4 2.65 V
S3th VCO Input VoltageforS3 Switching Pin12 voltage, VREF-H=8V 2.9 3 3.3 V
S4th VCO Input VoltageforS4 Switching Pin12 voltage, VREF-H=8V 3.5 3.7 3.9 V Free Running Frequency V14 =VREF/2= 6.49kΩ= 680pF
23.5 25 27.5 kHz
VS1Dto
VS4D
Low LevelOutput VoltageonS1toS4 Outputs Pins6to9,I= 0.5mA 0.2 0.4 V PLL1 Capture Range (F0= 27kHz) Min Max
See conditionson Figure1
kHz
PLLinh PLL1 Inhibition (Pin 35)
PLL ON
PLL OFF
V35
V35 2
SECOND PLL AND HORIZONTAL OUTPUT SECTION
FBth Flyback Input Threshold Voltage Pin3 0.65 0.75 V
Hjit Horizontal Jitter 100 ppm
HDmin
HDmin
Minimum Hor Drive Output Duty-cycle
Maximum Hor Drive Output Duty-cycle
Pin20or 21,V2 =2V
Pin20or 21,V2 =6V 45 %
HDvd Horizontal Drive Low Level Output Voltage V21-V20, Iout= 20mA,
Pin20to GND
1.1 1.7 V
HDem Horizontal Drive High Level Output Voltage
(outputon Pin 20)
Pin21to VCC,IOUT= 20mA 9.5 10 V
XRAYth X-RAY Protection Input ThresholdVoltage Pin16 1.6 1.8 V
ISblkO Maximum Output Currenton Safety Blanking
Output
I23 10 mA
VSblkO Low-Level Voltageon Safety Blanking Output V23 withI23= 10mA 0.25 0.5 V
Vphi2 Internal Clamping Voltageon 2nd PLL Loop
Filter Output (Pin1)
Vmin
Vmax
VOFF Pin2 Threshold Voltageto Stop H-out, V-out
B+out andto Activate S-BLK.OFF Mode
whenV2
9103-06.TBL
TDA9103
6/27
SECTIONOperating Conditions
Symbol Parameter Testconditions Min. Typ. Max. Unit
EAOI Maximum Error Amplifier Output Current Sourcedby Pin41
Sunkby Pin41
FeedRes Minimum Feedback Resistor Resistor between Pins40
and41
5kΩ
9103-07.TBL
Electrical Characteristics (VCC= 12V, Tamb =25°C)
Symbol Parameter Testconditions Min. Typ. Max. Unit
OLG Error AmplifierOpen Loop Gain At low frequency
(see Note1) dB
UGBW Unity Gain Bandwidth (see Note1) 6 MHz
IRI Regulation Input Bias Current Current sourcedby
Pin40 (PNP base)
0.2 μA
EAOI Maximum Guaranted Error Amplifier
Output Current
Current sourcedby Pin41
Current sunkby Pin41
CSG Current Sense Input VoltageGain Pin42 3
MCEth Max Curent Sense Input Threshold Voltage Pin42 1.2 V
ISI Current Sense Input Bias Current Current sunkby Pin42
(NPN base) μA
Tonmax Maximum External Power Transistoron Time %of H-periodf0= 27kHz %
B+OSV B+ Output Low Level Saturation Voltage V22 withI22= 10mA 0.25 V
IVREF Internal Reference Voltage On error amp (+)inputfor
V39 =4V
4.9 V
VREFADJ Internal Reference Voltage Adjustment Range 2V< V39 <6V ±14 %
9103-08.TBL
EAST WEST PARABOLA GENERATOR
ElectricalCharacteristics (VCC= 12V, Tamb =25°C)
Symbol Parameter Testconditions Min. Typ. Max. Unit
Vsym Parabola Symetry Adjustment Capability (for
Keystone Adjustment; with Pin 38)
See Figure2; internal
voltage
V38 =2V
V38 =4V
V38 =6V
Kadj Keystone Adjustment Capability
B/A ratio
A/B ratio
See Figure2; V37 =4V
V38 =2V
V38 =6V
Paramp Parabola Amplitude Adjustment Capability
Maximum Amplitudeon Pin36
Maximum Ratio between Max and Min
V38= 4.3V, V28 =2V
V37 =2V< V37 <6V
9103-09.TBL
TDA9103
7/27
9103-11.TBL
VERTICAL SECTION
Operating Conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSVR Vertical Sync Input Voltage Range OnPin34 0 5.5 V
9103-10.TBL
Electrical Characteristics (VCC= 12V,Tamb =25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
IBIASP Pin 23-28-29 Bias Current (Current Sourced PNP Base)
For V23-28-29 =2V 2 μA
IBIASN Pin31 Bias Current (Current Sunkby NPN
Base)
ForV31=6V 0.5 μA
VSth Vertical Sync Input Threshold Voltage Pin34; High-level
Low-level
VSBI Vertical Sync Input Bias Current (Current
Sourcedby PNP Base)
V34= 0.8V 1 μA
VRB Voltageat Ramp Bottom Point On Pin27 2/8 VREF-V
VRT Voltageat Ramp Top Point (with Sync) On Pin27 5/8 VREF-V
VRTF Voltageat Ramp Top Point (without Sync) On Pin27 VRT-0.1 V
IR27 Output Current Rangeon Pin27 during
Ramp Charging Time. Currentto Charge
Capacitor between Pin27 and Ground
V28=2V (Note2),Min current
Max current 100
135 μA
VSW Minimum Vertical Sync Pulse Width Pin34 5 μS
VSmDut Vertical Sync Input Maximum Duty-cycle Pin34 15 %
VSTD Vertical Sawtooth Discharge Time Duration On Pin27, with 150nF cap 85 μS
VFRF Vertical Free Running Frequency (V28= 2V) Measuredon Pin27
Cosc (Pin27)= 150nF
100 Hz
ASFR AUTO-SYNC Frequency Range
(see Note3)
With C27= 150nF ±5% 50 150 Hz
RATD Ramp Amplitude Thermal Drift On Pin30 (see Note1)
(0°C< Tamb <70°C)
100 ppm/°C
RAFD Ramp Amplitude Drift Versus Frequency V31= 6V, C27= 150nF
50Hz200 ppm/Hz
Rlin Ramp Linearityon Pin27 ΔI27/I27 V28= 2V, V25= 4.3V
2.5V< V27< 4.5V
0.5 %
Rload Minimum LoadonPin25for less than1%
Vertical Amplitude Drift MΩ
Vpos Vertical Position Adjustment Range Voltage Pin32
V33 =2V
V33 =4V
V33=6V 3.65
3.3 V
IVPOS Max Currenton Vertical Position Control
Output (Pin32) ±2mA
Vor Vertical Output Voltage Range (on Pin30)
(Peakto Peak VoltageonPin 30)
V31 =2V
V31 =4V
V31=6V 3.75
2.2 V
VOUTDC DC Voltageon Vertical Output (Pin30) See Note4 7/16 VREF-V
V0I Vertical Output Maximum Output Current On Pin30 ±5mA
dVS Max Vertical S-Correction Amplitude
(V28=2V Inhibits S-CORR; V28=6V gives
Maximum S-CORR) (see Figure3)
ΔV/V30ppat T/4
ΔV/V30ppat 3T/4
Ccorr C-Correction Adjustment Range Voltageon
Pin27for Maximum Slopeonthe Ramp
(with S-Correction) (see Figure4)
V29 =2V
V29 =4V
V29 =6V
Notes:1. These parametersarenot testedon each unit. Theyare measured duringour internalqualification procedure whichincludes
characterization onbatches comming from corners ofour processes andalso temperature characterization. When2Vare appliedonPin28 (VerticalS-Correction control),thenthe S-Correctionis inhibited, consequentlythe sawtooth have linear shape.Itisthe frequencyrangefor whichthe VERTICALOSCILLATORwill automatically synchronize, usinga single capacitor valueon
Pin27and witha constant ramp amplitude. Typically 3.5Vfor Verticalreference voltage typical value (8V).
TDA9103
8/27
150nF
470nF1%
12VINPUT
INTERFACE
VERTICAL
OSCILLATOR
CORRECTION
PARABOLA
GENERATOR
10k
INPUT
INTERFACE
1st
PHASE
COMP
12V
12V
FREQUENCY
OUTPUT
BUFFER
PULSE
SHAPER
2nd
PHASE
COMP
22nF
220nF
49k
680pF1%
10nF
VCO
LOCK
DETECT SAFETY
PROCESSOR
2.2 24
H-VREF V-VREF
BANDGAP
Outputs
Inhibition 4022 4142S
REF
12V
3.9k
47k
470pF
10k
12V
4.7k
TDA9103
4.7 F
9103-54.EPS
Figure1: Testing Circuit
TDA9103
9/27
36273.838 =2V38 =4V38 =6V
9103-03.AI
Figure2: KeystoneAdjustment30 increase whenV28 increase. =0 whenV28 =0.
V30pp T/4 T/2 T3T/4
9103-04.AI
Figure3:S Amplitude Adjustment27
3.0V
3.5V
4.0V
9103-05.AI
Figure4:C Correction Adjustment
TDA9103
10/27
VREF
10kΩ
22kΩ DC Control Voltage
10kΩ
9103-06.AI
Figure5: Exampleof Practical DC Control
Voltage Generation
9103-07.AI
Figure6
1.6VHSYNC
9103-08.AI
Figure7: Input Structure
OPERATING DESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
The typical valueof the power supply voltage VCC 12V. Perfect operationis obtainedif VCC ismain-
tainedin the limits: 10.8V→ 13.2V. orderto avoid erratic operationof the circuit
during the transient phaseof VCC switching on,or
switching off, the valueof VCC ismonitoredand the
outputsof the circuit are inhibitedifitis too low. ordertohaveavery good powersupplyrejection,
the circuitis internally poweredby several internal
voltage references (The unique typical valueof
whichis 8V). Twoof these voltage references are
externally accessible, one for the vertical part and
one for the horizontal part. These voltage refer-
ences can be used for the DC control voltages
appliedon the concerned pinsby the wayof poten-
tiometersor digitalto analog converters (DAC’s).
Furthermoreitis possibleto filterthe a.m. voltage
referencesby the useof external capacitor con-
nectedto ground,in orderto minimize the noise
and consequently the ”jitter”on vertical and hori-
zontal output signals. Control Adjustments
The circuithas 10adjustmentcapabilities:3 forthe
horizontal part,1for the SMPS part,2for the E/W
correction,4 forthe vertical part.
The corresponding inputsof the circuit hasto be
driven witha DC voltage typically comprised be-
tween2 and 6V fora valueof the internal voltage
referenceof 8V.
More precisely, the control voltages haveto be
maintained between VREF/4 and 3/4⋅ VREF. The
applicationof control voltages outside this rangeis
not dangerousfor the circuit but the good operation not guaranted (except for Pin2: duty cycle
adjusment. See outputs inhibition paragraph).
The input currentsof the DC control inputs are
typically very low (abouta few μA). Dependingon
the internal structureof the inputs, the input cur-
rents canbe positiveor negative (sinkor source).
HORIZONTAL PART
Input section
The horizontal inputis designedtobe sensitiveto
TTL signals typically comprised between 0and 5V.
The typicalthresholdof this inputis 1.6V.This input
stage usesan NPN differentialstage and the input
currentis very low.
Concerning the duty cycleof the input signal, the
following signals maybe appliedto the circuit.
Using internal integration, both signals are recog-
nizedon conditionthat Z/T≤ 25%. Synchronisation
occurson the leading edgeof the rectified signal.
The minimum valueofZis 0.7μs.
PLL1
The PLL1is composedofa phase comparator,an
external filter anda Voltage Controlled Oscillator
(VCO).
Thephase comparatorisa ”phase frequency”type,
designedin CMOS technology. This kindof phase
detector avoids lockingon false frequencies.Itis
followedbya ”charge pump”, composedof2 cur-
rent sources sink and source(I= 1mA typ.)
TDA9103
11/27
The dynamic behaviourof the PLLis fixedby an
external filter which integrates the currentof the
charge pump.A ”CRC” filteris generallyused.
PLL1is inhibitedby applyinga high levelon Pin35
(PLLinhib) whichisa TTLcompatible input. The inhibi-
tion results from the openingofa switch located be-
tween thechargepump andthe filter (see Figure8).
The VCO usesan external RC network.It delivers linear sawtooth obtained by charge and dis-
chargeof the capacitor,bya current proportionnal the currentin the resistor. typical thresholdsof
sawtooth are 1.6V and 6.4V.
PLL1F
9103-10.AI
Figure9 Lockdet
LOCKDET
COMP1INPUT
INTERFACE
CHARGE
PUMP
PLL
INHIBITION VCO
PHASE
ADJUST
Eini
Horizontal
Adjust C0Filter
Horizontal
Input
High
LowE2
3.2V
OSC 35 12 11 10
9103-09.AI
Figure8: Principle Diagram
The control voltageof the VCOis typically com-
prised between 1.6V and 6V. The theoretical fre-
quency rangeof this VCOisin the ratio1→ 3.75,
but dueto spread and thermal driftof external
components and the circuit itself, the effective fre-
quency range hasto be smaller (e.g. 30kHz→
82kHz).Inthe absenceofsynchronisationsignal the
control voltageis equalto 1.6V typ. and the VCO
oscillatesonits lowest frequency (free frequency).
Thesynchrofrequencyhastobe always higher than
the free frequencyanda margin hasto betaken.As example fora synchro range from 30kHzto
82kHz, the suggested free frequencyis 27kHz.To
compensatefor the spreadof external components
andof the circuit itself, the free frequency maybe
adjustedbya DC voltageon Pin14 (Fmin adjust)
(see Figure10for details).
The PLL1 ensures the coincidence between the
leading edgeof the synchro signal anda phase
reference obtained by comparison between the
sawtoothof the VCO and an internal DC voltage
adjustable between 2.4V and 4V (by Pin 15). Soa
±45° phase adjustmentis possible.
Loop
Filter
(0.8VFHMINADJ
1.6V
6.4V
6.4V
1.6V 0.75TT
FLIP FLOPa
(1.6V4I0
9103-58.EPS
Figure10: Detailsof VCO and Fhmin Adjustment
TDA9103
12/27
SMPSOutputInhibition
VCC30
REF30
XRAY30
VCCoff30
H-duty Cycle3030
Flyback30
0.7V30PLL-Unloocked
VCC Checking
XRAY Protection
Inhibition
HOutput
Inhibition Output
Inhibition
Blanking
9103-21.AI
Figure11: Safety Functions Block Diagram
20kΩ
220nF
From
Phase
Comparator
NOR1 A
6.5V NOR2 23 SBLK OUTH-Lock CAP
9103-59.EPS
Figure12: LOCK/UNLOCK Block Diagram
The TDA9103 also includesa LOCK/UNLOCK
identification block which sensein real-time
wheather the PLLis locked on the incomming
horizontalsyncsignalor not.Theresulting informa-
tionis availableon safety blanking output (Pin 23)
whereitis mixedwith others information (see Fig-
ure 11). The block diagramof the LOCK/UNLOCK
functionis describedin Figure 12.
The NOR1 gateis receiving the phase comparator
output pulses (which alsodrives thecharge pump).
When the PLLis locked,on pointA thereisa very
small negative pulse (100ns)at each horizontal
cycle,so after R-C filter, thereisa high levelon Pin which force SBLKto high level (provided other
inputson NOR2 are alsoat low level).
When the PLLis unlocked, the 100ns negative
pulse onA becomesmuch largerandconsequently
the average levelon Pin13 will decrease. Whenit
reaches 6.5V, pointB goesto high level forcing
NOR2 open collector outputto ”0”.
The statusof Pin13is approximatelythe following: Near 0V when thereisno H-SYNC, Between0 and4V with H-SYNC frequency differ- Osc
Sawtooth
Phase REF1 Synchro
1.6V
6.4V
2.4V0.75T 0.25T
Phase REF1is obtainedby comparison betweenthe sawtooth
anda DC voltage adjustable between 2.4V and4V. The PLL1
ensuresthe exact coincidence betweenthe signals phase REF
and HSYNS.A±45° phase adjustment ispossible.
9103-16.AI
Figure13: PLL1 Timing Diagram
ent from VCO, Between4 and 8V whenH-SYNC frequency VCO frequency but notin phase, Nearto 8V when PLLis locked.is importantto notice that Pin13is notan output
pin andmust onlybe usedfor filtering purpose (see
Figure 12).
TDA9103
13/27
LockdetLOCKDET
COMP1INPUT
INTERFACE
CHARGE
PUMP
PLL
INHIBITION VCO
PHASE
ADJUST
Eini
Horizontal
AdjustC0Filter
Freq
Adjust
High
LowE2
3.2V
OSC
FAJUST
HFREQ
GENPULSECOMP2CHARGE
PUMP
High
Low
RAP
CYC
Adjust
Rapcyc
Cap
PH12
PWM LOGI
PWM BUFFER
FLYBACK
SortCOLL
Flyback
SortEMVA
Horizontal
Input 35 12 1110
9103-15.AI
Figure14: Dual PLL Block Diagram
PLL2
The PLL2 ensures the coincidence between the
leading edgeof the shaped flyback signal anda
phase reference signal obtained bycomparisonof
the sawtoothofthe VCOanda constantDCvoltage
(3.2V) (see Figure 15).
The phase comparatorof PLL2is similarto the one PLL1,itis followedbya charge pump witha
20kΩ
400Ω
GND0VHFLY
9103-11.AI
Figure16: Flyback Input Electrical Diagram Osc
Sawtooth
Phase REF2 Drive
1.6V
3.2V
6.4V
0.75T 0.25T
Duty Cycle
Shapped
Flyback
Flyback
9103-57.AI
Phase REF2is obtainedbycomparison betweenthe sawtoothand 3.2V (constant). The PLL2 ensuresthe exact coincidence
betweenthe signals phase REF2 andtheflyback signal. The duty
cycleof H-driveis adjustable between 30%and 50%.
Figure15: PLL2 Timing Diagram
±0.5mA(typ.) output current.
Theflybackinputiscomposedofan NPNtransistor.
This input hasto be currentdriven. The maximum
recommanded input currentis 2mA (see Fig-
ure 16).
Output Section
The H-drive signalis transmittedto the output
througha shaping block ensuringa duty cycle
adjustable from 30%to 50%.In orderto ensurea
reliable operationof the scanning power part, the
outputis inhibitedin the following circumstances:
-VCC toolow. Xray protection activated. During the flyback. Output voluntarily inhibited.
The output stageis composed ofa DarlingtonNPN
bipolartransistor.Both the collectorand the emitter
are accessible.
TDA9103
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