TDA8950J-TDA8950TH Fast Delivery |IC PHOENIX CO.,LIMITED

TDA8950TH ,2 x 150 W class-D power amplifierBlock diagramVDDA n.c. STABI PROT VDDP2 VDDP13 (20) 10 (4) 18 (12) 13 (7) 23 (16) 14 (8)15 (9)BOOT1 ..
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TDA8950J-TDA8950TH
2 x 150 W class-D power amplifier
General descriptionThe TDA8950isa high-efﬁciency ClassD audio power ampliﬁer. The typical output power
is 2 × 150 W with a speaker load impedance of 4Ω.
The TDA8950 is available in both HSOP24 and DBS23P power packages. The ampliﬁer
operates over a wide supply voltage range from ±12.5 V to ±40 V and features low
quiescent current consumption. Features Pin compatible with TDA8920B for both HSOP24 and DBS23P packages Symmetrical operating supply voltage range from ±12.5 V to ±40V Stereo full differential inputs, can be used as stereo Single-Ended (SE) or mono
Bridge-Tied Load (BTL) ampliﬁer High output power in typical applications: SE 2× 150 W, RL =4 Ω (VP = ±37V) SE 2× 170 W, RL =4 Ω (VP = ±39V) SE 2× 100 W, RL =6 Ω (VP = ±37V) BTL 1× 300 W, RL =8 Ω (VP = ±37V) Low noise Smooth pop noise-free start-up and switch off Zero dead time switching Fixed frequency Internal or external clock High efﬁciency Low quiescent current Advanced protection strategy: voltage protection and output current limiting Thermal FoldBack (TFB) Fixed gain of 30 dB in SE and 36 dB in BTL applications Fully short-circuit proof across load BD modulation in BTL conﬁguration Applications DVD Mini and micro receiver Home Theater In A Box (HTIAB) system High-power speaker system
TDA8950 × 150 W class-D power ampliﬁer
Rev. 02 — 11 June 2009 Product data sheet
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer Quick reference data
[1] VP is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] The circuit is DC adjusted at VP= ±12.5 V to ±32.5 V.
[3] Output power is measured indirectly; based on RDSon measurement; see Section 13.3. Ordering information
Table 1. Quick reference data
General, VP[1] ±30 V supply voltage Operating mode [2] ±12.5 ±35 ±40 V
VP(ovp) overvoltage protection supply voltage Standby, Mute modes; VDD − VSS 85 - 90 V
Iq(tot) total quiescent current Operating mode; no load; no ﬁlter; no
RC-snubber network connected
-50 75 mA
Stereo SE conﬁguration output power Tj =85 °C; LLC =22 μH; CLC= 680nF
(see Figure 10)
[3]
THD + N=10 %; RL =4 Ω; VP= ±39V 170 W
THD+N= 0.5 %; RL = 4 Ω; VP= ±37V - 100- W
THD+N=10 %; RL = 4 Ω; VP= ±37V - 150- W
THD+N=10 %; RL = 6 Ω; VP = ±37 V - 100- W
Mono BTL conﬁguration output power Tj =85 °C; LLC =22 μH; CLC= 680nF
(see Figure 10); RL =8Ω;
THD + N =10 %; VP= ±37V
[3]- 300- W
Table 2. Ordering information
TDA8950J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
TDA8950TH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer Block diagram
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer Pinning information
7.1 Pinning
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
7.2 Pin description Functional description
8.1 General
The TDA8950 is a two-channel audio power ampliﬁer that uses Class D technology.
For each channel, the audio input signal is converted into a digital PWM signal using an
analog input stage and a PWM modulator; see Figure 1. To drive the output power
transistors, the digital PWM signal is fed to a control and handshake block and to high-
and low-side driver circuits. This level-shifts the low-power digital PWM signal froma logic
level to a high-power PWM signal switching between the main supply lines. 2nd-order low-pass ﬁlter converts the PWM signaltoan analog audio signal that canbe
used to drive a loudspeaker.
Table 3. Pin description
VSSA 1 18 negative analog supply voltage
SGND 2 19 signal ground
VDDA 3 20 positive analog supply voltage
IN2M 4 21 channel 2 negative audio input
IN2P 5 22 channel 2 positive audio input
MODE 6 23 mode selection input: Standby, Mute or Operating
mode
OSC 7 1 oscillator frequency adjustment or tracking input
IN1P 8 2 channel 1 positive audio input
IN1M 9 3 channel 1 negative audio input
n.c. 10 4 not connected
n.c. 11 5 not connected
n.c. 12 6 not connected
PROT 13 7 decoupling capacitor for protection (OCP)
VDDP1 14 8 channel 1 positive power supply voltage
BOOT1 15 9 channel 1 bootstrap capacitor
OUT1 16 10 channel 1 PWM output
VSSP1 17 11 channel 1 negative power supply voltage
STABI 18 12 decoupling of internal stabilizer for logic supply
n.c. 19 - not connected
VSSP2 20 13 channel 2 negative power supply voltage
OUT2 21 14 channel 2 PWM output
BOOT2 22 15 channel 2 bootstrap capacitor
VDDP2 23 16 channel 2 positive power supply voltage
VSSD 24 17 negative digital supply voltage
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
The TDA8950 single-chip Class D ampliﬁer contains high-power switches, drivers, timing
and handshaking between the power switches, along with some control logic. To ensure
maximum system robustness, an advanced protection strategy has been implemented to
provide overvoltage, overtemperature and overcurrent protection.
Eachof the two audio channels containsa PWM modulator,an analog feedback loop and
a differential input stage. The TDA8950 also contains circuits common to both channels
such as the oscillator, all reference sources, the mode interface and a digital timing
manager.
The two independent ampliﬁer channels feature high output power, high efﬁciency, low
distortion and low quiescent currents, and can be connected in the following
conﬁgurations: Stereo Single-Ended (SE) Mono Bridge-Tied Load (BTL)
The ampliﬁer system can be switched to one of three operating modes using pin MODE: Standby mode: featuring very low quiescent current Mute mode: the ampliﬁer is operational but the audio signal at the output is
suppressed by disabling the voltage-to-current (VI converter) input stages Operating mode: the ampliﬁeris fully operational, de-muted and can deliveran output
signal slowly rising voltage shouldbe applied (e.g. viaan RC network)to pin MODEto ensure
pop noise-free start-up. The bias-current setting of the (VI converter) input stages is
related to the voltage on the MODE pin.
In Mute mode, the bias-current setting of the VI converters is zero (VI converters are
disabled). In Operating mode, the bias current is at a maximum. The time constant
required to apply the DC output offset voltage gradually between Mute and Operating
mode levels canbe generated usingan RC network connectedto pin MODE. An example
of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor was
omitted, the very short switching time constant could result in audible pop noises being
generated at start-up (depending on the DC output offset voltage and loudspeaker used).
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer ensure the coupling capacitorsat the inputs (CINin Figure 10) are fully charged before
the outputs start switching,a delayis inserted during the transition from Muteto Operating
mode. An overviewof the start-up timingis providedin Figure5. For proper switch-off, the
MODE pin shouldbe forced LOWat leaxt 100 ms before the supply lines (VDDA and VSSA)
drop below 12.5 V.
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
8.2 Pulse-width modulation frequency
The ampliﬁer output signal is a PWM signal with a typical carrier frequency of between
250 kHz and 450 kHz.A 2nd-order LC demodulation ﬁlteron the outputis usedto convert
the PWM signal into an analog audio signal. The carrier frequency is determined by an
external resistor, ROSC, connected between pins OSC and VSSA. The optimal carrier
frequency setting is between 250 kHz and 450 kHz.
The carrier frequencyis setto 345 kHzby connectingan external30 kΩ resistor between
pins OSC and VSSA. SeeT able 9 for more details.
If two or more Class D ampliﬁers are used in the same audio application, it is
recommended that an external clock circuit be used with all devices (see Section 13.4).
This will ensure that they operate at the same switching frequency, thus avoiding beat
tones(if the switching frequencies are different, audible interference knownas ‘beat tones’
can be generated)
8.3 Protection
The following protection circuits are incorporated into the TDA8950: Thermal protection: Thermal FoldBack (TFB) OverTemperature Protection (OTP) OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protection: UnderVoltage Protection (UVP) OverVoltage Protection (OVP) UnBalance Protection (UBP)
How the device reacts to a fault conditions depends on which protection circuit has been
activated.
8.3.1 Thermal protection
The TDA8950 employes an advanced thermal protection strategy. A TFB function
gradually reduces the output power withina deﬁned temperature range.If the temperature
continues to rise, OTP is activated to shut down the device completely.
8.3.1.1 Thermal FoldBack (TFB) the junction temperature (Tj) exceeds the thermal foldback activation threshold, the gain gradually reduced. This reduces the output signal amplitude and the power dissipation,
eventually stabilizing the temperature.
TFB is speciﬁed at the thermal foldback activation temperature Tact(th_fold) where the
closed-loop voltage gain is reduced by 6 dB. The TFB range is:
Tact(th_fold)−5 °C < Tact(th_fold) < Tact(th_prot)
The value of Tact(th_fold) for the TDA8950 is approximately 153 °C; see Table 8 for more
details.
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
8.3.1.2 OverTemperature Protection (OTP) TFB failsto stabilize the temperature and the junction temperature continuesto rise, the
ampliﬁer will shut down as soon as the temperature reaches the thermal protection
activation threshold, Tact(th_prot). The ampliﬁer will resume switching approximately 100 ms
after the temperature drops below Tact(th_prot).
The thermal behavior is illustrated in Figure6.
8.3.2 OverCurrent Protection (OCP)
In order to guarantee the robustness of the TDA8950, the maximum output current that
can be delivered at the output stages is limited. OCP is built in for each output power
switch.
OCP is activated when the current in one of the power transistors exceeds the OCP
threshold (IORM = 9.2 A) due, for example, to a short-circuit to a supply line or across the
load.
The TDA8950 ampliﬁer distinguishes between low-ohmic short-circuit conditions and
other overcurrent conditions such as a dynamic impedance drop at the loudspeaker. The
impedance threshold (Zth) depends on the supply voltage.
How the ampliﬁer reacts to a short circuit depends on the short-circuit impedance: Short-circuit impedance> Zth: the ampliﬁer limits the maximum output currentto IORM
but the ampliﬁer does not shut down the PWM outputs. Effectively, this results in a
clipped output signal across the load (behavior very similar to voltage clipping). Short-circuit impedance< Zth: the ampliﬁer limits the maximum output currentto IORM
and at the same time discharges the capacitor on pin PROT. When CPROT is fully
discharged, the ampliﬁer shuts down completely and an internal timer is started.
The value of the protection capacitor (CPROT) connected to pin PROT can be between pF and 220 pF (typically 47 pF). While OCP is activated, an internal current source is
enabled that will discharge CPROT.
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
When OCP is activated, the power transistors are turned off. They are turned on again
during the next switching cycle.If the output currentis still greater than the OCP threshold,
they willbe immediately switchedoff again. This switching will continue until CPROTis fully
discharged. The ampliﬁer will then be switched off completely and a restart sequence
initiated.
After a ﬁxed period of 100 ms, the ampliﬁer will attempt to switch on again, but will fail if
the output current still exceeds the OCP threshold. The ampliﬁer will continue trying to
switch on every 100 ms. The average power dissipation will be low in this situation
because the duty cycle is low.
Switching the ampliﬁer on and off in this way will generate unwanted ‘audio holes’. This
can be avoided by increasing the value of CPROT (up to 220 pF) to delay ampliﬁer
switch-off. CPROT will also prevent the ampliﬁer switching off due to transient
frequency-dependent impedance drops at the speakers.
The ampliﬁer will switch on, and remain in Operating mode, once the overcurrent
condition has been removed. OCP ensures the TDA8950 ampliﬁer is fully protected
against short-circuit conditions while avoiding audio holes.
[1] VP is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] OVP can be triggered by supply pumping; see Section 13.6.
8.3.3 Window Protection (WP)
Window Protection (WP) checks the conditionsat the output terminalsof the power stage
and is activated: During the start-up sequence, when the TDA8950 is switching from Standby to Mute.
Start-up will be interrupted If a short-circuit is detected between one of the output
terminals and pin VDDP1/VDDP2 or VSSP1/VSSP2. The TDA8950 will wait until the
short-circuitto the supply lines has been removed before resuming start-up. The short
circuit will not generate large currents because the short-circuit check is carried out
before the power stages are enabled. When the ampliﬁer is shut down completely because the OCP circuit has detected a
short circuit to one of the supply lines.
WP will be activated when the ampliﬁer attempts to restart after 100 ms (see
Section 8.3.2). The ampliﬁer will not start-up again until the short circuitto the supply
lines has been removed.
Table 4. Current limiting behavior during low output impedance conditions at different
values of CPROT
TDA8950 29.5 500 20 10 yes yes OVP[2]
1000 10 yes yes no 15 yes yes OVP[2]
1000 15 yes no no
1000 220 no no no
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
8.3.4 Supply voltage protection the supply voltage drops below the minimum supply voltage threshold, VP(uvp), the UVP
circuit will be activated and the system will shut down. Once the supply voltage rises
above VP(uvp) again, the system will restart after a delay of 100 ms.
If the supply voltage exceeds the maximum supply voltage threshold, VP(ovp), the OVP
circuit will be activated and the power stages will be shut down. When the supply voltage
drops below VP(ovp) again, the system will restart after a delay of 100 ms.
An additional UnBalance Protection (UBP) circuit compares the positive analog supply
voltage (on pin VDDA) with the negative analog supply voltage (on pin VSSA) and is
triggered if the voltage difference exceeds a factor of two (VDDA > 2 ×|VSSA| OR |VSSA|> × VDDA). When the supply voltage difference drops below the unbalance threshold,
VP(ubp), the system restarts after 100 ms.
An overview of all protection circuits and their respective effects on the output signal is
provided in Table5.
[1] Ampliﬁer gain depends on the junction temperature and heatsink size.
[2] The ampliﬁer shuts down completely only if the short-circuit impedance is below the impedance threshold
(Zth; see Section 8.3.2). In all other cases, current limiting results in a clipped output signal.
[3] Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been
activated (short-circuit to one of the supply lines).
8.4 Differential audio inputs
The audio inputs are fully differential ensuring a high common mode rejection ratio and
maximum ﬂexibility in the application. Stereo operation: to avoid acoustical phase differences, the inputs should be in
antiphase and the speakers should be connected in antiphase. This conﬁguration: minimizes power supply peak current minimizes supply pumping effects, especially at low audio frequencies Mono BTL operation: the inputs mustbe connectedin anti-parallel. The outputof one
channelis inverted and the speaker loadis connected between the two outputsof the
TDA8950. In practice (because of the OCP threshold) the output power can be
boosted to twice the output power that can be achieved with the single-ended
conﬁguration.
The input conﬁguration for a mono BTL application is illustrated in Figure7.
Table 5. Overview of TDA8950 protection circuits
TFB[1] NNNN
OTP Y N Y N
OCP Y[2] N[2] Y[2] Y N[3] YN N
UVP YN YN
OVP Y N Y N
UBP YN YN
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer Limiting values
[1] VP is the supply voltage on pins VDDP1, VDDP2 and VDDA.
10. Thermal characteristics
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1] supply voltage Standby, Mute modes; VDD− VSS -90 V
IORM repetitive peak output current maximum output current limiting 9.2 - A
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °C junction temperature - 150 °C
VMODE voltage on pin MODE referenced to SGND 0 6 V
VOSC voltage on pin OSC 0 SGND + 6 V input voltage referenced to SGND; pin IN1P; IN1M;
IN2P and IN2M
−5+5 V
VPROT voltage on pin PROT referenced to voltage on pin VSSD 0 12 V
VESD electrostatic discharge voltage Human Body Model (HBM) −2000 +2000 V
Charged Device Model (CDM) −500 +500 V
Iq(tot) total quiescent current Operating mode; no load; no ﬁlter; no
RC-snubber network connected
-75 mA
VPWM(p-p) peak-to-peak PWM voltage on pins OUT1 and OUT2 - 120 V
Table 7. Thermal characteristics
Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W
Rth(j-c) thermal resistance from junction to case 1.1 K/W
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
11. Static characteristics
[1] VP is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] The circuit is DC adjusted at VP= ±12.5 V to ±42.5 V.
[3] Unbalance protection activated when VDDA > 2 ×|VSSA| OR |VSSA|> 2 × VDDA.
[4] With respect to SGND (0V).
[5] The transition between Standby and Mute modes has hysteresis, whilethe slope ofthe transition between Mute and Operating modesis
determined by the time-constant of the RC network on pin MODE; see Figure8.
[6] DC output offset voltage is gradually applied to the output during the transition between Mute and Operating modes. The slope caused
by any DC output offset is determined by the time-constant of the RC network on pin MODE.
[7] Ata junction temperatureof approximately Tact(th_fold)−5°C, gain reduction commences andata junction temperatureof approximately
Tact(th_prot), the ampliﬁer switches off.
Table 8. Static characteristics
VP = ±35 V; fosc = 345 kHz; Tamb = 25 °C; unless otherwise speciﬁed.
Supply[1] supply voltage Operating mode [2] ±12.5 ±30 ±40 V
VP(ovp) overvoltage protection supply voltage Standby, Mute modes;
VDD− VSS - 90 V
VP(uvp) undervoltage protection supply voltage VDD− VSS 20 - 25 V
VP(ubp) unbalance protection supply voltage [3] -33 - %
Iq(tot) total quiescent current Operating mode; no load; no
ﬁlter;no RC-snubber network
connected 5075mA
Istb standby current measured at 30 V - 480 650 μA
Mode select input; pin MODE
VMODE voltage on pin MODE referenced to SGND [4] 0- 6V
Standby mode [4][5]0 - 0.8 V
Mute mode [4][5] 2.2 - 3.0 V
Operating mode [4][5] 4.2 - 6 V input current VI = 5.5 V - 110 150 μA
Audio inputs; pins IN1M, IN1P, IN2P and IN2M input voltage DC input [4] -0 -V
Ampliﬁer outputs; pins OUT1 and OUT2
VO(offset) output offset voltage SE; Mute mode - - ±25 mV
SE; Operating mode [6] -- ±150 mV
BTL; Mute mode - - ±30 mV
BTL; Operating mode [6] -- ±210 mV
Stabilizer output; pin STABI
VO(STABI) output voltage on pin STABI Mute and Operating modes;
with respect to VSSD
9.3 9.8 10.3 V
Temperature protection
Tact(th_prot) thermal protection activation
temperature 154 - °C
Tact(th_fold) thermal foldback activation
temperature
closed loop SE voltage gain
reduced with 6dB
[7]- 153 - °C
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
12. Dynamic characteristics
12.1 Switching characteristics
[1] VP is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] When using an external oscillator, the frequency ftrack (500 kHz minimum, 900 kHz maximum) will result in a PWM frequency fosc
(250 kHz minimum, 450 kHz maximum) due to the internal clock divider; see Section 8.2.
[3] When tr(i) > 100 ns, the output noise ﬂoor will increase.
Table 9. Dynamic characteristics[1] ±35 V; Tamb = 25 °C; unless otherwise speciﬁed.
Internal oscillator
fosc(typ) typical oscillator frequency ROSC= 30.0kΩ 290 345 365 kHz
fosc oscillator frequency 250 - 450 kHz
External oscillator input or frequency tracking; pin OSC
VOSC voltage on pin OSC HIGH-level SGND+ 4.5 SGND+5 SGND+6 V
Vtrip trip voltage - SGND + 2.5 - V
ftrack tracking frequency [2] 500 - 900 kHz input impedance 1 - - MΩ input capacitance - - 15 pF
tr(i) input rise time from SGND +0V
SGND + 5 V
[3]- - 100 ns
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
12.2 Stereo SE conﬁguration characteristics
[1] VP is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] RsL is the series resistance of the low-pass LC ﬁlter inductor used in the application.
[3] Output power is measured indirectly; based on RDSon measurement; see Section 13.3.
[4] THD measured between22Hz and20 kHz, using AES1720 kHz brick wall ﬁlter; max. limitis guaranteedbut maynotbe 100% tested.
[5] Vripple = Vripple(max) = 2 V (p-p); measured independently between VDDPn and SGND and between VSSPn and SGND.
[6] 22 Hz to 20 kHz, using AES17 20 kHz brick wall ﬁlter.
Table 10. Dynamic characteristics[1] ±35 V; RL = 4 Ω; fi = 1 kHz; fosc = 345 kHz; RsL[2] Ω; Tamb = 25 °C; unless otherwise speciﬁed. output power Tj =85 °C; LLC =22 μH; CLC= 680 nF (see
Figure 10)
[3]
THD + N=10 %; RL =4 Ω; VP= ±39V 170 W
THD+N= 0.5 %; RL = 4 Ω; VP= ±37V - 100- W
THD+N=10 %; RL = 4 Ω; VP= ±37V - 150- W
THD+N=10 %; RL = 6 Ω; VP = ±37 V - 100- W
THD total harmonic distortion Po=1 W; fi=1 kHz [4]- 0.05- %=1 W; fi=6 kHz [4]- 0.05- %
Gv(cl) closed-loop voltage gain 29 30 31 dB
SVRR supply voltage ripple rejection between pins VDDPn and SGND
Operating mode; fi= 100Hz [5] -90 - dB
Operating mode; fi=1 kHz [5] -70 - dB
Mute mode; fi= 100Hz [5] -75 - dB
Standby mode; fi= 100Hz [5]- 120- dB
between pins VSSPn and SGND
Operating mode; fi= 100Hz [5] -80 - dB
Operating mode; fi=1 kHz [5] -60 - dB
Mute mode; fi= 100Hz [5] -80 - dB
Standby mode; fi= 100Hz [5]- 115- dB input impedance between one of the input pins and SGND 45 63 - kΩ
Vn(o) output noise voltage Operating mode; Rs =0Ω [6]- 160- μV
Mute mode [7] -85 - μV
αcs channel separation [8] -70 - dB
|ΔGv| voltage gain difference - - 1 dB
αmute mute attenuation fi=1 kHz; Vi=2 V (RMS) [9] -75 - dB
CMRR common mode rejection ratio Vi(CM)=1 V (RMS) - 75 - dB
ηpo output power efﬁciency SE, RL = 4Ω -88 - %
SE, RL = 6Ω -90 - %
BTL, RL = 8Ω -88 - %
RDSon(hs) high-side drain-source on-state
resistance
[10]- 200- mΩ
RDSon(ls) low-side drain-source on-state
resistance
[10]- 190- mΩ
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
[8] Po = 1 W; fi = 1 kHz.
[9] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.
[10] Leads and bond wires included.
12.3 Mono BTL application characteristics
[1] VP is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] RsL is the series resistance of the low-pass LC ﬁlter inductor used in the application.
[3] Output power is measured indirectly; based on RDSon measurement; see Section 13.3.
[4] THD measured between22Hz and20 kHz, using AES1720 kHz brick wall ﬁlter; max. limitis guaranteedbut maynotbe 100% tested.
[5] Vripple = Vripple(max) = 2 V (p-p).
[6] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall ﬁlter; low noise due to BD modulation.
[7] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall ﬁlter.
[8] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.
Table 11. Dynamic characteristics[1] ±35 V; RL = 8 Ω; fi = 1 kHz; fosc = 345 kHz; RsL[2] Ω ; Tamb = 25 °C; unless otherwise speciﬁed. output power Tj =85 °C; LLC =22 μH; CLC= 680 nF (see
Figure 10)
[3]
THD+N=10 %; RL = 8 Ω; VP= ±39V - 340- W
THD+N= 0.5 %; RL = 8 Ω; VP= ±37V - 200- W
THD+N=10 %; RL = 8 Ω; VP= ±37V - 300- W
THD total harmonic distortion Po=1 W; fi=1 kHz [4]- 0.05- %=1 W; fi=6 kHz [4]- 0.05- %
Gv(cl) closed-loop voltage gain - 36 - dB
SVRR supply voltage ripple rejection between pin VDDPn and SGND
Operating mode; fi= 100Hz [5] -80 - dB
Operating mode; fi=1 kHz [5] -80 - dB
Mute mode; fi= 100Hz [5] -95 - dB
Standby mode; fi= 100Hz [5]- 120- dB
between pin VSSPn and SGND
Operating mode; fi= 100Hz [5] -75 - dB
Operating mode; fi=1 kHz [5] -75 - dB
Mute mode; fi= 100Hz [5] -90 - dB
Standby mode; fi= 100Hz [5]- 130- dB input impedance measured between one of the input pins and
SGND 63 - kΩ
Vn(o) output noise voltage Operating mode; Rs =0Ω [6]- 190- μV
Mute mode [7] -45 - μV
αmute mute attenuation fi=1 kHz; Vi=2 V (RMS) [8] -75 - dB
CMRR common mode rejection ratio Vi(CM)=1 V (RMS) - 75 - dB
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
13. Application information
13.1 Mono BTL application
When using the power ampliﬁerina mono BTL application, the inputsof the two channels
must be connected in parallel and the phase of one of the inputs must be inverted; see
Figure 7. In principle, the loudspeaker can be connected between the outputs of the two
single-ended demodulation ﬁlters.
13.2 Pin MODE
To ensure a pop noise-free start-up, an RC time-constant must be applied to pin MODE.
The bias-current setting of the VI converter input is directly related to the voltage on pin
MODE. In turn the bias-current setting of the VI converters is directly related to the DC
output offset voltage. A slow dV/dt on pin MODE results in a slow dV/dt for the DC output
offset voltage, ensuringa pop noise-free transition between Mute and Operating modes.A
time-constant of 500 ms is sufﬁcient to guarantee pop noise-free start-up; see Figure4,
Figure 5 and Figure 8 for more information.
13.3 Estimating the output power
13.3.1 Single-Ended (SE)
Maximum output power:
(1)
Maximum output current is internally limited to 9.2A:
(2)
Where: Po(0.5 %): output power at the onset of clipping RL: load impedance RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) RsL: series impedance of the ﬁlter coil VP: single-sided supply voltage or 0.5× (VDD + |VSS|) tw(min): minimum pulse width (typical 150 ns, temperature dependent) fosc: oscillator frequency
Remark: Note that Io(peak) should be less than 9.2 A (Section 8.3.2). Io(peak) is the sum of
the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.o 0.5%()LL R DSonhs() RsL++ ----------------------------------------------------- VP 1tw min() 0.5× fosc– ()××L -----------------------------------------------------------------------------------------------------------------------------------------= opeak()P 1tw min() 0.5fosc×– ()×L R DSonhs() RsL++ ---------------------------------------------------------------------=
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
13.3.2 Bridge-Tied Load (BTL)
Maximum output power:
(3)
Maximum output current internally limited to 9.2A:
(4)
Where: Po(0.5 %): output power at the onset of clipping RL: load impedance RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) RDSon(ls): low-side RDSson of power stage output DMOS (temperature dependent) RsL: series impedance of the ﬁlter coil VP: single-sided supply voltage or 0.5× (VDD + |VSS|) tw(min): minimum pulse width (typical 150 ns, temperature dependent) fosc: oscillator frequency
Remark: Note that Io(peak) shouldbe less than 9.2A; see Section 8.3.2.Io(peak)is the sum
of the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.
13.4 External clock
To ensure duty cycle-independent operation, the external clock frequency is divided by
two internally. The external clock frequencyis therefore twice the internal clock frequency
(typically 2 × 350 kHz = 700 kHz).
If several Class D ampliﬁers are used in a single application, it is recommended that all
the devices runat the same switching frequency. This canbe achievedby connecting the
OSC pins together and feeding them from an external oscillator. When using an external
oscillator, it is necessary to force pin OSC to a DC level above SGND. This disables the
internal oscillator and causes the PWM to switch at half the external clock frequency.
The internal oscillator requires an external resistor ROSC, connected between pin OSC
and pin VSSA. ROSC must be removed when using an external oscillator.
The noise generated by the internal oscillator is supply voltage dependent. An external
low-noise oscillator is recommended for low-noise applications running at high supply
voltages.o 0.5%()LL R DSonhs() R DSonls()++ ------------------------------------------------------------------- 2VP 1t wmin() 0.5fosc×– ()××L
-----------------------------------------------------------------------------------------------------------------------------------------------------------= opeak()P 1tw min() 0.5fosc×– ()×L R DSonhs() R DSonls()+ () 2RsL++ -------------------------------------------------------------------------------------------=
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer
13.5 Heatsink requirements
An external heatsink must be connected to the TDA8950.
Equation5 deﬁnes the relationship between maximum power dissipation before activation
of TFB and total thermal resistance from junction to ambient.
(5)
Power dissipation (P) is determined by the efﬁciency of the TDA8950. Efﬁciency
measured as a function of output power is given in Figure 20. Power dissipation can be
derived as a function of output power as shown in Figure 19.thja–()j T amb– ------------------------=
NXP Semiconductors TDA8950 × 150 W class-D power ampliﬁer the following example,a heatsink calculationis madeforan8Ω BTL application witha
±30 V supply:
The audio signal has a crest factor of 10 (the ratio between peak power and average
power (20 dB)); this means that the average output power is1 ⁄10 of the peak power.
Thus, the peak RMS output power level is the 0.5 % THD level, i.e. 170W.
The average power is then1⁄10 × 170W=17W.
The dissipated power at an output power of 17 W is approximately 7W.
When the maximum expected ambient temperature is 50 °C, the total Rth(j-a) becomes
Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a)
Rth(j-c) (thermal resistance from junction to case) = 1.1 K/W
Rth(c-h) (thermal resistance from case to heatsink) = 0.5 K/W to1 K/W (dependent on
mounting)
So the thermal resistance between heatsink and ambient temperature is:
Rth(h-a) (thermal resistance from heatsink to ambient) = 14− (1.1+1)= 11.9 K/W
The derating curves for power dissipation (for several Rth(j-a) values) are illustrated in
Figure 9. A maximum junction temperature Tj= 150 °C is taken into account. The
maximum allowable power dissipation for a given heatsink size can be derived, or the
required heatsink size can be determined, at a required power dissipation level; see
Figure9.
13.6 Pumping effects
In a typical stereo single-ended conﬁguration, the TDA8950 is supplied by a symmetrical
supply voltage (e.g. VDD=30 V and VSS= −30 V). When the ampliﬁer is used in an SE
conﬁguration,a ‘pumping effect’ can occur. During one switching interval, energyis taken
from one supply (e.g. VDD), while a part of that energy is returned to the other supply line
(e.g. VSS) and vice versa. When the voltage supply source cannot sink energy, the voltage
across the output capacitors of that voltage supply source increases and the supply
voltage is pumped to higher levels. The voltage increase caused by the pumping effect
depends on: Speaker impedance Supply voltage Audio signal frequency Value of supply line decoupling capacitors Source and sink currents of other channels
Pumping effects should be minimized to prevent the malfunctioning of the audio ampliﬁer
and/or the voltage supply source. Ampliﬁer malfunction due to the pumping effect can
trigger UVP, OVP or UBP.
148 50– () ------------------------- 14 K/W=

Partno	Mfg	Dc	Qty	Available	Descript
TDA8950J	NXP	N/a	13	avai	2 x 150 W class-D power amplifier
TDA8950TH	NXP	N/a	19	avai	2 x 150 W class-D power amplifier