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TDA8034AT
Low power smart card interface
1. General descriptionThe TDA8034T/TDA8034AT is a cost-effective analog interface for asynchronous and
synchronous smart cards operating at 5 V or 3 V. Using few external components, the
TDA8034T/TDA8034AT provides all supply, protection and control functions between a
smart card and the microcontroller.
2. Features and benefits Integrated circuit smart card interface in an SO16 package5 V or 3 V smart card supply One protected half-duplex bidirectional buffered I/O line (C7) VCC regulation: 5V 5 % or 3 V 5 % using two low ESR multilayer ceramic capacitors: one of
220 nF and one of 470 nF current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC =1.8 V) up to MHz, with controlled rise and fall times and filtered overload detection of
approximately 120 mA Thermal and short-circuit protection for all card contacts Automatic activation and deactivation sequences triggered by a short-circuit, card
take-off, overheating, falling VDD, VDD(INTF) or VDDP Enhanced card-side ElectroStatic Discharge (ESD) protection of >6 kV External clock input up to 26 MHz connected to pin XTAL1 Card clock generation up to 20 MHz using pin CLKDIV1 with synchronous frequency
changes of:1⁄2 fxtal or1 ⁄4 fxtal on TDA8034T fxtal or1⁄2 fxtal on TDA8034AT Non-inverted control of pin RST using pin RSTIN Compatible with ISO 7816, NDS and EMV 4.2 payment systems Supply supervisor for killing spikes during power on and off: using a fixed threshold using an external resistor bridge with threshold adjustment Built-in debouncing on card presence contacts (typically 4.5 ms) Multiplexed status signal using pin OFFN
3. Applications Pay TV Electronic payment
TDA8034T ; TDA8034AT
Smart card interface
Rev. 3.1 — 13 December 2012 Product data sheet
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface Identification Bank card readers
4. Quick reference data[1] To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of
either 100 nF or one 220 nF and one 470nF.
5. Ordering information
Table 1. Quick reference dataVDDP =5V; VDD =3.3 V; VDD(INTF) =3.3 V; fxtal =10MHz; GND= 0V; Tamb=25 °C; unless otherwise specified.
SupplyVDDP power supply voltage pin VDDP 4.85 5 5.5 V
VDD supply voltage pin VDD 2.7 3.3 3.6 V
VDD(INTF) interface supply voltage pin VDD(INTF) 1.6 3.3 VDD +0.3 V
IDD supply current Shutdown mode - - 35 A
IDDP power supply current Shutdown mode; fxtal
stopped 5 A
Active mode;
fCLK=1⁄2 fxtal; no load 1.5 mA
IDD(INTF) interface supply current Shutdown mode - - 6 A
Card supply voltage: pin VCC[1]VCC supply voltage active mode
5V card
ICC<65 mA DC 4.75 5.0 5.25 V
current pulses of nA/s at
ICC <200 mA; < 400ns
4.65 5.0 5.25 V
Vripple(p-p) peak-to-peak ripple voltage from 20 kHz to 200 MHz - - 350 mV
ICC supply current VCC =0 V to 5 V or 3V - - 65 mA
Generaltdeact deactivation time see Figure 7 on page11 35 90 250 s
Ptot total power dissipation Tamb= 25 C to +85 C- - 0.25 W
Tamb ambient temperature 25 - +85 C
Table 2. Ordering informationTDA8034T/C1 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
TDA8034AT/C1
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
6. Block diagramNXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
7. Pinning information
7.1 Pinning
7.2 Pin description
Table 3. Pin descriptionXTAL1 1 VDD I crystal connection input
XTAL2 2 VDD O crystal connection output
VDD(INTF) 3VDD(INTF)P interface supply voltage
RSTIN 4 VDD(INTF)I microcontroller card reset input; active HIGH
CMDVCCN5 VDD(INTF)I microcontroller start activation sequence input; active LOW
CLKDIV1 6 VDD(INTF)I sets the clock frequency on pin CLK; see Table 4 on page7
PRESN 7 VDD(INTF)I card presence contact input; active LOW[2]
I/O 8 VCC I/O card input/output data line (C7)[3]
GND 9 - G ground
CLK 10 VCC O card clock (C3)
RST 11 VCC O card reset (C2)
VCC 12 VCC P card supply (C1); decouple to pin GND using one 470 nF capacitor close to pin VCC
and one 220 nF capacitor close to card socket contact C1 with an ESR < 100 m[4]
VDDP 13 VDDP P low-dropout regulator input supply voltage
VDD 14 VDD P digital supply voltage
OFFN 15 VDD(INTF)O NMOS interrupt to microcontroller[5] 8.9 on page11
I/OUC 16 VDD(INTF) I/O microcontroller input/output data line[6]
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface[5] Uses an internal 20 k pull-up resistor connected to pin VDD(INTF).
[6] Uses an internal 10 k pull-up resistor connected to pin VDD(INTF).
8. Functional description
Remark: Throughout this document the ISO 7816 terminology conventions have been adhered to and it is assumed that the reader is familiar with these.
8.1 Power suppliesThe power supply voltage ranges are as follows:
VDDP: 4.85Vto 5.5V
VDD: 2.7Vto 3.6V
VDD should rise prior to VDDP or at the same time. VDDP should not rise before VDD.
All interface signals to the system controller are referenced to VDD(INTF). All card contacts
remain inactive during power up or power down. After powering up the device, pin OFFN
remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power
down, pin OFFN goes LOW when VDDP falls below the falling threshold voltage (Vth).
The internal oscillator frequency (fosc(int)) is only used during the activation sequences.
When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low
frequency mode to reduce power consumption.
This device has a Low Drop-Off (LDO) voltage regulator connected to pin VCC, and is
used instead of a DC-to-DC converter. It ensures a minimum VCC of 4.75 V and that the
power supply voltage on pin VDDP does not fall below 4.85 V for a maximum load current
of 65 mA.
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
8.2 Voltage supervisorThe voltage supervisor monitors the voltage of the VDDP and VDD supplies providing both
Power-On Reset (POR) and supply drop-out detection during a card session. The
supervisor threshold voltages for VDDP and VDD are set internally. As long as VDD is less
than Vth + Vhys, the IC remains inactive irrespective of the command line levels. After VDD
has reached a level higher than Vth + Vhys, the IC remains inactive for the duration of tw.
The output of the supervisor is sent to a digital controller in order to reset the
TDA8034T/TDA8034AT. This defined reset pulse of approximately 8 ms, i.e. (tw = 1024 ⁄fosc(int)low), is used internally to maintain the IC in the Shutdown mode during the supply
voltage power on; see Figure 4. A deactivation sequence is performed when either VDD or
VDDP falls below Vth.
Remark: fosc(int)low is the low frequency (or inactive) mode of the defined fosc(int) parameter.
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
8.3 Clock circuitsThe clock signal from pin CLK to the card is either supplied by an external clock signal
connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and
XTAL2. The TDA8034T/TDA8034AT automatically detects if an external clock is
connected to XTAL1, eliminating the need for a separate pin to select the clock source.
Automatic clock source detection is performed on each activation command (falling edge
of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is
checked during a time window defined by the internal oscillator. If a clock is detected, the
internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator
is started. When an external clock is used, it is mandatory that the clock is applied to pin
XTAL1 before the falling edge of the signal on pin CMDVCCN.
The clock frequency is selected using pin CLKDIV1 to be either 1⁄2 fxtal or 1⁄4 fxtal on
TDA8034T or fxtal or 1⁄2 fxtal on TDA8034AT as shown in Table4.
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change has the correct width. When dynamically changing the frequency, the modification
is only effective after 10 clock periods on pin XTAL1.
The duty cycle of fxtal on pin CLK should be between 45 % and 55 %. If an external clock
is connected to pin XTAL1, its duty cycle must be between 48 % and 52%.
When the frequency of the clock signal on pin CLK is either 1⁄2 fxtal or 1⁄4 fxtal on TDA8034T
or fxtal or 1⁄2 fxtal on TDA8034AT, the frequency dividers guarantee a duty cycle between % and 55 %.
Table 4. Clock configurationHIGH 1⁄2 fxtal 1⁄2 fxtal
LOW 1⁄4 fxtal fxtal
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
8.4 Input and output circuitsWhen pins I/O and I/OUC are pulled HIGH using an 11 k resistor between pins I/O and
VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is
referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC VDD(INTF).
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other line, making it the slave. After a time delay td,
the logic 0 present on the master-side is sent to the slave-side. When the master-side
returns logic 1, the slave-side sends logic 1 during time delay (tw(pu)). After this sequence,
both master and slave sides return to their idle states.
The active pull-up feature ensures fast LOW-to-HIGH transitions making the
TDA8034T/TDA8034AT capable of delivering more than 1 mA, up to an output voltage of
0.9VCC, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is
dependent on the internal pull-up resistor value and load current. The current sent to and
received from the card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
8.5 Shutdown modeAfter a power-on reset, if pin CMDVCCN is HIGH, the circuit enters the Shutdown mode,
ensuring only the minimum number of circuits are active while the TDA8034T/TDA8034AT
waits for the microcontroller to start a session.
all card contacts are inactive. The impedance between the contacts and GND is
approximately 200.
pin I/OUC is high-impedance using the 11 k pull-up resistor connected to VDD(INTF)
the voltage generators are stopped
the voltage supervisor is active
the internal oscillator runs at its lowest frequency (fosc(int)low)
8.6 Activation sequenceThe following device activation sequence is applied when using an external clock; see
Figure6: Pin CMDVCCN is pulled LOW (t0). The internal oscillator is triggered (t0). The internal oscillator changes to high frequency (t1). VCC rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2). Pin I/O is driven HIGH (t3). The clock on pin CLK is applied to the C3 contact (t4). Pin RST is enabled (t5).
Calculation of the time delays is as follows:
t1 = t0+ 3841 ⁄fosc(int)low
t2 = t1
t3 = t1+ 17T/2
t4 = driven by host controller; > t3 and < t5
t5 = t1+ 23T/2
Remark: The value of period T is 64 times the period interval of the internal oscillator at high frequency (1 ⁄fosc(int)high); t3 is called td(start) and t5 is called td(end).
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
8.7 Deactivation sequenceWhen a session ends, the microcontroller sets pin CMDVCCN HIGH. The
TDA8034T/TDA8034AT then executes an automatic deactivation sequence by counting
the sequencer back to the inactive state (see Figure 7) as follows: Pin RST is pulled LOW (t11). The clock is stopped, pin CLK is LOW (t12). Pin I/O is pulled LOW (t13). VCC falls to 0V (t14). The deactivation sequence is completed when VCC reaches its
inactive state. VCC < 0.4 V (tdeac) All card contacts become low-impedance to GND. However, pin I/OUC remains pulled
up to VDD using the 11 k resistor. The internal oscillator returns to its low frequency mode.
Calculation of the time delays is as follows:
t11 = t10+3T/64
t12 = t11+T/2
t13 = t11+T
t14 = t11+3T/2
tdeac = t11 + 3T/ 2 + VCC fall time
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. 25 s).
8.8 VCC regulatorThe VCC buffer is able to continuously deliver up to 65 mA at VCC = 5V or 3V.
The VCC buffer has an internal overload protection with a threshold value of approximately
120 mA. This detection is internally filtered, enabling spurious current pulses up to
200 mA with a duration of a few milliseconds to be drawn by the card without causing
deactivation. However, the average current value must stay below maximum; see Table8.
8.9 Fault detectionThe following conditions are monitored by the fault detection circuit:
Short-circuit or high current on pin VCC
Card removal during transaction
VDDP falling
VDD falling
VDD(INTF) falling
Overheating
Fault detection monitors two different situations:
Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in
the reader and HIGH if the card is in the reader. Any voltage drop on VDD is detected
by the voltage supervisor. This generates an internal power-on reset pulse but does
not act upon the pin OFFN signal. The card is not powered-up and short-circuits or
overheating are not detected.
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface In card sessions, pin CMDVCCN is LOW: when pin OFFN goes LOW, the fault
detection circuit triggers the automatic emergency deactivation sequence (see
Figure 8). When the microcontroller resets pin CMDVCCN to HIGH, after the
deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN
returns to HIGH. This check identifies the fault as either a hardware problem or a card
removal incident.
On card insertion or removal, bouncing can occur in the PRESN signal. This depends on
the type of card presence switch in the connector (normally open or normally closed) and
the mechanical characteristics of the switch. To correct for this, a debouncing feature is
integrated in to the TDA8034T/TDA8034AT. This feature operates at a typical duration of
4.5 ms (tdeb = 640(1 ⁄fosc(int)low). Figure 9 on page 13 shows the operation of the
debouncing feature.
On card insertion, pin OFFN goes HIGH after the debounce time has elapsed. When the
card is extracted, the automatic card deactivation sequence is performed on the first
HIGH/LOW transition on pin PRESN. After this, pin OFFN goes LOW.
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
8.10 Automatic determining of card supply voltageThe supply voltage (VCC) that the card requires is determined automatically by monitoring
the duration of the HIGH state (logic 1) on pin CMDVCCN before the activation command
(CMDVCCN falling edge) occurs. If pin CMDVCCN stays HIGH for more than 30 ms,
activation occurs with VCC set to 5 V. If pin CMDVCCN stays HIGH for less than 15 ms,
activation occurs with VCC set to 3V.
To activate the card at VCC = 5 V, pin CMDVCCN must stay HIGH for t0>30 ms before
going LOW (logic 0).
To activate the card at VCC = 3 V, pin CMDVCCN must stay HIGH for t0<15 ms before
going LOW (logic 0).
If pin CMDVCCN is HIGH for more than 15 ms (t0 > 15 ms) but less than 30 ms, pin
CMDVCCN must be set LOW for t1 (200 s
(200sNXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
If pin CMDVCCN is HIGH for more than 30 ms (card inactive), and if the card needs to be
activated at 3 V, the sequence shown in Figure 12 applies: pin CMDVCCN must be set
LOW for t1 (200 s < t1 < 700 s), and then HIGH for t2 (200 s < t2 < 15 ms) before
going LOW.
9. Limiting values
Remark: All card contacts are protected against any short-circuit to any other card
contact. Stress beyond the levels indicated in Table 5 can cause permanent damage to
the device. This is a short-term stress rating only and under no circumstances implies
functional operation under long-term stress conditions.
10. Thermal characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDDP power supply voltage pin VDDP 0.3 +6 V
VDD supply voltage pin VDD 0.3 +4.6 V
VDD(INTF) interface supply voltage pin VDD(INTF) 0.3 +4.6 V input voltage pins CMDVCCN, CLKDIV1, RSTIN, OFFN,
XTAL1, XTAL2, I/OUC 0.3 +4.6 V
card contact pins PRESN, I/O, RST and
CLK 0.3 +6 V
Tstg storage temperature 55 +150 C
Ptot total power dissipation Tamb= 25 C to +85C - 0.25 W junction temperature - +125 C
Tamb ambient temperature 25 +85 C
VESD electrostatic discharge voltage Human Body Model (HBM) on card pins I/O,
RST, VCC, CLK, PRESN; within typical
application
6+6 kV
Human Body Model (HBM); all other pins 2+2 kV
Machine Model (MM); all pins 200 +200 V
Field Charged Device Model (FCDM);
all pins 500 +500 V
Table 6. Thermal characteristics
Rth(j-a) SO16 thermal resistance from junction to ambient in free air 94 K/W
NXP Semiconductors TDA8034T ; TDA8034AT
Smart card interface
11. CharacteristicsTable 7. Characteristics of IC supply voltage
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.
Supply
VDDP power supply voltage pin VDDP 4.85 5 5.5 V
VDD supply voltage pin VDD 2.7 3.3 3.6 V
VDD(INTF) interface supply voltage pin VDD(INTF) 1.6 3.3 VDD +0.3 V
IDD supply current Shutdown mode - - 35 A
IDDP power supply current Shutdown mode
fxtal stopped - - 5 A
Active mode
fCLK = 1⁄2 fxtal; no load - - 1.5 mA
fCLK = 1⁄2 fxtal; ICC =65mA - - 70 mA
IDD(INTF) interface supply current Shutdown mode - - 6 A
Vth threshold voltage pin VDD 2.30 2.40 2.50 V
pin VDDP 3.00 4.10 4.40 V
Vhys hysteresis voltage pin VDD 50 100 150 mV
pin VDDP 100 200 350 mV pulse width 5.1 8 10.2 ms
Card supply voltage: pin VCC[1]
Cdec decoupling capacitance connected to VCC [2] 550 - 830 nF output voltage Shutdown mode
no load 0.1 - +0.1 V =1mA 0.1 - +0.3 V output current Shutdown mode; pin VCC
connected to ground 1mA
VCC supply voltage active mode
5V card
ICC<65 mA DC 4.75 5.0 5.25 V
current pulses of 40 nA/s
at ICC <200 mA; < 400ns
4.65 5.0 5.25 V
3V card
ICC<65 mA DC 2.85 3.05 3.15 V
current pulses of 40 nA/s
at ICC <200 mA; < 400ns
2.76 - 3.20 V
Vripple(p-p) peak-to-peak ripple
voltage kHz to 200 MHz - - 350 mV
ICC supply current VCC = 0V to 5V or 3V - - 65 mA
VCC shorted to ground 90 120 150 mA slew rate 5 V card 0.055 0.180 0.300 V/s
3 V card 0.040 0.180 0.300 V/s
