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THS7319IZSVR ,3-Channel Very Low Power, Low Profile EDTV Video Amplifiers with 6-dB Gain 9-uCSP -40 to 85MAXIMUM RATINGSOver operating free-air temperature range, unless otherwise noted.THS7319 UNITSupply ..
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THS7347IPHP ,3-Channel RGBHV Video Buffer with I2C Control, Monitor Pass-Thru, 2:1 MUX 48-HTQFP -40 to 85FEATURES APPLICATIONS2345• 3-Video Amplifiers for CVBS, S-Video, EDTV,• ProjectorsHDTV Y'P' P' , G' ..
THS7347IPHPG4 ,3-Channel RGBHV Video Buffer with I2C Control, Monitor Pass-Thru, 2:1 MUX 48-HTQFP -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
THS7347IPHPR ,3-Channel RGBHV Video Buffer with I2C Control, Monitor Pass-Thru, 2:1 MUX 48-HTQFP -40 to 85ELECTRICAL CHARACTERISTICS, V = V = 3.3 VA DDR = 150Ω∥ 5 pF to GND for Monitor Output, 19 kΩ || 8 p ..
THS7353PW ,3-Channel Low Power Video Amp w/I2C Control, Selectable Filters, 0dB Gain, 2:1 MUX 20-TSSOP -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
TDA8023TT
Low power IC card interface
General descriptionThe TDA8023 is a complete cost-efficient, low-power analog interface for synchronous or
asynchronous smart cards.It canbe placed between the card and the microcontroller with
very few external components to perform all supply, protection and control functions.
FeaturesI2 C-bus controlled IC card interface in TSSOP28 Supply voltage from 2.7 V to 6.5V Independant supply voltage VDD(INTF) for interface signals with the microcontroller Shutdown input for very low power consumption when the part is not used Power reduction modes when the card is active DC-to-DC converter for VCC generation (capacitive doubler, tripler, or inductive, or
follower automatically selected according to supply voltage and card voltage) 1 specific protected half duplex bidirectional buffered I/O line, with current limitation at
±15 mA, maximum frequency 1 MHz 2 auxiliary card I/O lines controlled by I2 C-bus (C4 and C8) VCC regulation: 5 V, 3 V or 1.8V±8 %, ICC < 55 mA, current spikes of 40 nAs up to MHz, with controlled rise and fall times, filtered overload detection approximately mA, current limitation about 120 mA Thermal and short-circuit protections on all card contacts Automatic activation and deactivation sequences: initiatedby softwareorby hardware
in the event of a short-circuit, card take-off, overheating, VDD or VDD(DCDC) drop-out Enhanced ElectroStatic Discharge (ESD) protection on card side (> 6 kV) 20 MHz clock input Clock generation for the card up to 10 MHz (CLKIN divided by 1, 2, 4 or 5) with
synchronous frequency changes; stop HIGH or LOW or free running 1 MHz in cards
Low-power mode; current limitation on pin CLK (C3) RST signal (C2) with current limitation at 20 mA, controlled by an embedded
programmable CLK pulse counter on asynchronous cards or by a register on
synchronous cards ISO 7816-3, GSM 11.11 and EMV 2000 (payment systems) compatibility Supply voltage supervisor for spike killing during power-on and emergency
deactivation at power-off: threshold internally fixed or set via an external resistor
bridge; pulse width internally fixed or set via an external capacitor Card presence input with 10 ms built-in debouncing system One interrupt signal INT
TDA8023
Low power IC card interface
Rev. 01 — 16 July 2007 Product data sheet
NXP Semiconductors TDA8023
Low power IC card interface Applications Banking terminals Internet terminals Set-top boxes Portable IC card readers
Quick reference data
Table 1. Quick reference dataVDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
SupplyVDD supply voltage on pin VDD 2.7 - 6.5 V
VDD(DCDC) DC-to-DC converter
supply voltage
on pin VDDP 2.7 - 6.5 V
VDD(INTF) interface supply voltage on pin VDDI 1.5 - 6.5 V
IDD supply current Shutdown mode [1] -- 10 μA
Inactive mode; CLKIN LOW or HIGH [1]- - 200 μA
Active mode; VCC =5V; fCLK=5 MHz [1]
capacitive; ICC =5mA - - 15 mA
capacitive; ICC=55 mA - - 200 mA
inductive; ICC =5mA - - 15 mA
inductive; ICC=55 mA - - 150 mA
Power-down mode; VCC =5V; ICC= 100 μA;
CLK stopped; CLKIN HIGHor LOW;
capacitiveor inductive
[1] -- 2 mA
Supply voltage for the card: pin VCC[2]VCC supply voltage Active mode; 2.7V < VDD < 6.5V [3] V card; ICC < 60 mA; VCC = 5V 4.75 5 5.25 V V card; ICC < 55 mA; VCC = 3V 2.80 3 3.15 V
1.8 V card; ICC < 30 mA; VCC = 1.8V 1.65 1.8 1.95 V
Active mode; AC current pulses with< 200 mA, t < 400 ns and f<20 MHz
[3] V card; current pulses of 40 nAs 4.65 - 5.35 V V card; current pulses of 24 nAs 2.76 - 3.24 V
1.8 V card; current pulses of 15 nAs 1.62 - 1.98 V
Vripple(p-p) peak-to-peak ripple
voltage
on VCC; 20 kHz to 200 MHz - - 350 mV
ICC supply current VDD > 2.7V V card; VCC = 0 V to 5V - - −55 mA V card; VCC = 0 V to 3V - - −55 mA
1.8 V card; VCC = 0 V to 1.8V - - −35 mA
NXP Semiconductors TDA8023
Low power IC card interface[1] Sum of currents on pins VDD and VDDI.
[2] Two ceramic multilayer capacitors of minimum 100 nF with low Equivalent Series Resistance (ESR) should be used in order to meet
these specifications.
[3] Output voltage towards the card, including ripple.
Ordering information Block diagram
Generaltdeact deactivation time total sequence 60 80 100 μs
Ptot total power dissipation Tamb = −25 °C to +85°C - - 500 mW
Tamb ambient temperature −40 - +85 °C
Table 1. Quick reference data …continuedVDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Table 2. Ordering informationTDA8023TT TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
NXP Semiconductors TDA8023
Low power IC card interface Pinning information
7.1 Pinning
NXP Semiconductors TDA8023
Low power IC card interface
7.2 Pin description[1] I = input, O = output, S = supply, C = configuration.
[2] PRES is active-HIGH when SPRES = LOW and PRES is active-LOW when SPRES = HIGH.
[3] With integrated pull-up to VDD(INTF).
[4] With integrated pull-up to VCC.
Table 3. Pin descriptionVUP 1 O output of the DC-to-DC converter
INT 2 O Negative-channel Metal Oxide Semiconductor (NMOS) interrupt
to the host (active LOW and open-drain) (see fault detection in
Section 8.7 “Protection”)
SDWN 3 I shutdown and reset input
VDDI 4 S interface positive supply voltage
SDA 5 I/O serial data line to/from the I2 C-bus master (open-drain)
SCL 6 I serial clock line from the I2 C-bus master
SAD0 7 I I2 C-bus address selection
SPRES 8 I select PRES mode[2]
CLKIN 9 I external clock input
GND 10 S ground connection
I/OUC 11 I/O[3] data in/out from/to microcontroller 12 I/O[4] auxiliary input/output to/from the card (contact C8) 13 I/O[4] auxiliary input/output to/from the card (contact C4)
I/O 14 I/O[4] data input/output to/from (contact C7 of) the card
GNDC 15 S ground connection for the card (contact C5)
CLK 16 O clock output to (contact C3 of) the card
VCC 17 S supply voltage for the card (contact C1)
RST 18 O reset output to (contact C2 of) the card
PRES 19 I card presence input with a 10 ms built-in debouncing system[2]
PORADJ 20 I input for changing the power-on reset threshold with an external
resistor bridge.
caseno external resistor bridgeis used,itis mandatoryto
connect this pin to GND to avoid possible perturbations.CDEL 21 C delay capacitor connection for the voltage supervisor (1 ms per nF)
VDD 22 S power supply
SAM 23 C connection for the DC-to-DC converter
GNDP 24 S ground connection for the DC-to-DC converter
SBM 25 C connection for the DC-to-DC converter
VDDP 26 S positive supply for the DC-to-DC converter
SBP 27 C connection for the DC-to-DC converter
SAP 28 C connection for the DC-to-DC converter
NXP Semiconductors TDA8023
Low power IC card interface Functional description
Remark: Throughout this document, it is assumed that the reader is familiar with
ISO 7816 and EMV 2000 terminology.
8.1 Power suppliesThe supply pins for the TDA8023 are VDD and GND. VDD should be in the range from
2.7 V to 6.5 V. The supply voltages VDD, VDD(INTF) and VDD(DCDC) may be applied to the
TDA8023 in any time sequence.
All interface signals with the system controller are referencedtoa separate supply voltage
VDD(INTF) on pin VDDI, that may be lower or higher than VDD.
For generating a supply voltage VCC of 5V±5 % or 3V±5 % used by the card, an
integrated DC-to-DC converter is incorporated. This DC-to-DC converter should be
separately supplied by VDD(DCDC) on pin VDDP and GNDP (from 2.7 V to 6.5 V).
The I2 C-bus signals SDA and SCL may be externally referenced to a voltage higher than
VDD.
8.2 Voltage supervisor
8.2.1 Without external divider on pin PORADJThe voltage supervisor surveys the VDD supply voltage. It is used as Power-On Reset
(POR) and as supply dropout detection during a card session. Supply dropout detection
ensures that a proper deactivation sequence is followed before the voltage is too low. A
reset pulseof durationtW (see Figure4)is used internallyfor maintaining the TDA8023in
the Inactive mode during powering up or powering down of VDD. longas VDDis less than Vth(POR)H the TDA8023 will remain inactive whatever the levels
on the command lines are. This also lasts for the duration of tW after VDD has reached a
level higher than Vth(POR)H. When VDD falls below Vth(POR)L an automatic deactivation
sequence of the contacts is performed.
In this case (no external resistor bridge) it is mandatory to connect pin PORADJ to GND.
NXP Semiconductors TDA8023
Low power IC card interface
8.2.2 With external divider on pin PORADJIf an external resistor bridge is connected to pin PORADJ (R1 to GND and R2 to VDD as
shown in Figure 1 and Figure 2), then the internal threshold voltages and the internal
hysteresis voltage are overridden by externally determined ones.
The voltage on pin PORADJ is:
where
The thresholds that are applied by the TDA8023 to this voltage VPORADJ are:
(rising)
(falling)
where
Vbg(int) = 1.25 V (typ)
Vhys = 60 mV (typ)
The thresholds and hysteresis on VDD can then be calculated from:
(rising)
(falling)
The minimum threshold voltage Vth(POR)L should be chosen higher than 2V.
Input PORADJ is biased internally with a pull-down current source of 4 μA which is cut
when the voltageon this pin exceeds1V. This ensures that after detectionof the external
bridge during power-on, the input current on this pin does not cause inaccuracy of the
bridge voltage.
8.2.3 External capacitor on pin CDELThe width of the POR pulse (tW) is externally set by the value of the CDEL capacitor: the
typical value is 1 ms per 2 nF . Usually CCDEL = 22 nF , therefore tW = 10 ms (typ). PORADJ R1 R2+-------------------- VDD× kVDD×== R1 R2+--------------------=thH() PORADJ() Vbgint()hys-----------+=thL() PORADJ() Vbgint()hys-----------–=th POR()HthH() PORADJ() --------------------------------------bgint()hys-----------+ -----------------------------------------==th POR()LthL() PORADJ() -------------------------------------bgint()hys-----------– -----------------------------------------==hys POR()hys-----------=
NXP Semiconductors TDA8023
Low power IC card interface
8.2.4 Shutdown modeWhen pin SDWN = HIGH, the TDA8023 is in Shutdown mode; the consumption in this
mode is less than 10 μA. The I2 C-bus is unresponsive.
If the card is extracted or inserted when the TDA8023 is in Power-down mode, pin INT
becomes LOW and stays LOW as long as pin SDWN = HIGH.
When pin SDWN is pulled LOW, the TDA8023 leaves Shutdown mode and executes a
complete power-on reset sequence.
8.3I2 C-busA 400 kHz I2 C-bus slave interface is used for configuring the TDA8023 and reading the
status.
8.3.1I2 C-bus protocolThe I2 C-bus is for 2-way 2-line communication between ICs or modules. The serial bus
consists of two bidirectional lines: one for data signals (SDA) and one for clock signals
(SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy
During data transfer, the data line must remain stable whenever the clock line is
HIGH; changes in the data line while the clock line is HIGH will be interpreted as
control signals
8.3.2 Bus conditionsThe following bus conditions have been defined.
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer —A changein the stateof the data line from HIGHto LOW, while the
clock is HIGH, defines the START condition.
Stop data transfer —A changein the stateof the data line from LOWto HIGH, while the
clock is HIGH, defines the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock signal.
There is one clock pulse per bit of data.
8.3.3 Data transferEach data transfer is initiated with a ST ART condition and terminated with a STOP
condition (see Figure 7). See Table 15 for timing information.
Data transfer is unlimited in the Read mode. The information is transmitted in bytes and
each receiver acknowledges with a 9th bit.
NXP Semiconductors TDA8023
Low power IC card interfaceWithin theI2 C-bus specifications,a Standard mode (100 kHz clock rate) anda Fast-speed
mode (400 kHz clock rate) are defined. The TDA8023 operates in both Fast-speed and
Standard modes. definition,a device that sendsa signalis calleda transmitter anda device that receives
the signalis calleda receiver. The device that controls the signalis called the master. The
devices that are controlled by the master are called slaves.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put
on the bus by the transmitter. The master generates an extra acknowledge-related clock
pulse. The slave receiver that is addressed is obliged to generate an acknowledge after
the reception of each byte.
The master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge-related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an end datato the slave transmitterby not generatingan acknowledgeon the last byte that has
been clocked outof the slave.In this event, the transmitter must leave the data line HIGH
to enable the master generation of the STOP condition.
8.3.4 Device addressingEach TDA8023 has 2 different addresses, one for each of its two registers.
Two TDA8023s maybe usedin parallel dueto the address selection pin SAD0. Pin SAD0
is externally hardwired to pin VDD or pin GND. The voltage on pin SAD0 sets address bit
b2: HIGH sets bit b2 to logic 1, LOW resets b2 to logic 0.
Address bit b1 selects Register 0 or Register 1.
Address bit b0 defines Read or Write operation: 1 means Read, 0 means Write.
The addresses for the TDA8023 are shown in Table 4 andT able5.
Table 4. Device addressing 1 0 0 0 SAD0 0/1 R/W
Table 5. I2 C-bus addresses for write mode 40h 42h 44h 46h
NXP Semiconductors TDA8023
Low power IC card interface
8.3.5 RegistersWhenat least oneof the bits PRESL, PROT, MUTE and EARLYis set, pin INT goes LOW
until the status byte has been read. After power-on, bit SUPL is set until the status byte
has been read, and pin INT = LOW until the voltage supervisor becomes inactive.
Table 6. Table of registers ACTIVE VCC1V8 TEST D7 C15 C7 EARLY I/OEN RSTIN D6 C14 C6 MUTE REG1 C8 D5 C13 C5 PROT REG0 C4 D4 C12 C4 SUPL PDWN CLKPD2 D3 C11 C3 CLKSW 5V/3VN CLKPD1 D2 C10 C2 PRESL WARM CLKDIV2 D1 C9 C1 PRES START CLKDIV1 D0 C8 C0
Table 7. Status - Register 0 in Read mode bit description ACTIVE set if the card is active; reset if the card is inactive EARLY set during AnswerTo Reset (ATR) when the selected card has answered
too early MUTE set during ATR when the card has not answered during the ISO 7816
time slots PROT set when an overload or an overheating has occurred during a session;
reset when the status has been read SUPL set when the voltage supervisor has signalled a fault; reset when the
status has been read CLKSW set when the TDA8023 is in Power-down mode and the clock has
changed PRESL set when the card has been inserted or extracted; reset when the status
has been read PRES set when the card is present; reset when the card is not present
Table 8. Command - Register 0 in Write mode bit description VCC1V8 1: VCC = 1.8V
0: VCC is defined by bit 5V/3VN
this bit can not change if bit START is logic 1 I/OEN 1: signal on pin I/OUC is transferred to pin I/O
0: pin I/OUC and pin I/O are high-impedance
5 and 4 REG[1:0] selection of subaddress in Register 1 (see Table9, 10, 11 and 12)
NXP Semiconductors TDA8023
Low power IC card interface[1] Synchronousor asynchronous cards managementare defined whenbit STARTis set:the TDA8023willbe
in asynchronous cards management when bit RSTIN = 1 when bit START is set to logic 1. PDWN 1: applies on pin CLK the frequency that is defined by bits CLKPD[2:1]
and reduces power consumption(in Synchronous mode); thisbit can not
change if bit START is logic 1 5V/3VN 1: VCC = 5V
0: VCC = 3V
this bit can not change if bit START is logic 1 WARM 1: initiates a warm reset procedure
this bit will be automatically reset by hardware when bit MUTE is set to
logic 1 START 1: initiates an activation sequence and a cold reset procedure (only if bit
SUPL = 0 and the bit PRES = 1)
0: initiates a deactivation sequence
Table 9. R1_00 - Register 1 subaddress 00 in Read/Write mode bit description TEST 1: the circuit is in Test mode
0: the circuit is in Operational mode RSTIN[1] defines the voltage on pin RST:
1: VCC
0: 0V C8 defines the voltage on pin C8:
1: VCC
0: 0V C4 defines the voltage on pin C4:
1: VCC
0: 0V
3 and 2 CLKPD[2:1] clock pulse definition:
00: CLK stop LOW
01: CLK stop HIGH
10: frequency on pin CLK: fCLK = fosc(int) / 2
11: no change
in Synchronous mode bit CLKPD2 is always logic 0 by hardware and bit
CLKPD1 controls the voltage on pin CLK:
1: VCC
0: 0V
1 and 0 CLKDIV[2:1] clock divider:
00: fCLK = fCLKIN
01: fCLK = fCLKIN / 2
10: fCLK = fCLKIN / 4
11: fCLK = fCLKIN / 5
in Synchronous mode, bits CLKDIV[2:1] are always 00 by hardware
Table 8. Command - Register 0 in Write mode bit description …continued
NXP Semiconductors TDA8023
Low power IC card interfacebit RSTIN=0 whenbit STARTis setto logic1, then pin RSTis controlledbybit RSTIN.
Else, pin RST = LOW during a number of CLK periods, defined by the 16-bit CLK count
register C[15:0], and goes HIGH afterwards.
There are two synchronous card management types:
Ifbit PDWN=0 whenbit ST ARTis setto logic1, then the output CLKis controlledby
input CLKIN (without division)
Ifbit PDWN=1 whenbit ST ARTis setto logic1, then the output CLKis controlledby
bit CLKPD1
8.4 DC-to-DC converterFor generating a supply voltage VCC of 5V±5 % or 3V±5 % to the card, an integrated
voltage converteris incorporated. This DC-to-DC converter shouldbe separately supplied
by VDD(DCDC) on pin VDDP and GNDP (from 2.7 V to 6.5 V).
The DC-to-DC conversion is either capacitive or inductive, according to the external
components (automatic detection).
8.4.1 Capacitive configurationThe external components are three 100 nF capacitors (low-ESR), see Figure1.
The DC-to-DC converter is either tripler, doubler or follower according to the respective
values of VCC and VDD(DCDC). An hysteresis of 100 mV is present on both thresholds:
Follower:
If VCC = 5 V and VDD(DCDC) > 5.8V
If VCC = 3 V and VDD(DCDC) > 4V
If VCC = 1.8V
Table 10. R1_01 - Register 1 subaddress 01 in Read/Write mode bit description7 to 0 D[7:0] 8-bit programmable CLK period count register;
range: 0 to 255;
initial value: 170
Table 11. R1_10 - Register 1 subaddress 10 in Read/Write mode bit description7 to 0 C[15:8] 8-bit programmable CLK period count register;
range in combination with C[7:0]: 0 to 65535;
initial value: 164
Table 12. R1_11 - Register 1 subaddress 11 in Read/Write mode bit description7 to 0 C[7:0] 8-bit programmable CLK period count register;
range in combination with C[15:8]: 0 to 65535;
initial value: 116
NXP Semiconductors TDA8023
Low power IC card interface Doubler:
If VCC = 5 V and VDD(DCDC) = 4 V to 5.8V
If VCC = 3 V and VDD(DCDC) < 4V
Tripler:
If VCC = 5 V and VDD(DCDC) < 4V
8.4.2 Inductive configurationThe external components are a diode, a coil of 6.8 μH and a capacitor of 4.7 μF (see
Figure 2). In this configuration the DC-to-DC converter acts as follows.
If VCC = 5 V then VVUP is regulated at 5.5V
If VCC = 3 V then VVUP is regulated at 4V
If VCC = 1.8 V then the DC-to-DC converter acts as a follower
8.5 VCC bufferIn all modes (follower, doubler, tripler), the DC-to-DC converter is able to deliver 60 mA
over the whole VDD range (2.7 V to 6.5 V) or 90 mA if VDD > 3V.
The currenton the VCC buffer hasan internal limitationof around90 mA. When this limitis
reached, an automatic deactivation sequence is performed.
The VCC voltage should be decoupled with a low-ESR capacitor between 100 nF and
168 nF . If the card socket is not very close to the TDA8023, one capacitor should be
placed near the TDA8023, and a second one near the card contacts.
8.6 Sequencer and clock counterThe sequencer takes careof ensuring activation and deactivation sequences accordingto
ISO 7816 and EMV 2000, even in case of emergency (card removal during transaction,
supply dropout or hardware problem).
The sequencer is clocked with an internal oscillator.
The activationofa cardis initiatedby settingbit STARTin the Command register, whichis
only possible if the card is present and if the voltage supervisor is not active. The
activation sequence is described in Section 8.6.1.
The deactivation is initiated either by the system controller or automatically in case of a
hardware problem or a supply dropout. The deactivation sequence is described in
Section 8.6.2.
Outside a session, card contacts are forced low-impedance with respect to pin GNDC.
8.6.1 Activation sequenceWhen the cardis inactive, pins VCC, CLK, RST and I/O are LOW, whichis low-impedance
with respect to pin GNDC. The DC-to-DC converter is stopped.
NXP Semiconductors TDA8023
Low power IC card interfaceWhen everything is satisfactorily present (voltage supply, card present, no hardware
problems) the system controller may initiate an activation sequence of a present card: The internal oscillator changes to its high frequency (t0, see Figure5). The DC-to-DC converter is started (t1). VCC starts rising from 0 V to 5 V, 3 V or 1.8 V with a controlled rise time (t2). The voltage on pin I/O rises to VCC, due to integrated 14 kΩ pull-ups to VCC (t3). CLK is sent to the card and pin RST is enabled (t4 = tact).
During the activation sequence, the answer from the card (ATR) is monitored and the
steps are the following: If a start bit is detected on pin I/O during the first 200 CLK pulses, then it is simply
ignored, and the CLK count goes on.Ifa startbitis detected whilst pin RST= LOW (between 200 and 42100 CLK pulsesor
the value written in C[15:0]), then the bits EARLY and MUTE are set in the Status
register. Pin RST will remain LOW.Itisupto the softwareto decide whetherto accept
the card or not. If no start bit has been detected within 42100 CLK pulses, then pin RST is toggled to
HIGH (t5).If, again,a startbitis detected within 370 CLK pulses (200+ 170or the value defined
in D[7:0]), bit EARLY in the Status register is set. If the card does not answer within 42100 new CLK pulses, then bit MUTE in the
Status register is set.If the card answers within the correct time window, then the CLK countis stopped and
the system controller can send commands to the card.
The sequencer is clocked by which leads to a time interval T = 25 μs (typical).
Thus s to , , and .oscint()-------------------1 0= T------t2 t=1-------+ t3 t1= 7T-------+ t4 t=1 4T+
NXP Semiconductors TDA8023
Low power IC card interface
8.6.2 Deactivation sequenceWhen the session is completed, the microcontroller resets bit START to logic 0 (t10, see
Figure 6). The circuit then executes an automatic deactivation sequence: Card reset: pin RST falls to LOW (t11). CLK is stopped (t12). Pin I/O falls to 0 V (t13). Pin VCC falls to 0 V with a controlled slew rate (t14). The DC-to-DC converter is stopped and pins CLK, RST , VCC and I/O become
low-impedance with relation to GNDC (t15). The internal oscillator changes to its low frequency (t15). , , and .
The deactivation time tdeact is the time that VCC needs for going down to less than 0.4V,
counted from the moment bit START is reset.
8.7 ProtectionAll card contacts are protected against any short with any other card contact.
The currents on various pins are limited:
on pin CLK: limited to ±70 mA
on pin I/O: limited to ±10 mA (typical value)
on pin RST: limited (only when this pin is LOW) to ±20 mA
on pin VCC: limited to 90 mA
If any of these currents exceeds its limit, an emergency deactivation sequence is
performed: pin INT is pulled LOW and bit PROT in the Status register is set.11 t= 10------+ t12 t=11---+ t13 t=11 T+ t14 t= 11-------+ t15 t11= 7T-------+
NXP Semiconductors TDA8023
Low power IC card interfaceIn case of overcurrent on pin VCC, removal of the card during a session, overheating,
supply dropout, DC-to-DC outof limits,or overcurrenton pin RST, the TDA8023 performs
an automatic emergency deactivation sequence on the card, resets bit ST ART and pulls
pin INT LOW.
Limiting values[1] Everypin withstandsthe ESD test accordingto MIL-STD-883C class3for card contacts, class2forthe remaining. Method 3015 (HBM;
1500 Ω; 100 pF) defines 3 pulses positive and 3 pulses negative on each pin referenced to ground.
10. Thermal characteristics
Table 13. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage on pin VDD −0.5 +6.5 V
VDD(DCDC) DC-to-DC converter
supply voltage
on pin VDDP −0.5 +6.5 V
VDD(INTF) interface supply voltage on pin VDDI −0.5 +6.5 V
VIH HIGH-level input voltage on pins SAP, SAM, SBP , SBM, VUP −0.5 +7.5 V
on pins SDA, SCL −0.5 +6.5 V
on all other pins −0.5 VDD+ 0.5V
Ptot total power dissipation Tamb = −25 °C to +85°C - 500 mW
Tstg storage temperature −55 +150 °C junction temperature - 150 °C
Vesd electrostatic discharge
voltage
Human Body Model (HBM) [1]
on card pins I/O, VCC, CLK, GNDC, PRES, RST −6+6 kV
on all other pins −2+2 kV
Machine Model (MM)
all pins, excluding card pins −200 +200 V
Table 14. Thermal characteristicsRth(j-a) thermal resistance from junction to ambient in free air 100 K/W
