TDA7580 ,FM/AM DIGITAL IF SAMPLING PROCESSORfeatures complete functions to have the output data available2through either I C or SPI interface. ..
TDA7590 ,Digital signal processing IC for speech and audio applicationsElectrical characteristics for I/O pins . . . . 165 24 bit DSP core . . . . 176 Memories ..
TDA7701 ,Battery-operated fully integrated FM tunerAPPLICATIONS■ INTEGRATED LNA (WITH AGC) AND IMAGE REJECTION MIXERTFBGA40■ LOW-IF ARCHITECTURE WITH ..
TDA7705 ,Highly integrated tunerAbsolute maximum ratings . 16Table 5. Thermal data . . . . 16Table 6. General key param ..
TDA7705TR ,Highly integrated tunerFeatures■ Fully integrated VCO for world tuning■ High performance PLL for fast RDS system■ AM/FM m ..
TDA7705TR ,Highly integrated tunerElectrical characteristics . . . . . . 173.4.1 FM - section . . . . . . 173.4.2 AM - secti ..
THS4221DBVR ,Low-Distortion High-Speed Rail-to-Rail Output Operational AmplifierFEATURES APPLICATIONS Low-Voltage Analog-to-Digital ConverterPreamplifier Rail-to-Rail Output Swi ..
THS4221DBVRG4 , LOW-DISTORTION, HIGH-SPEED, RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS
THS4222D ,Low-Distortion High-Speed Rail-to-Rail Outputmaximum ratings under any condition is limited bythe constraints of the silicon process. Stresses a ..
THS4222DGK ,Low-Distortion High-Speed Rail-to-Rail OutputMAXIMUM RATINGSInstruments recommends that all integrated circuits be(1)over operating free-air tem ..
THS4222DGN ,Low-Distortion High-Speed Rail-to-Rail OutputFEATURES APPLICATIONS Low-Voltage Analog-to-Digital ConverterPreamplifier Rail-to-Rail Output Swi ..
THS4222DR ,Low-Distortion High-Speed Rail-to-Rail OutputELECTRICAL CHARACTERISTICS V = ±5 V, R = 499 Ω , and G = 1 unless otherwise notedS LTYP OVER TEM ..
TDA7580
FM/AM DIGITAL IF SAMPLING PROCESSOR
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TDA7580July 2002 FM/AM IF SAMPLING DSP ON-CHIP ANALOGUE TO DIGITAL
CONVERTER FOR 10.7MHz IF SIGNAL
CONVERSION SOFTWARE BASED CHANNEL EQUALIZATION FM ADJACENT CHANNEL SUPPRESSION RECEPTION ENHANCEMENT IN MULTIPATH
CONDITION STEREO DECODER AND WEAK SIGNAL
PROCESSING 2 CHANNELS SERIAL AUDIO INTERFACE
(SAI) WITH SAMPLE RATE CONVERTERI2 C AND BUFFER-SPI CONTROL INTERFACES RDS FILTER, DEMODULATOR & DECODER INTER PROCESSOR TRANSPORT
INTERFACE FOR ANTENNA AND TUNER
DIVERSITY FRONT-END AGC FEEDBACK
DESCRIPTIONThe TDA7580 is an integrated circuit implementing
an advanced mixed analogue and digital solution to
perform the signal processing of a AM/FM channel.
The HW&SW architecture has been devised so to
have a digital equalization of the FM/AM channel;
hence a real rejection of adjacent channels and any
other signals interfering with the listening of the de-
sired station. In severe Multiple Paths conditions, the
reception is improved to get the audio with high qual-
ity.
PRODUCT PREVIEWFM/AM DIGITAL IF SAMPLING PROCESSOR
BLOCK DIAGRAM
TDA7580 2/31
DESCRIPTION (continued)The algorithm is self-adaptive, thus it requires no “on-the-field” adjustments after the parameters optimization.
The chip embeds a Band Pass Sigma Delta Analogue to Digital Converter for 10.7MHz IF conversion from a
“tuner device” (it is highly recommended the TDA7515).
The internal 24bit-DSP allows some flexibility in the algorithm implementation, thus giving some freedom for
customer required features. The total processing power offers a significant headroom for customer’s software
requirement, even when the channel equalization and the decoding software is running. The Program and Data
Memory space can be loaded from an external non volatile memory via I2 C or SPI.
The oscillator module works with an external 74.1MHz quartz crystal. It has very low Electro Magnetic Interfer-
ence, as it introduces very low distortion, and in any case any harmonics fall outside the Radio bandwidth.
The companion tuner device receives the reference clock through a differential ended interface, which works
off the Oscillator module by properly dividing down the master clock frequency. That allows the overall system
saving an additional crystal for the tuner.
After the IF conversion, the digitized baseband signal passes through the Base Band processing section, either
FM or AM, depending on the listener selection. The FM Base Band processing comprises of Stereo Decoder,
Spike Detection and Noise Blanking. The AM Noise Blanking is fully software implemented.
The internal RDS filter, demodulator and decoder features complete functions to have the output data available
through either I2 C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in back-
ground and in parallel with other DSP processing. This mode (RDS-only) allows current consumption saving for
low power application modes.
An I2 C/SPI interface is available for any control and communication with the main micro, as well as RDS data
interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the
DSP task and frequently respond to the interrupt from the control interface.
Serial Audio Interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either
master or slave. The flexibility of this module gives a wide choice of different protocols, including I2 S. Two fully
independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose
digital audio processor.
A fully Asynchronous Sample Rate Converter (ASRC) is available as a peripheral prior to sending audio data
out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconver-
sion to any external rate.
An Inter Processor Transport Interface (HS3 I, High Speed Synchronous Serial Interface) is also available for a
modular system which implements Dual Tuner Diversity, thus enhancing the overall system performance. It is
about a Synchronous Serial Interface which exchanges data up to the MPX rate. It has been designed to reduce
the Electro Magnetic Interference toward the sensitive analogue signal from the Tuner.
General Purpose I/O registers are connected to and controlled by the DSP, by means of memory map.
A Debug and Test Interface is available for on-chip software debug as well as for internal registers read/write
operation.
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TDA7580
ABSOLUTE MAXIMUM RATINGSWarning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.
Note:1. VDD3 refers to all of the nominal 3.3V power supplies (VDDH, VOSC, VDDSD). VDD refers to all of the nominal 1.8V power supplies
(VDD, VMTR). During Normal Mode operation VDD3 is always available as specified During Fail-safe Mode operation VDD3 may be not available.
THERMAL DATA
TDA7580 4/31
PIN CONNECTION (Top view)
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TDA7580
PIN DESCRIPTION
TDA7580 6/31
PIN DESCRIPTION (continued)
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TDA7580
PIN DESCRIPTION (continued)
TDA7580 8/31
PIN DESCRIPTION (continued)
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TDA7580
PIN DESCRIPTION (continued)
I/O TYPEP: Power Supply from Voltage regulator
G: Power Ground from Voltage regulator
A: Analogue I/O
I: Digital Input
O: Digital Output
B: Bidirectional I/O
I/O DEFINITION AND STATUSZ: high impedance (input)
O: logic low output
X: undefined output
1: logic high output
Output PP: Push-Pull/ OD: Open-Drain
TDA7580 10/31
RECOMMENDED DC OPERATING CONDITIONSNote:1. VDDH, VOSC, VDDSD are also indicated in this document as VDD3. All others as VDD.
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
11/31
TDA7580Note:1. The leakage currents are generally very small, <1nA. The value given here, 1μA, is the maximum that can occur after an Electro-
static Stress on the pin. On pins:17 to 20,23 to 26,29 to 33,36 to 39,42 to 46,49 to 52,55 to 58. On pins: 13 and 14. Same check on the analogue pin 15 (phisically without pull-up-down) On pins:25, 26,32,49,50,55,56 On pins:17 to 20,23 to 24,29 to 31,33,36 to 39,42 to 46,51, 52,57, 58
LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICSNote:1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability.
HIGH VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICSNote:1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability X=4mA for pins 17 to 20,29,30,32,36 to 39,42 to 46; X=8mA for pins 23 to 26,49 to 52,55 to 58.
CURRENT CONSUMPTION
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
TDA7580 12/31
Note: 74.1MHz internal DSP clock, at Tamb = 25°C. Current due to external loads not included.
OSCILLATOR CHARACTERISTICSNotes:1. The accuracy of this figure only depends on the quartz frequency precision: high stability oscillator
QUARTZ CHARACTERISTICS
DSP CORE
FM STEREO DECODER CHARACTERISTICS
CURRENT CONSUMPTION (continued)
13/31
TDA7580
SAMPLE RATE CONVERTERMCK = 18.525MHz, Fsin/Fsout = 0.820445366
TDA7580 14/31
POWER ON TIMING
Figure 1. Power on and boot sequence using I2C
Figure 2. Power on and boot sequence using SPI
15/31
TDA7580
TDA7580 16/31
SAI INTERFACE
Figure 3. SAI TimingsNote TDSP = DSP master clock cycle time = 1/FDSP
Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
