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TDA7565
QUAD POWER AMPLIFIER WITH BUILT-IN VOLTAGE CONVERTER
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TDA7565September 2003 DMOS POWER OUTPUT NON-SWITCHING HI-EFFICIENCY
AMPLIFIER SWITCHING HIGH EFFICIENCY VOLTAGE
CONVERTER HIGH OUTPUT POWER CAPABILITY 4x60W
EIAJ/4Ω FULL I2 C BUS DRIVING:
–ST-BY INDEPENDENT FRONT/REAR SOFT PLAY/MUTE SELECTABLE GAIN 26dB - 12dB (FOR
LOW NOISE LINE OUTPUT FUNCTION) HIGH EFFICIENCY ENABLE/DISABLE VOLTAGE CONVERTER ENABLE/DISABLE REGULATED VOLTAGE SELECTION SWITCHING FREQUENCY SELECTION HARDWARE MUTE FUNCTION FULL FAULT PROTECTION DC OFFSET DETECTION FOUR INDEPENDENT SHORT CIRCUIT
PROTECTION CLIPPING DETECTOR WITH SELECTABLE
THRESHOLD (1%/10%) VIA I2 C BUS
DESCRIPTIONThe TDA7565 is a new BCD technology QUAD
BRIDGE type of car radio amplifier in Flexiwatt27
package specially intended for car radio applica-
tions. Thanks to the DMOS output stage the
TDA7565 has a very low distortion allowing a clear
powerful sound. The built-in voltage converter
control block assures a very high output power
with an extremely low number of added compo-
nents.The dissipated power under average listen-
ing condition is alligned to the conventional
solutions (4x40W).
PRODUCT PREVIEWQUAD POWER AMPLIFIER WITH BUILT-IN
VOLTAGE CONVERTER
BLOCK DIAGRAM
TDA7565 2/10
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
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TDA7565
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, VS = 13.5V; RL = 4Ω; f = 1KHz; Voltage converter Disabled (VCOff); Tamb = 25°C; unless
otherwise specified.)
TDA7565 4/10
Figure 1. Demoboard Schematic
ELECTRICAL CHARACTERISTICS (continua)(Refer to the test circuit, VS = 13.5V; RL = 4Ω; f = 1KHz; Voltage converter Disabled (VCOff); Tamb = 25°C; unless
otherwise specified.)
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TDA75652
C BUS INTERFACEData transmission from microprocessor to the TDA7565 and viceversa takes place through the 2 wires I2 C BUS inter-
face, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data ValidityAs shown by fig. 2, the data on the SDA line must be stable during the high period of the clock.
The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop ConditionsAs shown by fig. 3 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte FormatEvery byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
AcknowledgeThe transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 22).
The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDAline is stable LOW during this clock pulse.
* Transmitter
master (μP) when it writes an address to the TDA7565
slave (TDA7565) when the μP reads a data byte from TDA7565
** Receiver
slave (TDA7565) when the μP writes an address to the TDA7565
master (μP) when it reads a data byte from TDA7565
Figure 2. Data Validity on the I2
C BUS
Figure 3.
Figure 4.
TDA7565 6/10
SOFTWARE SPECIFICATIONSAll the functions of the TDA7565 are activated by I2 C interface.
The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from μP to TDA7565) or
read instruction (from TDA7565 to μP).
If R/W = 0, the μP sends 2 "Instruction Bytes": IB1 and IB2.
IB1
IB2
