TDA7513T ,SINGLE-CHIP FM/AM TUNER WITH STEREO DECODER AND AUDIO PROCESSORfeatures front-end processing, includ-mute function are included to handle sourceing the digital tu ..
TDA7515 ,RF-FRONTEND FOR AM/FM-DSP-CARRADIOS WITH IF SAMPLINGBLOCK DIAGRAMoptional222AGC ADJIF 10.7MHz2FMAGCDAGCQIPM2BusAGC InterfaceTV1 TV22SupplyAMPMDIV :1/:2 ..
TDA7515TR , RF front-end for AM/FM-DSP car radios with IF sampling
TDA7518 ,MULTICHIP MODULE FOR CAR-RADIO APPLICATIONSAPPLICATIONSTQFP144■ IF COUNTER WITH SEARCH-STOP SIGNAL■ IF BANDWIDTH CONTROL FUNCTIONTable 1. Orde ..
TDA7519 ,MULTICHIP MODULE FOR CAR-RADIO APPLICATIONSAPPLICATIONSPRELIMINARY DATA■ HIGH-PERFORMANCE SIGNAL PROCESSOR FOR CAR-RADIO
TDA7529 ,RF front-end for AM/FM DSP car-radio with IF samplingAbsolute maximum ratings . . . . 194.2 Thermal data . . . . . . 194.3 General key paramet ..
THS4052CDGNR ,70-MHz Low-Cost Voltage-Feedback Amplifier, DualSLOS238D − MAY 1999 − REVISED AUGUST 2008CAUTION: The THS4051 and THS4052 provide ESD protection ci ..
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TDA7513T
SINGLE-CHIP FM/AM TUNER WITH STEREO DECODER AND AUDIO PROCESSOR
1/59
TDA7513TJune 2004
FEATURES AM/FM TUNER FOR CAR-RADIO INTEGRATED TUNING PLL VARIABLE-BANDWITH FM IF FILTER (ISS) FULLY INTEGRATED FM STEREO
DECODER FULLY INTEGRATED FM NOISE BLANKER HIGHLY INTEGRATED AUDIO PROCESSOR
DESCRIPTIONThe TDA7513T is the first device for car-radio ap-
plications that combines full RF front-end func-
tions with audio-processing capabilities.
As far as FM and AM functions are concerned , the
TDA7513T features front-end processing, includ-
ing the digital tuning PLL, IF processing with de-
modulation and variable-bandwidth IF filtering
(ISS), stop station and quality detection functions,
FM stereo decoding by means of a fully-integrat-
ed, adjustment-free dedicated PLL and, finally, FM
noise blanking. The FM stereo decoder and noise
blanker functions are realized entirely without ex-
ternal components.
The audio processor section comprises input se-
lectors for two quasi-differential external sources,
volume control, tone control (bass, mid and tre-
ble), balance and fading control to drive four out-
put channels. A soft mute function and an RDS
mute function are included to handle source
change as well as RDS AF search without abrupt
changes in the audio level.
Most of the parameters in the front-end section are2 Cbus-driven and therefore under the control of
the car-radio maker. The I2 C bus allows further-
more the user to realize the full electric alignment
of all the external coils, therefore removing the
need for hand-made or mechanical adjustments.
SINGLE-CHIP FM/AM TUNER WITH STEREO DECODER
AND AUDIO PROCESSOR
Figure 2. Pins ConnectionREV. 1
TDA7513T BLOCK DIAGRAM
Figure 3. Tuner Section
Figure 4. Stereo Decoder / Audio Processor Section
3/59
TDA7513T
Table 2. Pin Description
TDA7513T
Table 2. Pin Description (continued)
5/59
TDA7513T ELECTRICAL CHARACTERISTCS
4.1 FM (VCC = 8V; Tamb = 25°C; Vsg = 60dBµV; fc = 98.1MHz; fdev = 40kHz; fmod = 1kHz unless otherwise specified)
Table 3. General (audioprocessor all flat and stereo decoder input gain = 4dB )
Table 4. Mixer1
Table 5. Front-end Adjustment (VRFadj and VANTadj referred to VLFOUT)
TDA7513T
Table 6. AGC (wide AGC input connected to RFT primary through 10pF and 1KΩ)
Table 7. IF Amplifier 1 (Input at FMIFAMP1IN, fc = 10.7MHz, no mod) (Output at FMIFAMP1OUT loadedwith 330Ω) (antenna level = FMIFAMP1IN – 31dB)
Table 8. IF Amplifier 2 (Input at FMIFAMP2IN, fc = 10.7MHz, no mod) (Output at FMIFAMP2OUT loadedwith 330Ω) (antenna level = FMIFAMP2IN – 45dB)
Gain MUST BE SET to 14dB for ISS operation.
7/59
TDA7513T
Table 9. Field-strength Meter (Input at FMMIX2IN; fc = 10.7MHz, no mod) (antenna level = V67 – 49dB)
Table 10. MPX output (output at TUNEROUT)
Table 11. Field-strength Stop Station (Input at FMMIX2IN – fc = 10.7MHz, no mod) (antenna level = V69 – 49dB)
Table 12. Soft Mute
TDA7513T
Table 13. ISS Filter (FMIF1AMP1 gain MUST be set to 14dB) ** if ISS function is not used, SEEK must be set to “ON” in FM
AM (VCC = 8V; Tamb =25°C; Vsg = 74dBµ V,emf; fc = 999kHz; 30% modulation; fmod = 400Hz unless oth-
erwise specified).
Table 14. General (with 20pF/65pF dummy antenna; input levels @ SG,emf; output @ audioprocessoroutput; audioprocessor all flat; stereo decoder input gain = 5.75dB)
9/59
TDA7513T
Table 15. Mixer1 (Input at AMMIX1IN+, no mod)
Table 16. AGC1 (Wide AGC input = AM Mixer1 input; Narrow AGC input = AM Mixer2 input; Ultra NarrowAGC input = AM IF2 Amp input; fWAGCin = 999kHz, fNAGCIN = 10.7MHz, fUNAGCin =
450kHz)
Table 17. Mixer2 (Input at AMMIX2IN, fc = 10.7MHz, no mod)
TDA7513T
Table 18. IF2 amplifier (Input at AMIF2AMPIN, fc = 450kHz, no mod)
Table 19. AGC2
Table 20. Audio output (output at TUNEROUT, 2.7k Ω load)
Table 21. Field-strength Meter (Input at AMIF2AMPIN; fc = 450 kHz, no mod) (SG,emf level = V65 – 29dB)
11/59
TDA7513T
4.2 OSCILLATORS (VCC = 8V; Tamb =25°C)
Table 22. VCO
Table 23. XTAL
Table 24. Audio Processor (VS = 8V; Tamb = 25°C; RL = 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified)
TDA7513T
Table 24. Audio Processor (continued)(VS = 8V; Tamb = 25°C; RL = 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified)
13/59
TDA7513T1) The SM pin is active low (Mute = 0)
2) See note in Programming Part
Table 24. Audio Processor (continued)(VS = 8V; Tamb = 25°C; RL = 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified)
TDA7513T
4.3 STEREO DECODER.
Table 25. Stereo Decoder (Vcc = 8V; deemphasis time constant = 50µs, VMPX = 305mVrms (75kHz deviation), fm= 1kHz, Gv = 4dB,
Tamb = 27°C; unless otherwise specified)
15/59
TDA7513T
4.4 NOISE BLANKER
Table 26. Noise Blanker
Table 25. Stereo Decoder (continued)(Vcc = 8V; deemphasis time constant = 50µs, VMPX = 305mVrms (75kHz deviation), fm= 1kHz, Gv = 4dB,
Tamb = 27°C; unless otherwise specified)
TDA7513T (c) = by design/characterization functionally guaranteed through dedicated test mode structure
(0) = All Thresholds are measured using a pulse with TR =2ms,THIGH = 2ms and TF = 10ms. The repetition rate must not icrease the PEAK
voltage.
1) NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold
2) NAT represents the Noiseblanker Byte bit pair D4, D3 for the noise controlled triggeradjustment
3) OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector
4) FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control
5) BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment
6) NRD represents the Configuration-Byte bit pair D1, D0 for the noise rectifier discharge-adjustment
7) PCH represents the Stereodecoder-Byte bit D5 for the noise rectifier charge-current adjustment
8) MPNB represents the HighCut-Byte bit D7 and the Fieldstrength-Byte D7 for the noise rectifier multipath adjustment
4.5 MULTIPATH AND QUALITY DETECTORS
Table 27. Multipath And Quality Detectors
Table 26. Noise Blanker (continued)
17/59
TDA7513T FUNCTIONAL DESCRIPTION
5.1 FM Section
5.1.1 Mixer1, AGC and 1st IFMixer1 is a wide dynamic range stage with low noise and large input signal performance. The mixer1 tank
center frequency can be adjusted by software (IF1T). The AGC operates on different sensitivities and
bandwidths (FMAGC) in order to improve the input sensitivity and dynamic range (keyed AGC). The output
signals of AGC are controlled voltage and current for preamplifier and prestage P-I-N diode attenuator
(see Figure 5). Two 10.7MHz amplifiers (IFG1 - fixed gain - and IFG2 - programmable) correct the IF ce-
ramic insertion loss.
5.1.2 Mixer2, Limiter and DemodulatorIn this 2nd mixer stage the first 10.7MHz IF is converted into the second 450kHz IF. A multi-stage limiter
generates signals for the complete integrated demodulator without external tank. MPX output DC offset
compensation is possible via software.
5.1.3 Quality Detection and ISS (see Figure 3) FieldstrengthParallel to the mixer2 input a 10.7MHz limiter generates a signal for the digital IF counter and a field-
strength output signal. This internal unfiltered fieldstrength is used for adjacent channel and multipath de-
tection. The behaviour of this output signal can be corrected for DC offset (SL). The internally generated
unfiltered fieldstrength is filtered at pin #SMETERTC and used for softmute function, FM AGC keying and
generation of ISS filter switching signal for weak input level (sm).
5.1.4 Adjacent Channel DetectorThe input of the adjacent channel detector is AC coupled to the internal unfiltered fieldstrength. A pro-
grammable and configurable highpass or bandpass filter (ACF) and amplifier (ACG) followed by a rectifier
measure the adjacent channel content. This voltage is compared with an adjustable threshold (ACWTH,
ACNTH) comparator (comparator1). The output signal of this comparator generates a DC level at PIN15
with a programmable time constant. Time constant control (TISS) for the adjacent channel is made by lin-
early charging and discharging an external capacitor following. The charge current is fixed and the dis-
charge current is controlled by I2 C bus. This level produces digital signals (ac, ac+) after comparing by the
following comparator4. The adjacent channel information after filtering and rectification is available as an-
alog output on pin #TUNQUALITY (the gain can be selected via I2 C bus) in combination with multipath
content information. It is possible to enable adjacent channel content information output only via I2 C bus
control.
Table 27. Multipath And Quality Detectors
TDA7513T
5.1.5 Multipath DetectorThe input of the multipath detector is AC coupled to the internal unfiltered fieldstrength. A programmable
band-pass filter (MPF) and amplifier (MPG) followed by a rectifier measures the multipath content. This
voltage is compared with an adjustable threshold (MPTH) comparator (comparator2). The output signal of
this comparator2 is used to disable the adjacent channel detector control of the ISS filter in case of strong
multipath, which would otherwise result in bandwidth reduction because of the multipath-induced high-fre-
quency content of the fieldstrength signal. The multipath detector influence on the adjacent channel de-
tector is selectable by I2 C bus (MPOFF). The multipath information after filtering and rectification is
available as analog output on pin #TUNQUALITY (the gain can be selected via I2 C bus) in combination
with the adjacent channel content information. It is possible to enable multipath content information output
only via I2 C bus control.
5.1.6 450kHz IF Narrow Bandpass Filter (ISS filter)The device features an additional automatically selectable IF narrow bandpass filter for suppression noise
and adjacent channel signals. This narrow filter has three switchable bandwidth positions: narrow range
(80kHz), mid range (120kHz) and weather band (30kHz). WHen the ISS filter is not inserted the IF band-
width (wide range) is defined only by the ceramic filter chain. The filter is switched in after mixer2 before
the 450kHz limiter stage. The centre frequency can be finely adjusted (AISS) by software.
5.1.7 Deviation DetectorIn order to avoid excessive audio distortion the narrow ISS filter is switched OFF when overdeviation of
the incoming signal is detected. The demodulator output signal is low-pass filtered and rectified to gener-
ate a DC level in an external capacitor through a software-controlled current (TDEV). This level is com-
pared with a programmable threshold (DWTH, DTH) comparator (comparator3) to generate two digital
signals (dev, dev+).
5.1.8 ISS Switch LogicAll digital signals coming from adjacent channel detector, deviation detector and softmute are combined
in a decision matrix to generate the control signals for the ISS filter switch. The IF bandpass switch mode
can be also controlled by software (ISSON, ISS30, ISS80, ISSCTL). The switch-on of the IF bandpass can
be further controlled from the outside by manipulation of the voltage at pin #ISSTC. Two application modes
are available (APPM). The conditions are described in table 1.
5.1.9 Soft Mute ControlThe external fieldstrength signal at pin #SMETERTC is the reference for MPX mute control. The start point
and mute depth are programmable over a wide range. The time constant is defined by the external capac-
itor connected to pin #FMMUTETC.
Additionally adjacent channel mute function is supported. A software-configurable highpass / bandpass
filter centered at about 100kHz followed by an amplifier and a peak rectifier generates adjacent noise in-
formation starting from the MPX output; the information is acted upon with the same time constant as the
softmute by the MPX muting circuit. The adjacent channel mute starting point, slope and depth are I2C
bus programmable.
5.1.10Station Detector and Seek Stop A station detection function is provided for easy seek stop operation. The unfiltered fieldstrength signal is
compared with a programmable threshold and the result (logic '1' if the current station strength is higher
than the threshold) is combined by an AND gate with the IF counter output (logic '1' if the current channel
is centered within a programmable window around the desired frequency). The result is available on pin
#SD for direct connection to the microprocessor. Channel quality assessment for RDS Alternate Frequen-
cy operation makes use of the SD signal in conjunction with analog information on adjacent channel and
multipath content on pin #TUNQUALITY and channel noise (furtherly combined with multipath content in-
formation) on pin #QUALITY.
19/59
TDA7513T
5.2 AM SectionThe upconversion mixer1 is combined with a gain control circuit 1 sensing three input signals: ultra-narrow
band information (from the IF2 amplifier input - pin #AMIF2AMPIN), narrow-band information (from the
mixer2 input - pin #AMMIX2IN) and wide band information (from the mixer1 input - pins #AMMIX1IN+ and
#AMMIX1IN-). This gain control circuit generates two output signals: a current for P-I-N diode attenuation
and a voltage for the external preamplifier cascode upper base. It is possible to put in a separate narrow
bandpass filter before mixer2 at PIN 58. The intervention point for first AGC on all three bands is program-
mable by software.
The oscillator frequency for mixer1 is generated by dividing the FM VCO frequency (AMD) by 6, 8 and 10
(6 for Japan applications, 8 for Eastern European applications, 10 for Western European and North Amer-
ican operation).
In mixer2 the IF1 is downconverted into the 450kHz IF2. The gain of mixer2 is reduced by the 2nd AGC
after the gain of the subsequent IF2 amplifier has been reduced by 30dB. The mixer2 tank center frequen-
cy is software-adjustable (IF2T).
After channel selection is done by the ceramic filter, a 450kHz amplifier with a gain control is included. The
gain is controlled by the AGC2 loop over a 30dB range; the full gain with no AGC applied is programmable.
The AM demodulation is made by multiplication of the IF2 amplifier output by the amplified and limited sig-
nal coming from the IF2 amplifier input, thus making the demodulation process inherently linear.
The demodulated audio signal is low-passed by the capacitor at pin #AMAGC2TC to produce the DC
AGC2 voltage. The low-pass time constant is switchable by a ratio of 30 in order to reduce the settling
time of the AGC2 in 'seek' mode (AMSEEK).
The FM 450kHz limiter is used to generate the square wave needed by the AM demodulator, a field-
strength indication and to feed the AM IF counter. The fieldstrength information is generated mainly from
the narrow-band signal at the input of the IF2 amplifier; since the dynamic range at that input is limited by
the AGC2 action, a fieldstrength extension is made adding the contribution of the signal at the input of
mixer2. Since the bandwidth there is very large, though, the latter contribution is enabled only if the
strength of the narrow-band signal is higher than an internally defined threshold. The fieldstrength signal
must be low-passed to remove audio content and this is done by use of the capacitor at pin #SMETERTC
with an I2 C bus programmable internal resistor. The value of the capacitor is determined for correct FM
operation; the value of the internal resistor for AM is selectable in order to make the AM time constant
suitable for AM operation.
A station detection function is provided for easy seek stop operation. The fieldstrength signal is compared
with a programmable threshold and the result (logic '1' if the current station strength is higher than the
threshold) is combined by an AND gate with the IF counter output (logic '1' if the current channel is cen-
tered within a programmable window around the desired frequency). The result is available on pin #SD for
direct connection to the microprocessor.
5.3 PLL and IF Counter SectionThe IC contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is
required to build a complete PLL system for FM and AM upconversion. For auto search stop operation an
IF counter system is available.
5.3.1 PLL Frequency Synthesizer BlockThe counter works in a two stages configuration. The first stage is a swallow counter with a two-modulus
(32/33) precounter. The second stage is an 11-bit programmable counter. The circuit receives the scaling
factors for the programmable counters and the values of the reference frequency via I2 C bus. The refer-
ence frequency is generated by an adjustable internal (XTAL) oscillator followed by the reference divider.
The reference and step-frequencies are independently selectable (RC, PC). The phase-frequency detec-
tor outputs switches the programmable current source. The loop filter integrates the latter to a DC voltage.
The current source values is programmable with 6 bits received via I2C bus (A, B, CURRH, LPF). To min-
imize the noise induced by the digital part of the system, a special guard area is implemented. The loop
gain can be adjusted for different conditions by setting the current values of the chargepump generator.
TDA7513T
5.3.2 Frequency Generation for Phase ComparisonThe VCO signal is fed to a two-modulus counter (32/33) prescaler, which is controlled by a 5-bit divider
(A). A 5-bit register (PC0 to PC4) controls this divider. The output of the prescaler is connected to an 11-
bit divider (B), controlled by an 11-bit PC register (PC5 to PC15).
The following expressions relate the divider output frequency (fSYN, forced by the loop to equal the refer-
ence frequency at the phase comparator input fREF) to the VCO frequency (fVCO) and to the crystal oscil-
lator frequency (fXTAL):
fXTAL = (R+1) x fREF
fVCO = [33 x A + (B + 1 - A) x 32] x fREF
fVCO = (32 x B + A + 32) x fREF
Important: For correct operation: A ≤32; B ≥A
5.3.3 Three State Phase ComparatorThe phase comparator generates a phase error signal according to phase difference between fSYN and
fREF. This phase error signal drives the charge pump current generator.
5.3.4 Charge Pump Current GeneratorThis system generates correction current pulses with a polarity and a duration dictated by the phase error
signal. The current absolute values are programmable through register A for high current and register B
for low current.
The charge pump operates in high current mode when the phase difference between between fSYN and
fREF is high. The switch back to low current mode can be done either automatically as a function of the
inlock detector output (setting bit LDENA to "1") or via software.
After reaching a phase difference equivalent to 10-40 ns (programmable) and a delay multiple of 1/fREF,
the chargepump is forced in low current mode. A new PLL divider programming by I2 C bus will switch the
chargepump into high current mode.
A few programmable phase errors (D0, D1) are available for inlock detection. The count of detected inlock
informations to release the inlock signal is adjustable (D2, D3), to avoid switching to low current during a
frequency jump.
5.3.5 Low Noise CMOS Op-ampAn internal voltage divider at pin #LFREF is connected to the positive input of the low noise op-amp. The
charge pump output is connected to the negative input. This internal amplifier in cooperation with external
components provides the active loop filter. Only one loop filter connection is provided because the same
reference frequency is used for both AM and FM operation. The pin #LFHC is connected in such a way
as to partially shunt the loop filter in order to decrease the time constant of the filter itself during jumps with
high current mode activated.
5.3.6 IF Counter BlockThe input signal for FM and AM has the same structure although FM IF is measured at IF1 (10.7MHz) and
AM IF is measured at IF2 (450kHz). The degree of integration is adjustable to up to eight different mea-
suring cycle times. The tolerance of the accepted count value is adjustable to reach the optimum compro-
mise between search speed and evaluation precision.
T center frequency of the measured count value is adjustable to fit the IF-filter tolerance.
5.3.7 The IF-Counter ModeThe IF counter works in 2 modes controlled by the IFCM register.
5.3.8 Sampling TimerA 14-bit programmable (IRC) sampling timer generates the gate signal for the main counter. In FM mode
a 6.25kHz frequency reference is generated for this purpose, whereas in AM mode this reference be-
comes 1kHz. These reference frequencies are further divided to generate the measurement time windows
21/59
TDA7513T(160us - 320µ s ... 20.48ms for FM, 1ms - 2ms … 128ms for AM).
5.3.9 Intermediate Frequency Main CounterThis counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to
allow the adjustment to the peak of the IF-filter response. The counter length is automatically adjusted to
the chosen sampling time and counter mode (FM, AM).
The IF counter is also used to automatically perform the stereo decoder 456kHz VCO frequency adjust-
ment.
At the start the counter will be loaded with a value equivalent to the expected number of zero-crossing in
the sampling time window (tSample x fIF ). If the correct frequency is applied to the IF counter input, at the
end of the sampling time the main counter will have either a 0h state or a 1FFFFFh state stored.
A deviation from the expected IF will result in a difference of the counter final state from either of these
values. The counter final state is then compared to either 0h or 1FFFFFh minus a number of LSB's deter-
mined by the acceptable frequency window programming (EW).
If the comparison result is good the IF counter output changes from LOW to HIGH and is made available
outside at the pin #SD (after a NAND operation with the signal strength evaluation circuit). The following
relationships apply:
tTIM = (IRC + 1) / fOSC
tCNT = (CF + 1697) / fIF (FM mode)
tCNT = (CF + 448) / fIF (AM mode)
where
tTIM = IF timer cycle time (sampling time)
tCNT = IF counter cycle time
Counting succesful:
tCNT - tERR = tTIM = tCNT + tERR
Count failed:
tTIM > tCNT + tERR
tTIM < tCNT - tERR
where
tERR = discrimination window (controlled by the EW registers)
The IF counter can be started only by inlock information from the PLL, and it is enabled by software
(IFENA).
5.3.10Adjustment of the Measurement Time and Frequency windowThe measurement precision is adjustable by controlling the width of the frequency discrimination window
through control registers EW0 to EW2. The center frequency of the discrimination window is adjustable by
the control register CF0 to CF4. The measurement time per cycle is adjustable by setting the registers
TDA7513T IFS0 - IFS2.
5.4 AUDIO PROCESSOR
5.4.1 Input MultiplexerCD quasi differential 1
CD quasi differential 2
Stereodecoder input (for both FM and AM signals).
5.4.2 Input stagesThe quasi-differential input stages (see figure 4) have been designed to cope with some CD players in the
market having a significant high source impedance which affects strongly the common-mode rejection of
"normal" differential input stages. The additional buffer of the CD input avoids this drawback and offers the
full common-mode rejection even with those CD players. The quasi-differential input can also be used with
normal stereo single-ended output signal sources such as TAPEOUT.
5.4.3 AutoZeroIn order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage,
so that in theory any offset generated by or before the In-Gain stage would be transferred or even ampli-
fied to the output. To avoid this undesired situation a special offset cancellation stage called AutoZero is
implemented. This stage is located before the Volume block to eliminate all offsets generated by the Ste-
reodecoder, the Input Stage and the In-Gain stage (please note that externally generated offsets, e.g.
those generated because of leakage current into the coupling capacitors, are not cancelled).
The auto-zeroing is started every time the APSD data byte 0 is selected and takes a maximum time of
0.6ms. The rationale behind this choice is that the APSD byte encodes the signal source selection, and
auto-zero ought to be performed every time a new source is selected. To avoid audible clicks the audio-
processor is muted before the volume stage during this time.
5.4.4 AutoZero RemainIn some cases, for example if the uP is executing a refresh cycle of the I2 C bus programming, it is not
necessary to start a new AutoZero action because no new source is selected and an undesired mute
would appear at the outputs. For such applications the device can be switched in the "AutoZero Remain
mode" (Bit 6 of the APSD subaddress byte). If this bit is set to high, the APSD data byte 0 can be loaded
without invoking the AutoZero and the old adjustment value remains.
5.4.5 SoftmuteThe digitally controlled softmute stage allows signal muting and unmuting with a I2 C bus programmable
slope. The mute process can either be activated by pin #AUDIOMUTE or I2 C bus. The slope is realized
in a special S-shaped curve so as to slowly mute in the critical regions (see figure 5). For timing purposes
the Bit 3 of the I2 C bus output register is set to 1 from the start of muting until the end of unmuting.
5.4.6 BASSThere are four parameters programmable in the bass filter stage: (see figs 6, 7, 8, 9):
5.4.7 AttenuationFigure 6 shows the attenuation as a function of frequency at a center frequency at a center frequency of
80Hz.
5.4.8 Center FrequencyFigure 7 shows the four possible center frequencies: 60,70,80 and 100Hz.
5.4.9 Quality FactorsFigure 8 shows the four possible quality factors: 1, 1.25, 1.5 and 2.
23/59
TDA7513T
5.4.10DC ModeIn this mode the DC gain is increased by 5.1dB. In addition the programmed center frequency and quality
factor is decreased by 25%: this can be used to realize different center frequencies or quality factors with
respect to the values listed in the "BASS" section.
5.4.11MIDThere are 3 parameters programmable in the mid filter stage (see figs. 10, 11 & 12):
5.4.12AttenuationFigure 10 shows the attenuation as a function of frequency at a center frequency of 1kHz.
5.4.13Center FrequencyFigure 11 shows the four possible center frequencies: 500Hz, 1kHz, 1.5kHz and 2kHz.
5.4.14Quality FactorFigure 12 shows the two possible quality factors (1 and 2) at a center frequency of 1kHz.
5.4.15TREBLEThere are two parameters programmable in the treble filter stage (see figs 13, 14):
5.4.16AttenuationFigure 13 shows the attenuation as a function of frequency at a center frequency of 17.5kHz.
5.4.17Center FrequencyFigure 14 shows the four possible Center Fre-quencies: 10, 12.5, 15 and 17.5kHz.
5.4.18AC CouplingIn some applications additional signal manipulations are desired such as surround-sound processing or
more extensive band equalizing. For this purpose a AC-Coupling is placed before the Speaker-attenua-
tors, which can be activated or internally shorted by Bit7 in the APSD data byte 0. The input impedance
of the AC Inputs is 25kΩ. The external AC coupling is advised for those applications where very low-level
"pop" performance is a must.
5.4.19Speaker AttenuatorThe speaker attenuators have exactly the same structure and range as the Volume stage.
5.5 STEREODECODERThe stereodecoder part of the present device (see Fig. 15) contains all functions necessary to demodulate
the MPX signal such as pilot tone-dependent MONO/STEREO switch as well as "stereoblend" and "high-
cut" functions.
Stereodecoder MuteThe device has a fast and easy-to-control RDS mute function meant for "freezing" the stereo decoder sta-
tus during the RDS AF check time period. When this function is invoked three effects take place:
1 the stereo decoder input impedance changes to infinity (condition known as high-ohmic input); this
prevents the decoupling capacitor between the pins #TUNER_OUT (tuner output) and #TUNER_IN
(stereo decoder input) to be discharged by a channel with a potentially different DC output for the
duration of the AF check;
2 the stereo decoder PLL pilot detector is held at the current value;
3 the external capacitor of the multipath detector used inside the stereo decoder for quality control is
disconnected from the dection circuit in order to make quality checking the AF faster.
TDA7513T The RDS mute is activated from pin #RDSMUTE in AND with Bit 0 of APSD data byte 9.
5.5.1 Stereo Decoder Input stage, Ingain + InfilterThe stereo decoder is crossed by both the FM and the AM signal: the input impedance of the pin
#TUNER_IN is different between the two modes in order to allow the same external coupling components
between #TUNER_OUT and #TUNER_IN to realize different filtering functions. Whilst the input impe-
dence in FM is 100k , in AM the input impedance is decreased to 2kΩ: this allows the realization of typical
high-pass filters with a corner frequency of 70Hz for AM and less than 5Hz for FM. The low-pass section
of the typical AM transfer function is realized by use of the internal FM High-Cut filter.
The Ingain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally which is the
recommended value. The 4th order input filter has a corner frequency of 80kHz and is used to attenuate
spikes and nose and acts as an anti aliasing filter for the following switch capacitor filters.
5.5.2 DemodulatorIn the demodulator block the left and the right channel are separated from the MPX signal. In this stage
the 19 kHz pilot tone is cancelled.
To reach a good channel separation the device offers an I2C bus programmable roll-off adjustment which
is able to finely compensate for the low-pass behaviour of the tuner section. An adjustment to better than
40dB channel separation is possible. The bits for this adjustment are located ogether with the fieldstrength
adjustment in one byte. This gives the possibility to perform an optimization step during the production of
the carradio where the channel separation in relation to the fieldstrength control are trimmed.
The setup of the Stereoblend characteristics, which is programmable in a wide range, is de-scribed in 2.8.
5.5.3 De-emphasis and Highcut.One filter is provided to realize de-emphasis and High-Cut filtering.
The lowpass filter for the de-emphasis allows to choose between a time constant of 50µs and 75µs.
The filter time constant can further be controlled in both cases over the range = 2 DEEMPH. The control
is automatically performed as a function of the filtered field strength level: inside the highcut control range
(between VHCH and VHCL) the level is converted into a 5 bit word which drives the lowpass time constant.
The FM highcut function can be switched off by I2 C bus (bit 0,of APSD data byte 11). The setup of the
highcut characteristics is described in 2.9.
In AM the high-cut filter can be programmed (bit 3 to 7 of APSD data byte 16) to a fixed value (inside the
above-mentioned programmable range) in order to provide the desired lowpass characteristic of the AM
signal.
5.5.4 PLL and Pilot Tone DetectorThe PLL is tasked with locking on the 19kHz pilot tone during a stereo transmission to allow the correct
demodulation. The detector enables the stereo demodulation if the pilot tone reaches the selected pilot
tone threshold VPTHST. Two different thresholds are available. The detector output can be checked by
reading the status byte of the TDA7407 via I2 C bus.
5.5.5 Fieldstrength ControlThe filtered field strength signal is fed to the stereo decoder where it can be finely adjusted and normalized
so that it can be used to control the highcut and stereoblend functions. Furthermore the adjusted signal
can also be used to control the noise-blanker thresholds. The unfiltered field strength meter, on the other
hand, is used as input for the stereo decoder multipath detector. These additional functions are described
in sections 3.3 and 4.
5.5.6 LEVEL Input and GainTo help suppress undesired high frequency modulation of the highcut and stereoblend functions the tuner
filtered field strength signal (LEVEL) is lowpassed by a combination of a 1st order RC low-pass at 53kHz
(working as anti-aliasing filter) and a 1st-order switched capacitor lowpass at 2.2kHz.
The second stage is a programmable gain stage to finely adapt the LEVEL signal internally against tuner
25/59
TDA7513Tspread (see Testmode section 5 LEVELINTERN). The gain is widely programmable in 16 steps from 0dB
to 10dB (step = 0.67dB).
5.5.7 Stereoblend ControlThe stereoblend control block converts the internal LEVEL voltage (LEVELINTERN) into a demodulator-
compatible analog signal which is used to control the channel separation between 0dB and the maximum
separation. This control range has a fixed upper limit which is the in-ternal reference voltage REF5V. The
lower limit
can be programmed between 29.2% and 58% of REF5V in 4.167% steps (see figs. 14, 15).
To adjust the LEVEL voltage to the proper range two values must be defined: the LEVEL gain LG and
VSBL (see fig. 15). To adjust the voltage where the full channel separation is reached (VST) the LEVEL
gain LG has to be defined. The following equation can be used to estimate the gain:
The gain LG can be programmed with 4 bits. The MONO voltage VMO (0dB channel separation) can be
chosen selecting VSBL. All the necessary internal reference voltages like REF5V are derived from a band-
gap circuit, therefore they have a temperature coefficient which is practically zero.
5.5.8 Highcut ControlThe highcut control setup is similar to the stereoblend control setup : the starting point VHCH can be set
with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17, 22, 28 or 33% of
VHCH (see fig. 19).
5.6 NOISE-BLANKERIn the automotive environment the MPX signal is disturbed by spikes produced for example by the ignition
and by the wiper motor. The aim of the noiseblanker part is to cancel the audible influence of these spikes.
To perform this function the output of the stereodecoder is held at the curent voltage for a time between
22 and 38µs (programmable). The block diagram of the noiseblanker is shown in fig.20. In the first stage
the spikes are detected but to avoid a wrong triggering on high frequency (white) noise a complex trigger
desensitization control is implemented. Behind the trigger stage a pulse former generates the "blanking"
pulse
5.6.1 Trigger PathThe incoming MPX signal is highpassed by a filter with a corner frequency of 140kHz, amplified and rec-
tified. The rectified signal (RECT) is lowpassed to generate the signal PEAK. Also noise at a frequency
higher than 140kHz increases PEAK. The lowpass output voltage can be adjusted by changing the noise
rectifier discharge current. The PEAK voltage is fed to a threshold generator which adds to the PEAK volt-
age a constant voltage VTH, thus producing the trigger threshold PEAK+VTH. Both RECT and
PEAK+VTH are fed to a comparator which trig-gers a re-triggerable monoflop. The monoflop output acti-
vates the sample-and-hold circuits in the signalpath for a selectable duration.
5.6.2 Automatic Noise Controlled Threshold Adjustment (ATC)There are mainly two independent possibilities to program the trigger threshold: programming the so-called "low threshold" in 8 steps; programming the so-called "noise-adjusted threshold" in 4 steps
The "low threshold" is active in combination with a good MPX signal without any noise; the PEAK voltage
is less than 1V. The sensitivity in this operating mode is high.
If the MPX signal is noisy the PEAK voltage increases due to the higher noise, which is also rectified. With
increasing of the PEAK voltage the trigger threshold increases, too. This particular mechanism ("noise-
adjusted threshold") is programmable in 4 steps. G REF5V
Fieldstrengthvoltage STEREO[]------------------- --------------------------------- -------------------------------------------=
TDA7513T
5.7 AUTOMATIC THRESHOLD CONTROL MECHANISM
5.7.1 Automatic Threshold Control by the Stereoblend VoltageBesides the noise-controlled threshold adjustment there is an additional possibility to influence the trigger
threshold which depends on the stereoblend control.
The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting
point of the normal noise-controlled trigger adjustment is fixed. In some cases the behavior of the noise-
blanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes
a wrong triggering occures for the MPX signal often shows distortion in this range which can be avoided
even if using a low threshold. Because of the overlap of this range and the range of the stereo/mono tran-
sition it can be controlled by stereoblend.
This threshold increase is programmable in 3 steps or switched off.
5.7.2 Over Deviation DetectorIf the system is tuned to stations with a high de-viation the noiseblanker might be erroneously triggered
on the higher frequencies of the modulation. To avoid this unnecessary muting of the signal, the noise-
blanker offers a deviation-dependent threshold adjustment.
By rectifying the MPX signal a further signal representing the actual deviation is obtained. This is used to
increase the PEAK voltage. The circuit offset, gain (and enabling) are programmable in 3 steps.
5.8 MULTIPATH DETECTORUsing the stereo decoder multipath detector the audible effects of a multipath condition can be minimized.
A multipath condition is detected by rectifying the 19kHz spectrum in the fieldstrength signal. An external
capacitor is used to define the attack and decay times (see block diagram fig. 21). The pin #MULTIPATH-
TC is externally connected to a capacitor of about 47nF and the MPIN signal is internally connected to the
unfiltered field strength. To avoid losing the information stored in the external capacitor during AF checks
but at the same time to allow some fast multipath detection capability during the same AF check period,
the external capacitor is disconnected by the MP-Hold switch. This switch is controlled directly by the pin
#RDSMUTE.
Moreover, selecting the "internal influence" in the configuration byte, the channel separation is automati-
cally reduced during a multipath condition according to the voltage appearing at the pin #MULTIPATHTC.
5.8.1 ProgrammingTo obtain a good multipath performance an adaptation is necessary. Therefore tha gain of the 19kHz
bandpass is programmable in four steps as well as the rectifier gain. The attack and decay times can be
set by properly choosing the value of the external capacitor.
5.9 QUALITY DETECTORThe device offers a quality detector output voltage representing the quality of the FM reception conditions.
This voltage is derived from MPX noise information and multipath information according to the following
formula:
Quality = 1.6 (Vnoise -0.8V)+ a (REF5V- VMPOUT)
The noise signal is the PEAK signal of the noise blanker without additional influences. The multipath in-
formation weight "a" can be programmed between 0.7 and 1.15. The circuit output pin #QUALITY is a low
impedance output able to drive external circuitry as well as suitable to be simply fed to an A/D converter
for RDS applications.
5.9.1 AF Search ControlThe device is supplied with several functionality to support AF-checks using the stereodecoder. As already
mentioned before the high ohmic mute feature at the stereo decoder input avoids any clicks during the
jump condition.
It is possible at the same time to evaluate the noise- and multipath-content of the alternate frequency by
27/59
TDA7513Tusing the Quality detector output. During this time the multipath detector is automatically switched to a
small time constant.
One dedicated pin (#RDSMUTE) is provided in order to separate the audioprocessor-mute and stereode-
coder AF-functions.
5.10I2 C-Bus Interface2 C bus protocol is supported. This protocol defines any device that sends data onto the bus as a trans-
mitter, and the receiving device as the receiver.
The device that controls the transfer is a master and device being controlled is the slave. The master will
always initiate data transfer and provide the clock to transmit or receive operations. The present device
always acts as slave, both in transmission and in reception mode.
5.10.1Data TransitionData transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL
is HIGH will be interpreted as START or STOP condition.
5.10.2Start ConditionA start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH
level. This "START" condition must precede any command and initiate a data transfer onto the bus. The
device continuously monitors the SDA and SCL lines for a valid START and will not response to any com-
mand if this condition has not been met.
5.10.3Stop ConditionA STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable
HIGH level. This condition terminates the communication between the devices and forces the bus inter-
face of the device into the initial condition.
5.10.4AcknowledgeIndicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. Dur-
ing the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it received the eight bits
of data.
5.10.5Data TransferDuring data transfer the device samples the SDA line on the leading edge of the SCL clock. Therefore, for
proper device operation the SDA line must be stable during the SCL LOW to HIGH transition.
5.10.6Device AddressingTo start the communication between two devices, the bus master must initiate a start instruction se-
quence, followed by an eight bit word corresponding to the address of the device.
The device recognizes the following two addresses:
1100010d tuner part address
1000110d stereo decoder / audio processor address (APSD)
The last bit of the start instruction defines the type of operation to be performed: when set to "1", a read operation is selected (data are transferred from the device to the master) when set to "0", a write operation is selected (data are transferred from the master to the device)
The device connected to the bus will compare its own hardwired addresses with the slave address being
transmitted after detecting a START condition.
After this comparison, the device will generate an "acknowledge" on the SDA line and will perform either
a read or a write operation according to the state of the R/W bit.
TDA7513T
5.10.7Write OperationFollowing a START condition the master sends a slave address word with the R/W bit set to "0". The de-
vice will generate an "acknowledge" after this first transmission and will wait for a second word (the sub-
address field).
This 8-bit address field provides an access to any of the 64 internal addresses (32 corresponding to the
tuner address and 32 corresponding to the stereo decoder / audio processor address). Upon receipt of the
subaddress the device will respond with an "acknowledge".
At this time, all the following words transmitted to the device will be considered as Data.
The internal address may be automatically incremented if the auto-increment mode is selected (bit S5 of
the subaddress word) .
After each word has been received the device will answer with an "acknowledge".
5.10.8Read OperationIF the master sends a slave address word with the R/W bit set to "1", the device will transmit one 8-bit data
word.
This data word content changes according to the address corresponding to the tuner or to the stereo de-
coder / audio processor. The information are the following:
tunerbit0: ISS filter, 1 = ON, 0 = OFF
bit1: ISS filter bandwidth, 1 = 80kHz, 0 = 120kHz
bit2: MPOUT,1 = multipath present, 0 = no multipath
bit3: 1 = PLL is locked in , 0 = PLL is locked out
bit4: fieldstrength indicator, 1 = lower as softmute threshold, 0 = higher as softmute threshold
bit5: adjacent channel indicator, 1 = adjacent channel present, 0 = no adjacent channel
bit6: deviation indicator, 1 = strong overdeviation present, 0 = no strong overdeviation
bit7: deviation indicator, 1 = overdeviation present, 0 = no overdeviation
stereo decoder / audio processorbit2: Soft Mute status, 1 = ON, 0 = OFF
bit3: Stereo mode, 1 = stereo, 0 = mono
Table 28. ISS Modes
MODE 1
29/59
TDA7513T
MODE 2
Figure 5. Softmute Timing
Figure 6. Bass Control @ Fc = 80Hz, Q = 1
Figure 7. Bass center @Gain = 14dB, Q = 1
Figure 8. Bass Quality factors @ Gain = 14dB,
fc = 80Hz
Figure 9. Bass normal and DC Mode@ Gain =
TDA7513T
14dB, fc = 80Hz
Figure 10. Mid Control @ fc = 1KHz, Q = 1
Figure 11. Mid Center Frequency@ Gain
=14dB, Q = 1
Figure 12. Mid Q factor@ fc=1KHz,Gain
=14dB
Figure 14. Treble Center Frequencies@ Gain
= 14dB
