TDA7512 ,AM/FM CAR RADIO TUNER IC WITH INTELLIGENT SELECTIVITY SYSTEM (ISS)BLOCK DIAGRAM2/42TDA7512PIN CONNECTION (Top view)64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49AMM ..
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THS4051CD ,70-MHz Low-Cost Voltage-Feedback Amplifier.†The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., ..
THS4051CDGN ,70-MHz Low-Cost Voltage-Feedback AmplifierSLOS238D − MAY 1999 − REVISED AUGUST 2008CAUTION: The THS4051 and THS4052 provide ESD protection ci ..
THS4051CDGNR ,70-MHz Low-Cost Voltage-Feedback AmplifierMAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (UNLESS(1)OTHERWISE NOTED)Supply voltage, V . . ..
THS4051ID G4 ,70-MHz Low-Cost Voltage-Feedback Amplifier 8-SOIC -40 to 85FEATURESD, DGN, AND JG PACKAGES(TOP VIEW) High Speed:− 70 MHz Bandwidth (G = 1, −3 dB)NULL 1 8 NU ..
THS4051IDG4 ,70-MHz Low-Cost Voltage-Feedback Amplifier 8-SOIC -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratings only andfunction ..
THS4051IDGNR ,70-MHz Low-Cost Voltage-Feedback AmplifierSLOS238D − MAY 1999 − REVISED AUGUST 2008(1)AVAILABLE OPTIONSPACKAGED DEVICESNUMBER†PLASTICPLASTIC ..
TDA7512
AM/FM CAR RADIO TUNER IC WITH INTELLIGENT SELECTIVITY SYSTEM (ISS)
1/42
TDA7512January 2003
FM-PART RF AGC GENERATION BY RF AND IF
DETECTION I/Q MIXER FOR 1ST FM IF 10.7MHz WITH
IMAGE REJECTION 2 PROGRAMMABLE IF-GAIN STAGES MIXER FOR 2nd IF 450KHz INTERNAL 450KHz BANDPASS FILTER WITH
THREE BANDWIDTHS CONTROLLED BY ISS FULLY INTEGRATED FM-DEMODULATOR
WITH NOISE CANCELLATION
AM-PART WIDE AND NARROW AGC GENERATION PREAMPLIFIER AND MIXER FOR 1ST IF
10.7MHz, AM UPCONVERSION MIXER FOR 2nd IF 450KHz INTEGRATED AM-DEMODULATOR OUTPUT FOR AM-STEREO-DECODER
ADDITIONAL FEATURES VCO FOR WORLD TUNING RANGE HIGH PERFORMANCE FAST PLL FOR RDS-
SYSTEM IF COUNTER FOR FM AND AM WITH
SEARCH STOP SIGNAL QUALITY DETECTOR FOR LEVEL,
DEVIATION, ADJACENT CHANNEL AND
MULTIPATH QUALITY DETECTION INFORMATIONS AS
ANALOG SIGNALS EXTERNAL AVAILABLE ISS (INTELLIGENT SELECTIVITY SYSTEM)
FOR CANCELLATION OF ADJACENT
CHANNEL AND NOISE INFLUENCES ADJACENT CHANNEL MUTE FULLY ELECTRONIC ALIGNMENT ALL FUNCTIONS I2 C-BUS CONTROLLED ISS FILTER STATUS INFORMATION I2 C-BUS
READABLE
DESCRIPTIONThe TDA7512 is a high performance tuner circuit for
AM/FM car radio. It contains mixer, IF amplifier, de-
modulator for AM and FM, quality detection, ISS filter
and PLL synthesizer with IF counter on a single chip.
Use of BICMOS technology allows the implementa-
tion of several tuning functions and a minimum of ex-
ternal components.
PRELIMINARY DATAAM/FM CAR RADIO TUNER IC WITH INTELLIGENT
SELECTIVITY SYSTEM (ISS)
TDA7512 2/42
BLOCK DIAGRAM
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TDA7512
PIN CONNECTION (Top view)
PIN DESCRIPTION
TDA7512 4/42
PIN DESCRIPTION (continued)
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TDA7512
THERMAL DATA
ABSOLUTE MAXIMUM RATINGS
Table 1.
Table 2.
PIN DESCRIPTION (continued)
TDA7512 6/42
Table 3. ELECTRICAL CHARACTERISTICS Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCIF1=8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1 =10.7MHz, fIF2 =450KHz, fXtal= 10.25MHz, in application circuit, unless otherwise
specified.
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TDA7512
Table 3. ELECTRICAL CHARACTERISTICS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCIF1=8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1 =10.7MHz, fIF2 =450KHz, fXtal= 10.25MHz, in application circuit, unless otherwise
specified.
TDA7512 8/42
Table 3. ELECTRICAL CHARACTERISTICS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCIF1=8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1 =10.7MHz, fIF2 =450KHz, fXtal= 10.25MHz, in application circuit, unless otherwise
specified.
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TDA7512
Table 3. ELECTRICAL CHARACTERISTICS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCIF1=8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1 =10.7MHz, fIF2 =450KHz, fXtal= 10.25MHz, in application circuit, unless otherwise
specified.
TDA7512 10/42
Table 3. ELECTRICAL CHARACTERISTICS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCIF1=8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1 =10.7MHz, fIF2 =450KHz, fXtal= 10.25MHz, in application circuit, unless otherwise
specified.
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TDA7512
Table 3. ELECTRICAL CHARACTERISTICS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCIF1=8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1 =10.7MHz, fIF2 =450KHz, fXtal= 10.25MHz, in application circuit, unless otherwise
specified.
TDA7512 12/42
Table 4. ELECTRICAL CHARACTERISTICS Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCMIX2 =8.5V, fRF =1MHz, fMOD= 400Hz at
30% AMfIF1= 10.7MHz, fIF2 =450kHz, fxtal= 10.25MHz, in application circuit, (unless otherwise noted,
VINRF antenna input).
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TDA7512
Table 4. ELECTRICAL CHARACTERISTICS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCMIX2 =8.5V, fRF =1MHz, fMOD= 400Hz at
30% AMfIF1= 10.7MHz, fIF2 =450kHz, fxtal= 10.25MHz, in application circuit, (unless otherwise noted,
VINRF antenna input).
TDA7512 14/42
Table 5. ADDITIONAL PARAMETERS
15/42
TDA7512 Functional Description
1.1 FM Section
1.2 Mixer1, AGC and 1.IFFM quadrature I/Q-mixer converts FM RF to IF1 of 10.7MHz. The mixer provides inherent image rejection and
wide dynamic range with low noise and large input signal performance. The mixer1 tank can be adjusted by
software (IF1T). For accurate image rejection the gain- and phase-error generated as well in mixer as VCO
stage can be compensated by software (G,PH)
It is capable of tuning the US FM, US weather, Europe FM, Japan FM and East Europe FM bands US FM = 87.9 to 107.9 MHz US weather = 162.4 to 162.55 MHz Europe FM = 87.5 to 108 MHz Japan FM = 76 to 91 MHz East Europe FM = 65.8 to 74 MHz
The AGC operates on different sensitivities and bandwidths in order to improve the input sensitivity and dynamic
range. AGC thresholds are programmable by software (RFAGC,IFAGC,KAGC). The output signal is a con-
trolled current for double pin diode attenuator.
Two 10.7MHz programmable amplifiers (IFG1, IFG2) correct the IF ceramic insertion loss and the costumer lev-
el plan application.
1.3 Mixer2, Limiter and DemodulatorIn this 2. mixer stage the first 10.7MHz IF is converted into the second 450kHz IF. A multi-stage limiter generates
signals for the complete integrated demodulator without external tank. MPX output DC offset versus noise DC
level is correctable by software (DEM).
1.4 Quality Detection and ISS
1.4.1 FieldstrengthParallel to mixer2 input a 10.7MHz limiter generates a signal for digital IF counter and a fieldstrength output sig-
nal. This internal unweighted fieldstrength is used for keying AGC, adjacent channel and multipath detection
and is available at PIN14 (FSU) after +6dB buffer stage. The behaviour of this output signal can be corrected
for DC offset (SL) and slope (SMSL). The internal generated unweighted fieldstrength is filtered at PIN35 and
used for softmute function and generation of ISS filter switching signal for weak input level (sm).
1.4.2 Adjacent Channel DetectorThe input of the adjacent channel detector is AC coupled from internal unweighted fieldstrength. A programma-
ble highpass or bandpass (ACF) and amplifier (ACG) as well as rectifier determines the influences. This voltage
is compared with adjustable comparator1 thresholds (ACWTH, ACNTH). The output signal of this comparator
generates a DC level at PIN15 by programmable time constant. Time control (TISS) for a present adjacent chan-
nel is made by charge and discharge current after comparator1 in an external capacitance. The charge current
is fixed and the discharge current is controlled by I2 C Bus. This level produces digital signals (ac, ac+) in an
additional comparator4. The adjacent channel information is available as analog output signal after rectifier and
+8dB output buffer.
1.4.3 Multipath DetectorThe input of the multipath detector is AC coupled from internal unweighted fieldstrength. A programmable band-
pass (MPF) and amplifier (MPG) as well as rectifier determines the influences. This voltage is compared with
an adjustable comparator2 thresholds (MPTH). The output signal of this comparator2 is used for the "Milano"
effect. In this case the adjacent channel detection is switched off. The "Milano" effect is selectable by I2 C Bus
(MPOFF). The multipath information is available as analog output signal after rectifier and +8dB output buffer.
TDA7512 16/42
1.4.4 450kHz IF Narrow Bandpass Filter (ISS filter)The device gets an additional second IF narrow bandpass filter for suppression of noise and adjacent channel
signal influences. This narrow filter has three switchable bandwidthes, narrow range of 80kHz, mid range of
120kHz and 30KHz for weather band information. Without ISS filter the IF bandwidth (wide range) is defined
only by ceramic filter chain. The filter is switched in after mixer2 before 450kHz limiter stage. The centre fre-
quency is matching to the demodulator center frequency.
1.4.5 Deviation DetectorIn order to avoid distortion in audio output signal the narrow ISS filter is switched OFF for present overdeviation.
Hence the demodulator output signal is detected. A lowpass filtering and peak rectifier generates a signal that
is defined by software controlled current (TDEV) in an external capacitance. This value is compared with a pro-
grammable comparator3 thresholds (DWTH, DTH) and generates two digital signals (dev, dev+). For weak sig-
nal condition deviation threshold is proportinal to FSU.
1.4.6 ISS Switch LogicAll digital signals coming from adjacent channel detector, deviation detector and softmute are acting via switch-
ing matrix on ISS filter switch. The IF bandpass switch mode is controlled by software (ISSON, ISS30, ISS80,
CTLOFF). The switch ON of the IF bandpass is also available by external manipulation of the voltage at PIN15.
Two application modes are available (APPM). The conditions are described in table 34.
1.5 Soft Mute ControlThe external fieldstrength signal at PIN 35 is the reference for mute control. The startpoint and mute depth are
programmable (SMTH, SMD) in a wide range. The time constant is defined by external capacitance. Additional
adjacent channel mute function is supported. A highpass filter with -3dB threshold frequency of 100kHz, amplifier
and peak rectifier generates an adjacent noise signal from MPX output with the same time constant for softmute.
This value is compared with comparator5 thresholds (ACM). For present strong adjacent channel the MPX signal
is additional attenuated (ACMD).
1.6 AM SectionThe up/down conversion is combined with gain control circuit sensing three input signals, narrow band informa-
tion at PIN 39, upconversion signal (IFAGC) at PIN 58 and wide band information (RFAGC) at PIN 3.This gain
control gives two output signals. The first one is a current for pin diode attenuator and the second one is a volt-
age for preamplifier. Time constant of RF- and IF-AGC is defined by internal 100k resistor and external capacitor
at PIN 62. The intervention points for AGC (DAGC,WAGC) are programmable by software. In order to avoid a
misbehaviour of AGC intervention point it is important to know that the DAGC threshold has to be lower than
WAGC threshold !
The oscillator frequency for upconcersion-mixer1 is generated by dividing the FM VCO frequency after VCO
(VCOD) and AM predivider(AMD). It is possible to put in a separate narrow bandpass filter before mixer2 at PIN
58. In this case input P58 needs the DC-operation point from PIN 53 via resistance matched with filter imped-
ance. Additional it is possible to use second 10,7MHz ceramic filter by internal switch between mixer2 input and
PIN 52. This feature increases 900KHz attenuation.
In mixer2 the IF1 is downconverted into the IF2 450kHz. After filtering by ceramic filter a 450kHz amplifier is
included with an additional gain control of IF2 below DAGC threshold. Time constant is defined by capacitance
at PIN 40
Mixer1 and mixer2 tanks are software controlled adjustable (IF1T, IF2T).
The demodulator is a peak detector to generate the audio output signal.
A separate output is available for AMIF stereo (AMST).
17/42
TDA7512
1.7 PLL and IF Counter Section
1.7.1 PLL Frequency Synthesizer BlockThis part contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is required
to build a complete PLL system for FM world tuning and AM upconversion. For auto search stop operation an
IF counter system is available.
The counter works in a two stages configuration. The first stage is a swallow counter with a two modulus (32/33)
precounter. The second stage is an 11-bit programmable counter.
The circuit receives the scaling factors for the programmable counters and the values of the reference frequen-
cies via an I2 C-Bus interface.The reference frequency is generated by an adjustable internal (XTAL) oscillator
followed by the reference divider. The main reference and step-frequencies are free selectable (RC, PC).
Output signals of the phase detector are switching the programmable current sources. The loop filter integrates
their currents to a DC voltage.
The values of the current sources are programmable by 6 bits also received via the I2 C Bus (A, B, CURRH, LPF).
To minimize the noise induced by the digital part of the system, a special guard configuration is implemented.
The loop gain can be set for different conditions by setting the current values of the chargepump generator.
1.7.2 Frequency Generation for Phase ComparisonThe RF signals applies a two modulus counter (32/33) pre-scaler, which is controlled by a 5-bit A-divider. The
5-bit register (PC0 to PC4) controls this divider. In parallel the output of the prescaler connects to an 11-bit B-
divider. The 11-bit PC register (PC5 to PC15) controls this divider
Dividing range:
fVCO = [33 x A + (B + 1 - A) x 32] x fREF
fVCO = (32 x B + A + 32) x fREF
Important: For correct operation: A ≤ 32; B ≥ A
1.7.3 Three State Phase ComparatorThe phase comparator generates a phase error signal according to phase difference between fSYN and fREF.
This phase error signal drives the charge pump current generator.
1.7.4 Charge Pump Current GeneratorThis system generators signed pulses of current. The phase error signal decides the duration and polarity of
those pulses. The current absolute values are programmable by A register for high current and B register for
low current.
1.7.5 Inlock DetectorSwitching the chargepump in low current mode can be done either via software or automatically by the inlock
detector, by setting bit LDENA to "1".
After reaching a phase difference about lower than 40nsec the chargepump is forced in low current mode. A
new PLL divider alternation by I2 C-Bus will switch the chargepump in the high current mode.
1.7.6 Low Noise CMOS Op-ampAn internal voltage divider at pin VREF2 connects the positive input of the low noise op-amp. The charge pump
output connects the negative input. This internal amplifier in cooperation with external components can provide
an active filter. The negative input is switchable to three input pins, to increase the flexibility in application. This
feature allows two separate active filters for different applications.
While the high current mode is activated LPHC output is switched on.
1.7.7 IF Counter BlockThe aim of IF counter is to measure the intermediate frequency of the tuner for AM and FM mode. The input
signal for FM and AM upconversion is the same 10.7MHz IF level after limiter. AM 450KHz signal is coming from
TDA7512 18/42
narrow filtered IF2 before demodulation. A switch controlled by IF counter mode (IFCM) is chosing the input sig-
nal for IF counter.
The grade of integration is adjustable by eight different measuring cycle times. The tolerance of the accepted
count value is adjustable, to reach an optimum compromise for search speed and precision of the evaluation.
1.7.8 The IF-Counter ModeThe IF counter works in 3 modes controlled by IFCM register.
1.7.9 Sampling TimerA sampling timer generates the gate signal for the main counter. The basically sampling time are in FM mode
6.25kHz (tTIM=160μs) and in AM mode 1kHz (tTIM=1ms). This is followed by an asynchronous divider to gener-
ate several sampling times.
1.7.10 Intermediate Frequency Main CounterThis counter is a 11- 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to have
the possibility for an adjust to the centre frequency of the IF-filter. The counter length is automatic adjusted to
the chosen sampling time and the counter mode (FM, AM-UPC, AM).
At the start the counter will be loaded with a defined value which is an equivalent to the divider value
(tSample xfIF).
If a correct frequency is applied to the IF counter frequency input at the end of the sampling time the main
counter is changing its state from 0h to 1FFFFFh.
This is detected by a control logic and an external search stop output is changing from LOW to HIGH. The fre-
quency range inside which a successful count result is adjustable by the EW bits.
tCNT = (CF + 1696+1) / fIF FM mode
tCNT = (CF + 10688+1) / fIF AM up conversion mode
tCNT = (CF + 488+1) / fIF AM mode
Counter result succeeded:
tTIM ≥ tCNT - tERR
tTIM ≤ tCNT + tERR
Counter result failed:
tTIM > tCNT + tERR
tTIM < tCNT - tERR
tTIM = IF timer cycle time (sampling time)
tCNT = IF counter cycle time
tERR = discrimination window (controlled by the EW registers)
The IF counter is only started by inlock information from the PLL part. It is enabled by software (IFENA).
1.7.11 Adjustment of the Measurement Sequence TimeThe precision of the measurements is adjustable by controlling the discrimination window. This is adjustable by
programming the control registers EW.
The measurement time per cycle is adjustable by setting the registers IFS.
1.7.12 Adjust of the Frequency ValueThe center frequency of the discrimination window is adjustable by the control registers CF.
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TDA7512
1.8 I2 C-Bus InterfaceThe TDA7512 supports the I2 C-Bus protocol. This protocol defines any device that sends data onto the bus as
a transmitter, and the receiving device as the receiver. The device that controls the transfer is a master and
device being controlled is the slave. The master will always initiate data transfer and provide the clock to trans-
mit or receive operations.
1.8.1 Data TransitionData transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL is HIGH
will be interpreted as START or STOP condition.
1.8.2 Start ConditionA start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level.
This "START" condition must precede any command and initiate a data transfer onto the bus. The device con-
tinuously monitors the SDA and SCL lines for a valid START and will not response to any command if this con-
dition has not been met.
1.8.3 Stop ConditionA STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH
level. This condition terminates the communication between the devices and forces the bus-interface of the de-
vice into the initial condition.
1.8.4 AcknowledgeIndicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. During the
9th clock cycle the receiver will pull the SDA line to LOW level to indicate it receive the eight bits of data.
1.8.5 Data TransferDuring data transfer the device samples the SDA line on the leading edge of the SCL clock. Therefore, for prop-
er device operation the SDA line must be stable during the SCL LOW to HIGH transition.
1.8.6 Device AddressingTo start the communication between two devices, the bus master must initiate a start instruction sequence, fol-
lowed by an eight bit word corresponding to the address of the device it is addressing.
The most significant 6 bits of the slave address are the device type identifier.
The TDA7512 device type is fixed as "110001".
The next significant bit is used to address a particular device of the previous defined type connected to the bus.
The state of the hardwired PIN 41 defines the state of this address bit. So up to two devices could be connected
on the same bus. When PIN 41 is connected to VCC2 the address bit “1” is selected. In this case the AM part
doesn’t work. Otherwise the address bit “0” is selected (FM and AM is working). Therefor a double FM tuner
concept is possible.
The last bit of the start instruction defines the type of operation to be performed: When set to "1", a read operation is selected When set to "0", a write operation is selected
The TDA7512 connected to the bus will compare their own hardwired address with the slave address being
transmitted, after detecting a START condition. After this comparison, the TDA7512 will generate an "acknowl-
edge" on the SDA line and will do either a read or a write operation according to the state of R/W bit.
1.8.7 Write OperationFollowing a START condition the master sends a slave address word with the R/W bit set to "0". The device will
generate an "acknowledge" after this first transmission and will wait for a second word (the word address field).
This 8-bit address field provides an access to any of the 32 internal addresses. Upon receipt of the word address
the TDA7512 slave device will respond with an "acknowledge". At this time, all the following words transmitted
TDA7512 20/42
to the TDA7512 will be considered as Data. The internal address will be automatically incremented. After each
word receipt the TDA7512 will answer with an "acknowledge".
1.8.8 Read OperationIf the master sends a slave address word with the R/W bit set to "1", the TDA7512 will transit one 8-bit data
word. This data word includes the following informations:
bit0 (ISS filter, 1= ON, 0= OFF)
bit1 (ISS filter bandwidth, 1= 80kHz, 0 = 120kHz)
bit2 (MPOUT,1 = multipath present, 0= no multipath)
bit3 (1= PLL is locked in , 0 = PLL is locked out).
bit4 (fieldstrength indicator, 1= lower as softmute threshold, 0= higher as softmute threshold)
bit5 (adjacent channel indicator, 1 = adjacent channel present, 0= no adjacent channel)
bit6 (deviation indicator, 1 = strong overdeviation present, 0= no strong overdeviation)
bit7 (deviation indicator, 1 = overdeviation present, 0= no overdeviation)
Software SpecificationThe interface protocol comprises: start condition (S) chip address byte subaddress byte sequence of data (N bytes + Acknowledge) stop condition (P)
21/42
TDA7512
2.1 ADDRESS ORGANIZATION
2.2 Control Register Function
Table 6. Address Organization
Table 7.
