TDA7511 ,AM/FM TUNER FOR CAR RADIO HIFI APPLICATIONSBLOCK DIAGRAMLogic2/41AMIFin61 62 60 53 57 59 54 52 50 46 45 25 26 33 36 51 4956V VCC1 CC2 482I C B ..
TDA7512 ,AM/FM CAR RADIO TUNER IC WITH INTELLIGENT SELECTIVITY SYSTEM (ISS)BLOCK DIAGRAM2/42TDA7512PIN CONNECTION (Top view)64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49AMM ..
TDA7512F , FM car-radio tuner IC with intelligent selectivity system (ISS)
TDA7513T ,SINGLE-CHIP FM/AM TUNER WITH STEREO DECODER AND AUDIO PROCESSORFEATURESFigure 1. Package■ AM/FM TUNER FOR CAR-RADIO■ INTEGRATED TUNING PLL■ VARIABLE-BANDWITH FM I ..
TDA7513T ,SINGLE-CHIP FM/AM TUNER WITH STEREO DECODER AND AUDIO PROCESSORfeatures front-end processing, includ-mute function are included to handle sourceing the digital tu ..
TDA7515 ,RF-FRONTEND FOR AM/FM-DSP-CARRADIOS WITH IF SAMPLINGBLOCK DIAGRAMoptional222AGC ADJIF 10.7MHz2FMAGCDAGCQIPM2BusAGC InterfaceTV1 TV22SupplyAMPMDIV :1/:2 ..
THS4041IDGN ,165-MHz C-Stable Voltage-Feedback Amplifierelectrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted)A CC Ldynamic ..
THS4042CDG4 ,165-MHz C-Stable Voltage-Feedback Amplifier, Dual 8-SOIC 0 to 70 SLOS237B− MAY 1999 − REVISED FEBRUARY 2000THS ..
THS4042CDGN ,165-MHz C-Stable Voltage-Feedback Amplifier, Dualmaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V . . . ..
THS4042CDGNR ,165-MHz C-Stable Voltage-Feedback Amplifier, Dualelectrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted)A CC Ldynamic ..
THS4051CD ,70-MHz Low-Cost Voltage-Feedback Amplifier.†The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., ..
THS4051CDGN ,70-MHz Low-Cost Voltage-Feedback AmplifierSLOS238D − MAY 1999 − REVISED AUGUST 2008CAUTION: The THS4051 and THS4052 provide ESD protection ci ..
TDA7511
AM/FM TUNER FOR CAR RADIO HIFI APPLICATIONS
1/41
TDA7511November 2001
FM-PART RF AGC GENERATION BY RF AND IF
DETECTION FOR PIN DIODES AND MOSFET
(PRESTAGE)1ST MIXER FOR 1ST FM IF 10.7MHz WITH
PROGRAMMABLE IF TANK ADJUST FOR FM
AND AM UPCONVERSION 2 PROGRAMMABLE IF-GAIN STAGES2ND MIXER FOR 2ND IF 450KHz INTERNAL IF BANDPASS FILTER WITH
THREE BANDWIDTHS CONTROLLED BY ISS
(INCLUDING WEATHER BAND) FULLY INTEGRATED FM-DEMODULATOR
AM-PART WIDE AND NARROW AGC GENERATION PREAMPLIFIER AND MIXER FOR 1ST IF
10.7MHZ,
AM UPCONVERSION 2ND MIXER FOR 2ND IF 450KHZ INTEGRATED AM-DEMODULATOR OUTPUT FOR AM-STEREO-DECODER
ADDITIONAL FEATURES HIGH PERFORMANCE FAST PLL FOR RDS-
SYSTEM IF COUNTER FOR FM AND AM
UPCONVERSION WITH SEARCH STOP
SIGNAL QUALITY DETECTOR FOR LEVEL,
DEVIATION, ADJACENT CHANNEL AND
MULTIPATH QUALITY DETECTION INFORMATIONS AS
ANALOG SIGNALS EXTERNAL AVAILABLE ISS (INTELLIGENT SELECTIVITY SYSTEM)
FOR CANCELLATION OF ADJACENT
CHANNEL AND NOISE INFLUENCES ADJACENT CHANNEL MUTE FULLY ELECTRONIC ALIGNMENT ALL FUNCTIONS I2 C-BUS CONTROLLED ISS FILTER STATUS INFORMATION I2 C-BUS
READABLE
DESCRIPTIONThe TDA 7511 is a high performance tuner circuit for
AM/FM car radio. It contains mixers, IF amplifiers, de-
modulators for AM and FM, quality detection, ISS fil-
ter and PLL synthesizer with IF counter on a single
chip.
Use of BICMOS technology allows the implementa-
tion of several tuning functions and a minimum of ex-
ternal components.
AM/FM TUNER FOR CAR RADIO AND HIFI APPLICATIONS
TDA7511 2/41
BLOCK DIAGRAM
3/41
TDA7511
PIN CONNECTION (Top view)
PIN DESCRIPTION (continued)
TDA7511 4/41
PIN DESCRIPTION (continued)
5/41
TDA7511
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
ELECTRICAL CHARACTERISTCS Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= 8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1= 10.7MHz, fIF2= 450KHz, fXtal= 10.25MHz, in test or application circuit, unless otherwise
specified.
PIN DESCRIPTION (continued)
TDA7511 6/41
ELECTRICAL CHARACTERISTCS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= 8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1= 10.7MHz, fIF2= 450KHz, fXtal= 10.25MHz, in test or application circuit, unless otherwise
specified.
7/41
TDA7511
ELECTRICAL CHARACTERISTCS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= 8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1= 10.7MHz, fIF2= 450KHz, fXtal= 10.25MHz, in test or application circuit, unless otherwise
specified.
TDA7511 8/41
ELECTRICAL CHARACTERISTCS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= 8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1= 10.7MHz, fIF2= 450KHz, fXtal= 10.25MHz, in test or application circuit, unless otherwise
specified.
9/41
TDA7511
ELECTRICAL CHARACTERISTCS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= 8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1= 10.7MHz, fIF2= 450KHz, fXtal= 10.25MHz, in test or application circuit, unless otherwise
specified.
TDA7511 10/41
ELECTRICAL CHARACTERISTICS Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCMIX2 =8.5V, fRF =1MHz, fMOD= 400Hz at 30%
AMfIF1= 10.7MHz, fIF2= 450kHz, fxtal= 10.25MHz, in test or application circuit, (unless otherwise noted, VinRF
antenna input).
ELECTRICAL CHARACTERISTCS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= 8.5V, fRF= 98MHz, dev.= 40kHz,
fMOD =1kHz, fIF1= 10.7MHz, fIF2= 450KHz, fXtal= 10.25MHz, in test or application circuit, unless otherwise
specified.
11/41
TDA7511
ELECTRICAL CHARACTERISTICS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCMIX2 =8.5V, fRF =1MHz, fMOD= 400Hz at 30%
AMfIF1= 10.7MHz, fIF2= 450kHz, fxtal= 10.25MHz, in test or application circuit, (unless otherwise noted, VinRF
antenna input).
TDA7511 12/41
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (continued)Tamb= +25°C, VCC1= VCC2= VCC3= VCCVCO= VCCMIX1= VCCMIX2 =8.5V, fRF =1MHz, fMOD= 400Hz at 30%
AMfIF1= 10.7MHz, fIF2= 450kHz, fxtal= 10.25MHz, in test or application circuit, (unless otherwise noted, VinRF
antenna input).
13/41
TDA7511
ELECTRICAL CHARACTERISTICS (continued)
TDA7511 14/41
FUNCTIONAL DESCRIPTION
1.1 FM Section
1.2 Mixer1, AGC and 1.IFMixer1 is a wide dynamic range stage with low noise and large input signal performance. The mixer1 tank can
be adjusted by software (IF1T). The AGC operates on different sensitivities and bandwidths (FMAGC) in order
to improve the input sensitivity and dynamic range (keying AGC). The output signals of AGC are controlled volt-
age and current for preamplifier and prestage pin diode attenuator. (look at Figure4)
Two 10.7MHz programmable amplifiers (IFG1, IFG2) correct the IF ceramic insertion loss and the costumer lev-
el plan application.
1.3 Mixer2, Limiter and DemodulatorIn this 2. mixer stage the first 10.7MHz IF is converted into the second 450kHz IF. A multi-stage limiter generates
signals for the complete integrated demodulator without external tank. MPX output DC offset compensation is
possible by software (DEM).
1.4 Quality Detection and ISS (look at Figure2)
FieldstrengthParallel to mixer2 input a 10.7MHz limiter generates a signal for digital IF counter and a fieldstrength output sig-
nal. This internal unweighted fieldstrength is used for keying AGC, adjacent channel and multipath detection
and is available at PIN14 (FSU) after +6dB buffer stage. The behaviour of this output signal can be corrected
for DC offset (SL) and slope (SMSL). The internal generated unweighted fieldstrength is filtered at PIN35 and
used for softmute function and generation of ISS filter switching signal for weak input level (sm).
Adjacent Channel DetectorThe input of the adjacent channel detector is AC coupled from internal unweighted fieldstrength. A programma-
ble highpass or bandpass (ACF) and amplifier (ACG) as well as rectifier determines the influences. This voltage
is compared with adjustable comparator1 thresholds (ACWTH, ACNTH). The output signal of this comparator
generates a DC level at PIN15 by programmable time constant. Time control (TISS) for a present adjacent chan-
nel is made by charge and discharge current after comparator1 in an external capacitance. The charge current
is fixed and the discharge current is controlled by I2 C Bus. This level produces digital signals (ac, ac+) in an
additional comparator4. The adjacent channel information is available as analog output signal after rectifier and
+8dB output buffer.
Multipath DetectorThe input of the multipath detector is AC coupled from internal unweighted fieldstrength. A programmable band-
pass (MPF) and amplifier (MPG) as well as rectifier determines the influences. This voltage is compared with
an adjustable comparator2 thresholds (MPTH). The output signal of this comparator2 is used for the "Milano"
effect. In this case the adjacent channel detection is switched off. The "Milano" effect is selectable by I2 C Bus
(MPOFF). The multipath information is available as analog output signal after rectifier and +8dB output buffer.
450kHz IF Narrow Bandpass Filter (ISS filter)The device gets an additional second IF narrow bandpass filter for suppression noise and adjacent channel sig-
nal influences. This narrow filter has three switchable bandwidthes, narrow range of 80kHz, mid range of
120kHz and 30KHz for weather band information. Without ISS filter the IF bandwidth (wide range) is defined
only by ceramic filter chain. The filter is switched in after mixer2 before 450kHz limiter stage. The centre fre-
quency and matching to the demodulator center frequency can be fine adjusted (AISS) by software..
Deviation DetectorIn order to avoid distortion in audio output signal the narrow ISS filter is switched OFF for present overdeviation.
15/41
TDA7511Hence the demodulator output signal is detected. A lowpass filtering and peak rectifier generates a signal that
is defined by software controlled current (TDEV) in an external capacitance. This value is compared with a pro-
grammable comparator3 thresholds (DWTH, DTH) and generates two digital signals (dev, dev+).
ISS Switch LogicAll digital signals coming from adjacent channel detector, deviation detector and softmute are acting via switch-
ing matrix on ISS filter switch. The IF bandpass switch mode is controlled by software (ISSON, ISS30, ISS80,
ISSCTL). The switch ON of the IF bandpass is also available by manipulation of the voltage at PIN15. Two ap-
plication modes are available (APPM). The conditions are described in table 37.
1.5 Soft Mute ControlThe external fieldstrength signal at PIN 35 is the reference for mute control. The startpoint, mute depth and slope
are programmable (SMTH, SMD, SLOPE) in a wide range. The time constant is defined by external capacitance.
Additional adjacent channel mute function is supported. A highpass filter with -3dB threshold frequency of
100kHz, amplifier and peak rectifier generates an adjacent noise signal from MPX output with the same time con-
stant for softmute. This value is compared with comparator5 thresholds (ACM). For present strong adjacent chan-
nel the MPX signal is attenuated typical 6dB.
1.6 AM SectionThe upconversion mixer1 is combined with a gain control circuit 1 sensing three input signals, narrow band in-
formation at PIN 39, upconversion signal at PIN 58 and wide band information at PIN 3.This gain control circuit
gives two output signals. The first one is a current for pin diode attenuator and the second one is a voltage for
preamplifier. It is possible to put in a separate narrow bandpass filter before mixer2 at PIN 58. The intervention
point for first AGC (AMAGC) is programmable by software.
The oscillator frequency for mixer1 is generated by dividing the FM VCO frequency (AMD).
In mixer2 the IF1 is downconverted into the IF2 450kHz. Before the output signal reaches the 450kHz tank an
attenuator for IF gain control 2 is passed. Mixer1 and mixer2 tanks are software controlled adjustable
(IF1T, IF2T).
After filtering by ceramic filter a 450kHz amplifier with a gain control 3 is included. The gain control 2 and 3 are
the second AGC and programmable too by software (DAGC). In order to avoid an oscillation in intervention point
it is important to know that the DAGC threshold has to be smaller than AMAGC! .
The demodulator is a peak detector. A further time constant with capacitor at pin40 produces a DC AGC refer-
ence voltage dependent on input signal. The time constant is switchable by ratio of 30. This is necessary for the
station search function. The switching is software controlled (AMSEEK).
An internal comparator compares the AGC voltage with a programmable reference (AMSS). Consequently it is
possible to generate a seekstop impulse over a defined range.
A separate output is available for AMIF stereo or a permanent seek stop signal(SSTSEL).
1.7 PLL and IF Counter Section
PLL Frequency Synthesizer BlockThis part contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is required
to build a complete PLL system for FM and AM upconversion. For auto search stop operation an IF counter
system is available.
The counter works in a two stages configuration. The first stage is a swallow counter with a two modulus (32/33)
precounter. The second stage is an 11-bit programmable counter.
The circuit receives the scaling factors for the programmable counters and the values of the reference frequen-
cies via an I2 C-Bus interface.The reference frequency is generated by an adjustable internal (XTAL) oscillator
followed by the reference divider. The reference and step-frequencies are free selectable (RC, PC).
Output signals of the phase detector are switching the programmable current sources. The loop filter integrates
TDA7511 16/41
their currents to a DC voltage.
The values of the current sources are programmable by 6 bits also received via the I2 C Bus (A, B, CURRH, LPF).
To minimize the noise induced by the digital part of the system, a special guard area is implemented.
The loop gain can be set for different conditions by setting the current values of the chargepump generator.
Frequency Generation for Phase ComparisonThe RF signals applies a two modulus counter (32/33) pre-scaler, which is controlled by a 5-bit divider(A). The
5-bit register (PC0 to PC4) controls this divider. In parallel the output of the prescaler connects to an 11-bit di-
vider(B). The 11-bit PC register (PC5 to PC15) controls this divider
Dividing range:
fOSC = (R+1) x fREF
fVCO = [33 x A + (B + 1 - A) x 32] x fREF
fVCO = (32 x B + A + 32) x fREF
Important: For correct operation: A ≤ 32; B ≥ A
Three State Phase ComparatorThe phase comparator generates a phase error signal according to phase difference between fSYN and fREF.
This phase error signal drives the charge pump current generator.
Charge Pump Current GeneratorThis system generators signed pulses of current. The phase error signal decides the duration and polarity of
those pulses. The current absolute values are programmable by A register for high current and B register for
low current.
Inlock DetectorSwitching the chargepump in low current mode can be done either via software or automatically by the inlock
detector, by setting bit LDENA to "1".
After reaching a phase difference of 10 - 40nsec and a delay of some times 1/fREF, the chargepump is forced
in low current mode. A new PLL divider alternation by I2 C-Bus will switch the chargepump in the high current
mode.
Few programmable phase errors (D0, D1) are available for inlock detection
The count of detected inlock informations, to release the inlock signal is adjustable (D2, D3), to avoid a switching
to low current during a frequency jump.
Low Noise CMOS Op-ampAn internal voltage divider at pin VREF2 connects the positive input of the low noise op-amp. The charge pump
output connects the negative input. This internal amplifier in cooperation with external components can provide
an active filter. The negative input is switchable to three input pins, to increase the flexibility in application. This
feature allows two separate active filters for different applications.
A logical "0" in the LPF register activates PIN LPFM, otherwise PIN LPAM is active. While the high current mode
is activated LPHC is switched on.
IF Counter BlockThe input signal for FM and AM upconversion is the same 10.7MHz IF level after limiter. The grade of integration
is adjustable by eight different measuring cycle times. The tolerance of the accepted count value is adjustable,
to reach an optimum compromise for search speed and precision of the evaluation.
For the FM range the center frequency of the measured count value is adjustable in 32 steps, to get the possi-
bility of fitting the IF-filter tolerance. In the AM upconversion range an IF frequency of 10.689MHz to 10.720MHz
with 1kHz steps is available.
17/41
TDA7511
The IF-Counter ModeThe IF counter works in 2 modes controlled by IFCM register.
Sampling TimerA sampling timer to generate the gate signal for the main counter is build with a 14-bit programmable counter
(IRC). In FM mode a 6.25kHz, in AM mode a 1kHz basically signal is generated. This is followed by an asyn-
chronous divider to generate several sampling times.
Intermediate Frequency Main CounterThis counter is a 11- 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to have
the possibility for an adjust to the frequency of the IF-filter. The counter length is automatic adjusted to the cho-
sen sampling time and the counter mode (FM, AM-UPC).
At the start the counter will be loaded with a defined value which is an equivalent to the divider value
(tSample xfIF).
If a correct frequency is applied to the IF counter frequency input at the end of the sampling time the main
counter is changing its state from 0h to 1FFFFFh.
This is detected by a control logic and an external search stop output is changing from LOW to HIGH. The fre-
quency range inside which a successful count result is adjustable by the EW bits.
tTIM = (IRC + 1) / fOSC
tCNT = (CF + 1697) / fIF FM mode
tCNT = (CF + 10689) / fIF AM up conversion mode
Counter result succeeded:
tTIM ≥ tCNT - tERR
tTIM ≤ tCNT + tERR
Counter result failed:
tTIM > tCNT + tERR
tTIM < tCNT - tERR
tTIM = IF timer cycle time
tCNT = IF counter cycle time
tERR = discrimination window (controlled by the EW registers)
The IF counter is only started by inlock information from the PLL part. It is enabled by software (IFENA).
Adjustment of the Measurement Sequence TimeThe precision of the measurements is adjustable by controlling the discrimination window. This is adjustable by
programming the control registers EW0 to EW2.
The measurement time per cycle is adjustable by setting the Register IFS0 - IFS2.
Adjust of the Frequency ValueThe center frequency of the discrimination window is adjustable by the control register CF0 to CF4.
TDA7511 18/41
1.8 I2 C-Bus InterfaceThe TDA 7511 supports the I2 C-Bus protocol. This protocol defines any device that sends data onto the bus as
a transmitter, and the receiving device as the receiver. The device that controls the transfer is a master and
device being controlled is the slave. The master will always initiate data transfer and provide the clock to trans-
mit or receive operations.
Data TransitionData transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL is HIGH
will be interpreted as START or STOP condition.
Start ConditionA start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level.
This "START" condition must precede any command and initiate a data transfer onto the bus. The TDA 7511
continuously monitors the SDA and SCL lines for a valid START and will not response to any command if this
condition has not been met.
Stop ConditionA STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH
level. This condition terminates the communication between the devices and forces the bus-interface of the TDA
7511 into the initial condition.
AcknowledgeIndicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. During the
9th clock cycle the receiver will pull the SDA line to LOW level to indicate it receive the eight bits of data.
Data TransferDuring data transfer the TDA 7511 samples the SDA line on the leading edge of the SCL clock. Therefore, for
proper device operation the SDA line must be stable during the SCL LOW to HIGH transition.
Device AddressingTo start the communication between two devices, the bus master must initiate a start instruction sequence, fol-
lowed by an eight bit word corresponding to the address of the device it is addressing.
The most significant 6 bits of the slave address are the device type identifier.
The TDA 7511 device type is fixed as "110001".
The next significant bit is used to address a particular device of the previous defined type connected to the bus.
The state of the hardwired PIN 41 defines the state of this address bit. So up to two devices could be connected
on the same bus. When PIN 41 is connected to VCC2 the address bit “1” is selected. In this case the AM part
doesn’t work. Otherwise the address bit “0” is selected (FM and AM is working). Therefor a double FM tuner
concept is possible.
The last bit of the start instruction defines the type of operation to be performed:
- When set to "1", a read operation is selected
- When set to "0", a write operation is selected
The TDA 7511 connected to the bus will compare their own hardwired address with the slave address being
transmitted, after detecting a START condition. After this comparison, the TDA 7511 will generate an "acknowl-
edge" on the SDA line and will do either a read or a write operation according to the state of R/W bit.
19/41
TDA7511
Write OperationFollowing a START condition the master sends a slave address word with the R/W bit set to "0". The TDA 7511
will generate an "acknowledge" after this first transmission and will wait for a second word (the word address
field). This 8-bit address field provides an access to any of the 32 internal addresses. Upon receipt of the word
address the TDA 7511 slave device will respond with an "acknowledge". At this time, all the following words
transmitted to the TDA 7511 will be considered as Data. The internal address will be automatically incremented.
After each word receipt the TDA 7511 will answer with an "acknowledge".
Read OperationIF the master sends a slave address word with the R/W bit set to "1", the TDA 7511 will transit one 8-bit data
word. This data word includes the following informations:
bit0 (ISS filter, 1= ON, 0= OFF)
bit1 (ISS filter bandwidth, 1= 80kHz, 0 = 120kHz)
bit2 (MPOUT,1 = multipath present, 0= no multipath)
bit3 (1= PLL is locked in , 0 = PLL is locked out).
bit4 (fieldstrength indicator, 1= lower as softmute threshold, 0= higher as softmute threshold)
bit5 (adjacent channel indicator, 1 = adjacent channel present, 0= no adjacent channel)
bit6 (deviation indicator, 1 = strong overdeviation present, 0= no strong overdeviation)
bit7 (deviation indicator, 1 = overdeviation present, 0= no overdeviation)
Software SpecificationThe interface protocol comprises:
- start condition (S)
- chip address byte
- subaddress byte
- sequence of data (N bytes + Acknowledge)
- stop condition (P)
Figure 1.
TDA7511 20/41
2.1 Address Organization
2.2 Control Register Function
Table 1.
Table 2.
21/41
TDA7511
Table 2. (continued)
