TDA7502013TR ,IN-CAR REMOTE AMPLIFIER DSPAbsolute Maximum RatingsSymbol Parameter Value UnitV DC Supply voltage -0.5 to 4.6 VddV Digital inp ..
TDA7505 , Car radio DSP for advanced signal processing
TDA7511 ,AM/FM TUNER FOR CAR RADIO HIFI APPLICATIONSBLOCK DIAGRAMLogic2/41AMIFin61 62 60 53 57 59 54 52 50 46 45 25 26 33 36 51 4956V VCC1 CC2 482I C B ..
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TDA7512F , FM car-radio tuner IC with intelligent selectivity system (ISS)
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THS4041CDR ,165-MHz C-Stable Voltage-Feedback Amplifier SLOS237B− MAY 1999 − REVISED FEBRUARY 2000THS ..
THS4041ID ,165-MHz C-Stable Voltage-Feedback Amplifiermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V . . . ..
THS4041IDGN ,165-MHz C-Stable Voltage-Feedback Amplifierelectrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted)A CC Ldynamic ..
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TDA7502013TR
IN-CAR REMOTE AMPLIFIER DSP
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TDA7502September 2004
FEATURES 24-Bit FIXED-POINT DSP CORE DELIVERING
UP TO 50 MIPS 2 x 1024 x 24 Bit OF RAM FOR X AND Y DATA
MEMORY. 3072 x 24 Bit OF RAM FOR PROGRAM ALSO
USABLE FOR DELAY SERIAL AUDIO INTERFACE. DEBUG PORT. CONTROL INTERFACE FOR EXTERNAL
GPIOs, INTERRUPTS, AND RESET. SPI AND I2 C FOR COMMUNICATION
BETWEEN EXTERNAL MICRO AND DSP.
BOTH MASTER AND SLAVE OPERATING
MODES. PLL CLOCK OSCILLATOR 5V-TOLERANT 3.3V I/O INTERFACE
DESCRIPTIONThis device is a high-performance, fully programma-
ble DSP, suitable for a wide range of applications and
particularly for Audio and Sound Processing. It con-
tains a 24-bit 50 MIPS DSP core, several interfaces
for control and data, plus a configurable PLL.
The computational power and the memory configura-
tion make this device particularly suitable for in car
equalisation. This device will offer the best trade-off
between performance and cost when coupled with
the TDA7535, or other devices of the same family. A
library of sound processing functions is available for
this device; some of these functions are: parametric
equaliser, cross over filters, acoustic delay, dynamic
compression, Vol/Bass/Treble/Fader, active equali-
sation, Stereo Spatial Enhancement and more.
IN-CAR REMOTE AMPLIFIER DSP
Figure 2. Block DiagramRev. 9
TDA7502
Table 2. Absolute Maximum Ratings(*) When the IC is powered.
Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.
Figure 3. Pin Connection (Top view)
Table 3. Thermal Data(*) In still air.
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TDA7502
Table 4. Pin Description
TDA7502 Notes:1. XTI and XTO are not 5V tolerant
Table 4. Pin Description (continued)
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TDA7502
Table 5. Recommended DC Operating Conditions
Table 6. Power ConsumptionNote: 50MHz internal DSP clock
Table 7. Pll CharacteristicsNote: 1. Depending on VCO output frequency.
2. Fdsp = Fvco/2 when PLL is running
Table 8. Oscillator Characteristics
Table 9. General Interface Electrical CharacteristicsNote:1. The leakage currents are generally very small, <1nA. The value given here, 1mA, ia amaximum that can occur after an Electrostatic
Stress on the pin. Human Body Model.
Table 10. Low Voltage TTL Interface DC Electrical Characteristics
TDA7502 Note:1. TTL specifications only apply to the supply voltage range Vdd = 3.0V to 3.6V Takes into account 200mV voltage drop in both supply lines. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Table 11. DSP Core
Figure 4. Maximum DSP Clock Frequency (Fdsp) Versus Junction Temperature (Tj)
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TDA7502 SAI INTERFACE
Figure 5. SAI Timings
Table 12. Note TDSP = dsp master clock cycle time = 1/FDSP
Figure 6. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
TDA7502
Figure 7. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1.
Figure 8. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0.
Figure 9. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0.Note: some timing is used for transmitter and receiver
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TDA7502
4SPI INTERFACES
Figure 10. SPI Clocking scheme.
TDA7502
Table 13. Debug Port Interface
Figure 11. Debug Port Serial Clock Timing.
Figure 12. Debug Port Acknowledge Timing.
