TDA7500ATR ,DIGITAL AM/FM SIGNAL PROCESSORTDA7500ADIGITAL AM/FM SIGNAL PROCESSOR■ FULL SOFTWARE FLEXIBILITY WITH TWO 24X24 BIT DSP CORES■ SOF ..
TDA7500ATR ,DIGITAL AM/FM SIGNAL PROCESSORBLOCK DIAGRAManalog inanalog audio outSC SC SC SC SC SCSD SDFilter Filter Filter Filter Filter Filt ..
TDA7501 ,LINE-DRIVER FOR DIGITAL CARRADIO SIGNAL PROCESSORELECTRICAL CHARACTERISTICS (continued)Symbol Parameter Test Condition Min. Typ. Max. UnitSPEAKER OU ..
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TDA7501TR ,LINE-DRIVER FOR DIGITAL CARRADIO SIGNAL PROCESSORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Operating Supply Voltage V 10.5 VDDmax DDV Ope ..
TDA7502 ,IN-CAR REMOTE AMPLIFIER DSPTDA7502IN-CAR REMOTE AMPLIFIER DSP■ 24-Bit FIXED-POINT DSP CORE DELIVERING UP TO 50 MIPS■ 2 x 1024 ..
THS4032CDR ,100-MHz Low Noise Voltage-Feedback Amplifier, DualBlock Diagrams. 20Information..... 339.3 Feature Description.... 214 Revision HistoryNOTE: Page num ..
THS4032ID ,100-MHz Low Noise Voltage-Feedback Amplifier, Dual SLOS224H–JULY 1999–REVISED JUNE 20165 Device Comparison Table(1)Table 1. Available OptionsPACKAGED ..
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THS4032IDGN ,100-MHz Low Noise Voltage-Feedback Amplifier, Dual.(2) The D and DGN packages are available taped and reeled. Add an R suffix to the device type (tha ..
THS4041CD ,165-MHz C-Stable Voltage-Feedback Amplifiermaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
THS4041CDGN , 165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
TDA7500ATR
DIGITAL AM/FM SIGNAL PROCESSOR
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TDA7500ADecember 2001 FULL SOFTWARE FLEXIBILITY WITH TWO
24X24 BIT DSP CORES SOFTWARE AM/FM, AUDIO AND SOUND-
PROCESSING HARDWARE RDS FILTER, DEMODULATOR
& DECODER INTEGRATED CODEC (4ADCs, 6DACs) IIC AND SPI CONTROL INTERFACES SPI DEDICATED TO DISPLAY MICRO 6 CHANNEL SERIAL AUDIO INTERFACE
(SAI) SPDIF RECEIVER WITH SAMPLE RATE
CONVERTER EXTERNAL MEMORY INTERFACE (EMI) DOUBLE DEBUG INTERFACE ON-CHIP PLL 5V-TOLERANT 3V I/O INTERFACE 12x2 MULTIFUNCTION GENERAL PURPOSE
I/O PORTS
DESCRIPTIONThe TDA7500A is an integrated circuit implementing
a fully digital, integrated and advanced solution to
perform the signal processing in front of the power
amplifier and behind the AM/FM tuner or any other
audio source. The chip integrates two 45 MIPs DSP
cores: one for stereo decoding, noise blanking, weak
signal processing and multipath detection and one for
sound processing, Dolby B, echo and noise cancel-
ling for the telephone.
DIGITAL AM/FM SIGNAL PROCESSOR
BLOCK DIAGRAM
TDA7500A 2/40
DESCRIPTION (continued)An I2 C/SPI interface is implemented for control and communication with the main micro. A separate SPI is avail-
able to interface the display micro.The DSP cores are integrated with their associated data and program mem-
ories. The peripherals and interfaces I2 C, SPI, Serial Audio Interface (SAI), PLL Oscillator, External Memory
Interface, (EMI), General Purpose I/O register (Port A) and the D/A registers are connected to and controlled by
DSP0, whereas the A/D registers, the SPDIF and the General Purpose I/O register (Port B) are connected to
and controlled by DSP1. An hardware RDS filter , demodulator and decoder block is also embedded. No support
is needed from the DSPs but at initialisation so that RDS can work in background and in parallel with other DSP
processing. Separated Debug and Test Interfaces are connected to both DSP cores.
The TDA7500A is supposed to be used in kit with the TDA7501 or any other device of the same family. Thanks
to the serial audio interface also digital sources can be processed and a direct output to a digital bus is also
available.
The flexibility allowed by the wide memory space and by the two powerfull DSP cores make the TDA7500A us-
able for different applications. In example, inside the main radio as an audio co-processor or to perform the sig-
nal processing and equalisation associated to a digital power amplifier.
ABSOLUTE MAXIMUM RATINGSWarning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.
THERMAL DATANote:1. In still air On 4 layers board with soldered slug Measured on top side of the package
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TDA7500A
PIN DESCRIPTION
TDA7500A 4/40
PIN DESCRIPTION (continued)
5/40
TDA7500A
PIN DESCRIPTION (continued)
TDA7500A 6/40
PIN DESCRIPTION (continued)
7/40
TDA7500A
PIN DESCRIPTION (continued)
TDA7500A 8/40
PIN DESCRIPTION (continued)
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TDA7500A
I/O DEFINITION AND STATUSO: logic low output
X: undefined input/output
Z: high impedance
1: logic input output
PIN DESCRIPTION (continued)
TDA7500A 10/40
I/O DEFINITION AND STATUS (continued)
11/40
TDA7500A
I/O DEFINITION AND STATUS (continued)
TDA7500A 12/40
I/O DEFINITION AND STATUS (continued)
13/40
TDA7500A
I/O DEFINITION AND STATUS (continued)
TDA7500A 14/40
Output PP: Push-Pull/ OD: Open-Drain
5VT input: TTL Five Volt Tolerant Input - Schmitt-trigger for all inputs.
I/O DEFINITION AND STATUS (continued)
15/40
TDA7500A
PIN CONNECTION (Top view)
RECOMMENDED DC OPERATING CONDITIONS
POWER CONSUMPTIONNote: 45MHz internal DSP clock, 4ADC and 6DAC enabled.
PLL CHARACTERISTICSNote: 1. Depending on VCO output frequency.
2. Fdsp = Fvco/2 when PLL is running
TDA7500A 16/40
OSCILLATOR CHARACTERISTICS
GENERAL INTERFACE ELECTRICAL CHARACTERISTICSNote:1. The leakage currents are generally very small, <1nA. The value given here, 1mA, ia amaximum that can occur after an Electrostatic
Stress on the pin. Human Body Model.
LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICSNote:1. Takes into account 200mV voltage drop in both supply lines. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
LOW VOLTAGE TTL INTERFACE DC ELECTRICAL CHARACTERISTICSNote:1. TTL specifications only apply to the supply voltage range Vdd = 3.0V to 3.6V Takes into account 200mV voltage drop in both supply lines. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
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TDA7500A
DSP CORE
FM Stereo Decoder
ADC ELECTRICAL CHARACTERISTCS (Tamb = 25°C, VCC = 3.3V, measurement bandwidth 10Hz to 20KHz,A-Weighted Filter.)
Note1: 0dB reference at 0.75Vrms input
ADC ELECTRICAL CHARACTERISTCS (Tamb = 25°C, VCC = 3.3V, measurement bandwidth 10Hz to 53KHz.)
TDA7500A 18/40
ADC ELECTRICAL CHARACTERISTCS (Tamb = 25°C, VCC = 3.3V, measurement bandwidth 10Hz to
160KHz.)
DAC PERFORMANCE (Tamb = 25°C, VCC = 3.3V, measurement bandwidth 10Hz to 20KHz, A-Weighted Filter0dB gain, output load 30kΩ)
19/40
TDA7500A
SAI INTERFACE
Figure 1. SAI TimingsNote TDSP = dsp master clock cycle time = 1/FDSP
Figure 2. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
TDA7500A 20/40
Figure 3. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1.
Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0.
Figure 5. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0.
