TDA7468D13TR Fast Delivery |IC PHOENIX CO.,LIMITED

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TDA7468D13TR
TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND
1/22
TDA7468D
June 2004
1FEATURES INPUT MULTIPLEXER 4 STEREO INPUTS SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT BASS ALC TREBLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS EXTERNALLY ADJUSTABLE SURROUND
2DESCRIPTION
The TDA7468D is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applications in Hi-Fi systems.
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained
TWO BANDS DIGITALLY CONTROLLED
AUDIO PROCESSOR WITH BASS ALC SURROUND
Figure 2. PIN CONNECTION (Top view)
REV. 1
TDA7468D
Figure 3. BLOCK DIAGRAM
3/22
TDA7468D
Table 2. ABSOLUTE MAXIMUM RATINGS
Table 3. THERMAL DATA
Table 4. QUICK REFERENCE DATA
TDA7468D
ELECTRICAL CHARACTERISTICS
(refer to the test circuit Tamb = 25°C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise
specified)
5/22
TDA7468D
ELECTRICAL CHARACTERISTICS (continua)
(refer to the test circuit Tamb = 25°C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise
specified)
TDA7468D
Figure 4. TEST CIRCUIT
7/22
TDA7468D APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -63dB (mute) with 1dB
step resolution for this first one, 0 to 24dB (mute) with 8dB step resolution for the last one.
The very high resolution allows the implementation of systems free from any noisy acoustical effect.
The TDA7468D audioprocessor provides 2 bands tones control.
3.1 Bass, Stages
The Bass cell has an internal resistor Ri = 44KΩ typical.
Several filter types can be implemented, connecting external components to the Bass IN and OUT pins.
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
Viceversa, once FC, AV, and Ri internal value are fixed, the external components values will be:
3.2 Treble Stage
The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and
an external capacitor connected between treble pins and ground.
3.3 CREF
The suggested 10µ F reference capacitor (CREF) value can be reduced to 4.7µ F if the application requires
faster power ON.
Figure 5.
TDA7468D 2 C BUS INTERFACE
Data transmission from microprocessor to the TDA7468D and vice versa takes place through the 2 wires2 C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 6, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig.7 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
4). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse. The audio processor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time.
In this case the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µ P can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data. This approach of
course is less protected from misworking.
Figure 6. Data Validity on the I2 CBUS
Figure 7. Timing Diagram of I2 CBUS
Figure 8. Acknowledge on the I2 CBUS
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TDA7468D SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7468D address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
ACK = Acknowledge
S = Start; P = Stop
A = Address
B = Auto Increment EXAMPLES
6.1 No Incremental Bus
The TDA7468D receives a start condition, the correct chip address, a subaddress with the B = 0 (no in-
cremental bus), N-data (all these data concern the subaddress selected), a stop condition.
6.2 Incremental Bus
The TDA7468D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incre-
mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS
from "XXX1000" to "XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the
loop etc, and at the end it receivers the stop condition.
Table 5. POWER ON RESET CONDITION
TDA7468D DATA BYTES
Address = (HEX) 10001000.
Table 6. FUNCTION SELECTION: First byte (subaddress)
B = 1: INCREMENTAL BUS; ACTIVE
B = 0: NO INCREMENTAL BUS
X = INDIFFERENT 0/1
Table 7. INPUT SELECTION & MIC
11/22
TDA7468D
Table 8. INPUT GAIN SELECTION
GAIN = 0 to 30dB
Table 9. SURROUND

Partno	Mfg	Dc	Qty	Available	Descript
TDA7468D13TR	STM	N/a	38	avai	TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND
TDA7468D13TR	ST	N/a	381	avai	TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND
TDA7468D13TR	ST,ST	N/a	1000	avai	TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND