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TDA7466
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SRS SURROUND SOUND AND VOICE CANCELLER
TDA7466DIGITALLY CONTROLLED AUDIO PROCESSOR WITH
SRS SURROUND SOUND AND VOICE CANCELLER
1 STEREO INPUT
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
TREBLE MIDDLE AND BASS CONTROL
VOICE CANCELLER IS AVAILABLE
STEREO SRS SURROUND SOUND WITH
CENTER & SPACE CONTROL IS AVAILABLE
THREE STANDARD SURROUND MODES
ARE AVAILABLE:
- MUSIC IN 4 DIFFERENT SELECTABLE
RESPONSES
- MOVIE AND SIMULATED IN 256
DIFFERENT SELECTABLE RESPONSES
2 SPEAKERS OUTPUTS
- INDEPENDENT ATTENUATORS IN 1dB
STEP FOR BALANCE FACILITY
- ZERO CROSSING ATTENUATION AVAILABLE
- AVAILABILITY OF LOUDSPEAKERS
EQUALIZATION FIXED BY EXTERNAL
COMPONENTS
- INDEPENDENT MUTE FUNCTION
2 RECORD OUTPUTS
- INDEPENDENT ATTENUATORS IN 1dB
STEP FOR BALANCE FACILITY
- MUX AVAILABLE FOR PROCESSES SIGNAL
SELECTION
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
DESCRIPTIONThe TDA7466 is a volume tone (bass middle and
treble) balance (Left/Right) processors with stereo
SRS and voice canceller for quality audio applica-
tions in car radio, Hi-Fi, TV systems.
It reproduces SRS (Sound Retrieval System)
sound by external components and surround
sound by using phase shifters and a signal ma-
trix. The AC signal setting is obtained by resistor
networks and switches combined with operational
amplifiers according to the SRS laboratories
specification. Control of all the functions is ac-
complished by serial bus.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
PIN CONNECTION
The Device incorporates the SRS
(Sound Retrieval System) under
licence from SRS Labs, Inc.
BLOCK DIAGRAM
TDA74662/21
THERMAL DATA
QUICK REFERENCE DATA
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz
unless otherwise specified)
SUPPLY
TDA7466
ELECTRICAL CHARACTERISTICS (continued)SUPPLY
STANDARD SURROUND SOUND MATRIX
TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1
TDA74664/21
ELECTRICAL CHARACTERISTICS (continued)SRS SURROUND SOUND MATRIX
TDA7466
ELECTRICAL CHARACTERISTICS (continued)
TDA74666/21
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7466 and viceversa takes place through the
2 wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 3: Data Validity on the I2 CBUS
Figure 4: Timing Diagram of I2 CBUS
Figure 5: Acknowledge on the I2 CBUS
TDA7466
SOFTWARE SPECIFICATIONaddress
A subaddress bytes
ACK = Achnowledge
S = Start
P = Stop
A = Address
B = Auto Increment
EXAMPLES
No Incremental BusThe TDA7466 receives a start condition, the cor-
rect chip address, a subaddress with the MSB = 0
(no incremental bus), N-data (all these data con-
cern the subaddress selected), a stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU306
SUBADDRESS DATA
Incremental BusThe TDA7466 receives a start condition, the cor-
rect chip address, a subaddress with the MSB = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
SUBADDRESS from "1XXX1010" to "1XXX1111"
of DATA are ignored.
The DATA 1 concerns thesubaddress sent, and
the DATA 2 concerns the subaddress sent plus
one in the loop etc. and, at the end, it receives the
stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU307
SUBADDRESS DATA 1 to DATA n
TDA74668/21
INPUT ATTENUATION = 0 ∼ -31.5dB
INPUT ATTENUATION SELECTIONB = 1 INCREMENTAL BUS; ACTIVE
B = 0 NO INCREMENTAL BUS;
X = DONT’CARE
The first byte (subaddress)
DATA BYTES (Address = 80(HEX)):
FUNCTION SELECTION:
TDA7466
STANDARD SURROUND SELECTION
TDA746610/21
When external components aren’t connected, the data from NATURAL BASE must put "OFF"
TDA7466
