TDA7449 ,TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSORTDA7449®TONE CONTROLDIGITALLY CONTROLLED AUDIO PROCESSORINPUT MULTIPLEXER- 2 STEREO INPUTS- SELECTA ..
TDA7449D , TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
TDA7449L ,LOW COST DIGITALLY CONTROLLED AUDIO PROCESSORTDA7449L®LOW COSTDIGITALLY CONTROLLED AUDIO PROCESSORINPUT MULTIPLEXER- 2 STEREO INPUTS- SELECTABLE ..
TDA7451 ,4x7W OR 2x22W CAR RADIO POWER AMPLIFIER PLUS TRIPLE POWER SUPPLYTDA7451®4x7W OR 2x22W CAR RADIO POWER AMPLIFIER PLUSTRIPLE POWER SUPPLYPRELIMINARY DATAHIGH OUTPUT ..
TDA7454 ,4 x 35W HIGH EFFICIENCY QUAD BRIDGE CAR RADIO AMPLIFIERTDA74544 x 35W HIGH EFFICIENCY QUAD BRIDGECAR RADIO AMPLIFIERHIGH OUTPUT POWER CAPABILITY:MULTIPOWE ..
TDA7460ND ,CAR RADIO SIGNAL PROCESSORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVS Operating Supply Voltage 10.5 VTamb Operating ..
THS1031IPW ,10-Bit, 30 MSPS ADC Single Ch., Integ. Pgmable Digital Clamp & Gain, Out of Range Indic., PowerDownTHS1031 3-V TO 5.5-V, 10-BIT, 30 MSPSCMOS ANALOG-TO-DIGITAL CONVERTERSLAS242E – NOVEMBER 1999 – REV ..
THS1040IDW ,10 Bit, 40 MSPS Low Power ADC
THS1040IPW ,10 Bit, 40 MSPS Low Power ADC
THS1041IDW ,10 Bit, 40 MSPS Low Power ADC With PGA and Internal Precision ClampFEATURESFor more design flexibility, the internal reference can be Analog Supply 3 Vbypassed to us ..
THS117 ,HALL SENSOR GaAs ION IMPLANTED PLANAR TYPE HIGH STABILITY CONTROL DIGITAL TACHOMETER CRANK SHAFR POSITION SENSORELECTRICAL CHARACTERISTICS (Ta = 25°C)1nterna1Resistance(sput)lRdi=5mAl450l-l900lnResidua1vo1tageRa ..
THS118 ,HALL SENSOR GaAs ION IMPLANTED PLANAR TYPE HIGH STABILITY CONTROL DIGITAL TACHOMETER CRANK SHAFR POSITION SENSORELECTRICAL CHARACTERISTICS (Ta = 25°C)1nterna1Resistance(sput)lRdi=5mAl450l-l900lnResidua1vo1tageRa ..
TDA7449
TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
TDA7449TONE CONTROL
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- 2 STEREO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
TREBLE, AND BASS CONTROL IN 2.0dB
STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
- TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTIONThe TDA7449 is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applications in TV systems.
Selectable input gain is provided. Control of all
the functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
QUICK REFERENCE DATA
TDA74492/17
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ,RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified)
SUPPLY
NOTE1:
1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device.
2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
TDA74493/17
ELECTRICAL CHARACTERISTICS (continued.)
TDA74494/17
TEST CIRCUIT
P.C.Board
TDA74495/17
APPLICATION SUGGESTIONSThe first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution.
The very high resolution allows the implementation
of systems free from any noisy acoustical effect.
The TDA7449 audioprocessor provides 2 bands
tones control.
Bass, StagesThe Bass cell has an internal resistor Ri = 25KΩ
typical.
Several filter types can be implemented, connect-
ing external components to the Bass IN and OUT
pins.
The fig.1 refers to basic T Type Bandpass Filter
starting from the filter component values (R1 in-
ternal and R2,C1,C2 external) the centre fre-
quency Fc, the gain Av at max. boost and the fil-
ter Q factor are computed as follows:
FC = 1
2 ⋅ π ⋅√ Ri, R2, C1, C2
AV = R2 C2 + R2 C1 + Ri C1
R2 C1 + R2 C2
Q = √ Ri R2 + C1 C2
R2 C1 + R2 C2
Viceversa, once Fc, Av, and Ri internal value are
fixed, the external components values will be:
C1 = AV − 1
2 ⋅ π ⋅ Ri ⋅ Q C2 = Q2 ⋅ C1
(AV − 1) Q2
R2 = AV − 1 − Q2
2 ⋅ π ⋅ C1 ⋅ FC ⋅ (AV − 1) ⋅Q
Treble StageThe treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25KΩ
typical) and an external capacitor connected be-
tween treble pins and ground
Typical responses are reported in Figg. 10 to 13.
CREFThe suggested 10μF reference capacitor (CREF)
value can be reduced to 4.7μF if the application
requires faster power ON.
Figure 1.
Figure 2: THD vs. frequency Figure 3: THD vs. RLOAD
TDA74496/17
Figure 4: Channel separation vs. frequency
Figure 6: Treble response
Figure 5: Bass response
TDA74497/17
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7449 and vice versa takes place through the
2 wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data ValidityAs shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop ConditionsAs shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte FormatEvery byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
AcknowledgeThe master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audio processor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audio processor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without AcknowledgeAvoiding to detect the acknowledge of the audio
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 3: Data Validity on the I2 CBUS
Figure 4: Timing Diagram of I2 CBUS
Figure 5: Acknowledge on the I2 CBUS
TDA74498/17
SOFTWARE SPECIFICATIONInterface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte, containing the TDA7449
address
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU420
SUBADDRESS DATA 1 to DATA n
EXAMPLES
No Incremental BusThe TDA7449 receives a start condition, the cor-
rect chip address, a subaddress with the B = 0
(no incremental bus), N-data (all these data con-
cern the subaddress selected), a stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU421
SUBADDRESS DATA
Incremental BusThe TDA7449 receive a start conditions, the cor-
rect chip address, a subaddress with the B = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
SUBADDRESS from "XXX1000" to "XXX1111" of
DATA are ignored.
The DATA 1 concern the subaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU422
SUBADDRESS DATA 1 to DATA n
TDA74499/17
