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TDA7442-TDA7442D
TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR
TDA7442
TDA7442DTONE CONTROL AND SURROUND
DIGITALLY CONTROLLED AUDIO PROCESSOR
4 STEREO INPUTS
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
TREBLE AND BASS CONTROL
TWO SURROUND MODE AVAILABLE WITH
4 SELECTABLE RESPONSES:
- MUSIC
- SIMULATED STEREO
TWO SPEAKER ATTENUATORS:
- 2 INDEPENDENT SPEAKER CONTROLS
IN 1dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
2 MONITOR OUTPUT (ONLY FOR TDA7442)
DESCRIPTIONThe TDA7442/42D is volume tone (bass and
treble) balance (Left/Right) processors for quality
audio applications in TV and Hi-Fi systems.
It reproduces surround sound by using a pro-
grammable phase shifter. Control of all the func-
tions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the BIPOLAR/CMOS Technology used,
Low Distortion, Low Noise and DC stepping are
obtained.
PIN CONNECTIONS
BLOCK DIAGRAM (TDA7442D)
BLOCK DIAGRAM (TDA7442)
TDA7442 - TDA7442D2/16
QUICK REFERENCE DATA
THERMAL DATA
ABSOLUTE MAXIMUM RATINGS
TDA7442 - TDA7442D3/16
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz
unless otherwise specified)
SUPPLY
SURROUND SOUND MATRIX
TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1
TDA7442 - TDA7442D4/16
ELECTRICAL CHARACTERISTICS (continued)
TDA7442 - TDA7442D5/16
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7442D and viceversa takes place through the
2 wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 3: Data Validity on the I2 CBUS
Figure 4: Timing Diagram of I2 CBUS
Figure 5: Acknowledge on the I2 CBUS
TDA7442 - TDA7442D6/16
SOFTWARE SPECIFICATIONaddress
A subaddress bytes
ACK = Achnowledge
S = Start
P = Stop
A = Address
B = Auto Increment
EXAMPLES
No Incremental BusThe TDA7442D receives a start condition, the
correct chip address, a subaddress with the MSB
= 0 (no incremental bus), N-datas (all these datas
concern the subaddress selected), a stop condi-
tion.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU306
SUBADDRESS DATA
Incremental BusThe TDA7442D receive s a start condition, the
correct chip address, a subaddress with the MSB
= 1 (incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
SUBADDRESS from "1XXX1010" to "1XXX1111"
of DATA are ignored.
The DATA 1 concern thesubaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU307
SUBADDRESS DATA 1 to DATA n
TDA7442 - TDA7442D7/16
INPUT ATTENUATION = 0 ∼ -31.5dB
INPUT ATTENUATION SELECTIONB = 1 incremental bus; active
B = 0 no incremental bus;
X = indifferent 0,1
The first byte (subaddress)
DATA BYTESAddress = 80(HEX)
FUNCTION SELECTION:
TDA7442 - TDA7442D8/16
