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TDA7440D013TR
TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
1/17
TDA7440D
April 1999 FEATURES INPUT MULTIPLEXER 4 STEREO INPUTS SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE AND BASS CONTROL IN 2.0dB
STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS DESCRIPTION
The TDA7440D is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applications in Hi-Fi systems.
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained
TONE CONTROL
DIGITALLY CONTROLLED AUDIO PROCESSOR
Figure 2. Block Diagram
REV. 3
TDA7440D
Figure 3. Pin Connection (Top view)
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
Table 4. Quick Reference Data
3/17
TDA7440D
Table 5. Electrical Characteristcs
Refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless
otherwise specified.
NOTE1:
1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device.
2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
TDA7440D
Figure 4. Test Circuit
Table 5. Electrical Characteristcs (continued)
Refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless
otherwise specified.
5/17
TDA7440D APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first
one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution
allows the implementation of systems free from any noisy acoustical effect.
The TDA7440D audioprocessor provides 3 bands tones control.
3.1 Bass Stage
Several filter types can be implemented, connecting external components to the Bass IN and OUT pins.
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
Figure 5.
Treble Stage
The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and
an external capacitor connected between treble pins and ground.
Typical responses are reported in Figg. 14 to 17.
CREF
The suggested 10mF reference capacitor (CREF) value can be reduced to 4.7mF if the application re-
quires faster power ON.C 1π⋅⋅
---- ---------------=V
R2 C2 R2 C1 Ri C1++
R2 C1 R2 C2+----------- --------------- --------------------------------------= R2 C1 C2⋅⋅ ⋅
R2 C1 R2 C2+--------------------------------------------------= AV 1–πFCRi Q⋅⋅ ⋅ ⋅----------------------------------------- - C2 Q2 C1⋅V 1– Q2–
---------- ------------------- - R2 AV 1– Q2–π C1FC AV 1–() Q⋅⋅ ⋅ ⋅ ⋅-- --------------- ---------------- --------------- -----------------------===
TDA7440D
Figure 6. THD vs. frequency
Figure 7. THD vs. RLOAD
Figure 8. Channel separation vs. frequency
Figure 9. Bass response
Figure 10. Treble responsey
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TDA7440D2 C BUS INTERFACE
Data transmission from microprocessor to the TDA7440D and vice versa takes place through the 2 wires2 C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig. 12 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (µ P) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
13). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µ P can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 11. Data Validity on the I2 CBUS
Figure 12. Timing Diagram of I2 CBUS
Figure 13. Acknowledge on the I2 CBUS
TDA7440D SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7440D A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
5.1 EXAMPLES
5.1.1 No Incremental Bus
The TDA7440D receives a start condition, the correct chip address, a subaddress with the B = 0 (no in-
cremental bus), N-datas (all these data concern the subaddress selected), a stop condition.
5.1.2 Incremental Bus
The TDA7440D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incre-
mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS
from "XXX1000" to "XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent
in the loop etc, and at the end it receivers the stop condition.
9/17
TDA7440D
5.2 POWER ON RESET CONDITION
Table 6.
5.3 DATA BYTES
Address = 88 HEX (ADDR:OPEN).
Table 7. FUNCTION SELECTION: First byte (subaddress)
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON’T CARE
In Incremental Bus Mode, the "not used" function must be addressed in any case. For example to refresh
"Volume = 0dB" and Speaker_R = -40dB", the following bytes must be sent:
Table 8.
Table 9. INPUT SELECTION

Partno	Mfg	Dc	Qty	Available	Descript
TDA7440D013TR	ST,ST	N/a	14000	avai	TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR