TDA7440D ,TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSORTDA7440D®TONE CONTROLDIGITALLY CONTROLLED AUDIO PROCESSORINPUT MULTIPLEXER- 4 STEREO INPUTS- SELECT ..
TDA7440D013TR ,TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSORTDA7440DTONE CONTROLDIGITALLY CONTROLLED AUDIO PROCESSOR1
TDA7442 ,TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Operating Supply Voltage 11 VST Operating Ambi ..
TDA7442D ,TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSORTDA7442TDA7442D®TONE CONTROL AND SURROUNDDIGITALLY CONTROLLED AUDIO PROCESSOR4 STEREO INPUTS INPUT ..
TDA7448 ,6 CHANNELS VOLUME CONTROLLERTDA74486 CHANNEL VOLUME CONTROLLERPRODUCT PREVIEW■ 6 CHANNEL INPUTS■ 6 CHANNEL OUTPUTS■ VOLUME ATTE ..
TDA7448. ,6 CHANNELS VOLUME CONTROLLERTDA74486 CHANNEL VOLUME CONTROLLERPRODUCT PREVIEW■ 6 CHANNEL INPUTS■ 6 CHANNEL OUTPUTS■ VOLUME ATTE ..
THS0842 ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownblock diagramAVDDDRV DVDD DDCOUTCLK Timing CircuitryCOUTI +Sample& HoldI –DA(7–0)3-State8 BITBUSMUX ..
THS0842IPFB ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownTHS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTERWITH SINGLE OR DUAL PARALLE ..
THS10064 ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerFEATURES DESCRIPTION* High-Speed 6 MSPS ADCThe THS10064 is a CMOS, low-power, 10-bit, 6 MSPS* 4 Ana ..
THS10064CDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTHS10064DGND to D ..
THS10064CDAR ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerELECTRICAL CHARACTERISTICS over recommended operating conditions, AV = 5 V, DV = BV = 3.3 V, f = ..
THS10064IDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low Powermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
TDA7440D
TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
TDA7440DTONE CONTROL
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- 4 STEREO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
TREBLE AND BASS CONTROL IN 2.0dB
STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
- TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTIONThe TDA7440D is a volume tone (bass and
treble) balance (Left/Right) processor for quality
audio applications in Hi-Fi systems.
Selectable input gain is provided. Control of all
the functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION (Top view)
QUICK REFERENCE DATA
TDA7440D2/16
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ,RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified)
SUPPLY
NOTE1:
1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device.
2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
TDA7440D3/16
ELECTRICAL CHARACTERISTICS (continued.)
TEST CIRCUIT
TDA7440D4/16
APPLICATION SUGGESTIONSThe first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution.
The very high resolution allows the implementation
of systems free from any noisy acoustical effect.
The TDA7440D audioprocessor provides 3 bands
tones control.
Bass StageSeveral filter types can be implemented, connect-
ing external components to the Bass IN and OUT
pins.
The fig.1 refers to basic T Type Bandpass Filter
starting from the filter component values (R1 in-
ternal and R2,C1,C2 external) the centre fre-
quency Fc, the gain Av at max. boost and the fil-
ter Q factor are computed as follows:
FC = 1
2 ⋅ π ⋅√ R1 ⋅ R2 ⋅ C1 ⋅ C2
AV = R2 C2 + R2 C1 + Ri C1
R2 C1 + R2 C2
Q = √ R1 ⋅ R2 ⋅ C1 ⋅ C2
R2 C1 + R2 C2
Viceversa, once Fc, Av, and Ri internal value are
fixed, the external components values will be:
C1 = AV − 1
2 ⋅ π ⋅ FC ⋅ Ri ⋅ Q C2 = Q2 ⋅ C1
AV − 1 − Q2
R2 = AV − 1 − Q2
2 ⋅ π ⋅ C1 ⋅ FC ⋅ (AV − 1) ⋅Q
Treble StageThe treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25KΩ
typical) and an external capacitor connected be-
tween treble pins and ground
Typical responses are reported in Figg. 10 to 13.
CREFThe suggested 10μF reference capacitor (CREF)
value can be reduced to 4.7μF if the application
requires faster power ON.
Figure 1.
Figure 2: THD vs. frequency Figure 3: THD vs. RLOAD
TDA7440D5/16
Figure 4: Channel separation vs. frequency
Figure 6: Treble response
Figure 5: Bass response
TDA7440D6/16
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7440D and vice versa takes place through
the 2 wires I2 C BUS interface, consisting of the
two lines SDA and SCL (pull-up resistors to posi-
tive supply voltage must be connected).
Data ValidityAs shown in fig. 7, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop ConditionsAs shown in fig.8 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte FormatEvery byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
AcknowledgeThe master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 9). The peripheral (audio processor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audio processor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without AcknowledgeAvoiding to detect the acknowledge of the audio
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 7: Data Validity on the I2 CBUS
Figure 8: Timing Diagram of I2 CBUS
Figure 9: Acknowledge on the I2 CBUS
TDA7440D7/16
SOFTWARE SPECIFICATIONInterface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte, containing the TDA7440D
address
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU420
SUBADDRESS DATA 1 to DATA n
EXAMPLES
No Incremental BusThe TDA7440D receives a start condition, the
correct chip address, a subaddress with the B = 0
(no incremental bus), N-data (all these data con-
cern the subaddress selected), a stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU421
SUBADDRESS DATA
Incremental BusThe TDA7440D receive a start conditions, the
correct chip address, a subaddress with the B = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
SUBADDRESS from "XXX1000" to "XXX1111" of
DATA are ignored.
The DATA 1 concern the subaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU422
SUBADDRESS DATA 1 to DATA n
TDA7440D8/16
