TDA7438D013TR Fast Delivery |IC PHOENIX CO.,LIMITED

TDA7438D013TR ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORFEATURESFigure 1. Package■ INPUT MULTIPLEXER– 3 STEREO INPUTS– SELECTABLE INPUT GAIN FOR OPTIMALSO2 ..
TDA7439 ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORTDA7439®THREE BANDSDIGITALLY CONTROLLED AUDIO PROCESSORINPUT MULTIPLEXER- 4 STEREO INPUTS- SELECTAB ..
TDA7439B ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORapplications in car-radio and Hi-Fi systems.Thanks to the used BIPOLAR/CMOS Technology,Low Distorti ..
TDA7439D ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORELECTRICAL CHARACTERISTICS (refer to the test circuit T = 25°C, V = 9V, R = 10KΩ,amb S LRG = 600Ω, ..
TDA7439DS ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORELECTRICAL CHARACTERISTICS (refer to the test circuit T = 25°C, V = 9V, R = 10KΩ,amb S LRG = 600Ω, ..
TDA7439DS13TR ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORBlock DiagramMUXOUTL TREBLE(L) MIN(L) MOUT(L) BIN(L) BOUT(L)4 8 181716 1415L-IN1100KR RM B5L-IN2100 ..
THS0842 ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownblock diagramAVDDDRV DVDD DDCOUTCLK Timing CircuitryCOUTI +Sample& HoldI –DA(7–0)3-State8 BITBUSMUX ..
THS0842IPFB ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownTHS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTERWITH SINGLE OR DUAL PARALLE ..
THS10064 ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerFEATURES DESCRIPTION* High-Speed 6 MSPS ADCThe THS10064 is a CMOS, low-power, 10-bit, 6 MSPS* 4 Ana ..
THS10064CDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTHS10064DGND to D ..
THS10064CDAR ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerELECTRICAL CHARACTERISTICS over recommended operating conditions, AV = 5 V, DV = BV = 3.3 V, f = ..
THS10064IDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low Powermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..

TDA7438D013TR
THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR
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TDA7438
June 2004 FEATURES INPUT MULTIPLEXER 3 STEREO INPUTS SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE, MIDDLE AND BASS CONTROL IN
2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY -INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS DESCRIPTION
The TDA7438 is a volume tone (bass, middle and
treble) balance (Left/Right) processor for quality
audio applications in car-radio and Hi-Fi systems.
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
THREE BANDS
DIGITALLY CONTROLLED AUDIO PROCESSOR
Figure 2. Block Diagram
REV. 7
TDA7438
Table 2. Absolute Maximum Ratings
Figure 3. Pin Connection
Table 3. Thermal Data
Table 4. Quick Reference Data
(*) Even applied to Speaker Attenuator Left, Speaker Attenuator Right, Volume Control stand alone or to the combination, if any.
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TDA7438
Table 5. Electrical Characteristcs: (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ,
RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified)
TDA7438
Table 5 (continued)
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TDA7438
Figure 4. Test Circuit APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first
one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free
from any noisy acoustical effect. The TDA7438 audioprocessor provides 3 bands tones control.
3.1 Bass, Middle Stages
The Bass and the middle cells have the same structure.
The Bass cell has an internal resistor Ri = 44KΩ typical.
The Middle cell has an internal resistor Ri = 25KΩ typical.
Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT
pins.
Figure 5.
TDA7438
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
3.2 Treble Stage
The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and
an external capacitor connected between treble pins and ground Typical responses are reported in Figg.
14 to 17.
3.3 CREF
The suggested 10mF reference capacitor (CREF) value can be reduced to 4.7mF if the application re-
quires faster power ON.
Figure 6. THD vs. frequency Figure 7. THD vs. RLOAD
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TDA7438
Figure 8. Channel separation vs. frequency
Figure 9. Bass response
Figure 10. Treble response
Figure 11. Middle response
Figure 12. Typical tone response
TDA7438 2 C BUS INTERFACE
Data transmission from microprocessor to the TDA7438 and vice versa takes place through the 2 wires
I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 12, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig.13 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
14). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the mP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 13. Data Validity on the I2 CBUS
Figure 14. Timing Diagram of I2 CBUS
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TDA7438
Figure 15. Acknowledge on the I2 CBUS SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7438 address A subaddress bytes A sequence of data (N byte + acknowledge)
Figure 16.
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
5.1 EXAMPLES
5.1.1 No Incremental Bus
The TDA7438 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incre-
mental bus), N-data (all these data concern the subaddress selected), a stop condition.
Figure 17.
5.1.2 Incremental Bus
The TDA7438 receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremen-
tal bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"XXX1000" to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA
2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition
TDA7438
Figure 18. .
Table 6. POWER ON RESET CONDITION DATA BYTES
Address = 88 HEX (ADDR:OPEN).
Table 7. FUNCTION SELECTION: First byte (subaddress)
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON’T CARE
Figure 19. INPUT SELECTION

Partno	Mfg	Dc	Qty	Available	Descript
TDA7438D013TR	STMicroelectronics	N/a	12000	avai	THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR