TDA7437T Fast Delivery |IC PHOENIX CO.,LIMITED

TDA7437T ,DIGITALLY CONTROLLED AUDIO PROCESSORfeatures like BALANCE AND FADER FACILITIESsoftmute, and zero-crossing mute are imple-PAUSE DETECTO ..
TDA7438 ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORELECTRICAL CHARACTERISTICS Ω (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10K ,ΩRG = 600 , ..
TDA7438D ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORTDA7438®THREE BANDSDIGITALLY CONTROLLED AUDIO PROCESSORINPUT MULTIPLEXER- 3 STEREO INPUTS- SELECTAB ..
TDA7438D013TR ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORFEATURESFigure 1. Package■ INPUT MULTIPLEXER– 3 STEREO INPUTS– SELECTABLE INPUT GAIN FOR OPTIMALSO2 ..
TDA7439 ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORTDA7439®THREE BANDSDIGITALLY CONTROLLED AUDIO PROCESSORINPUT MULTIPLEXER- 4 STEREO INPUTS- SELECTAB ..
TDA7439B ,THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSORapplications in car-radio and Hi-Fi systems.Thanks to the used BIPOLAR/CMOS Technology,Low Distorti ..
THS0842 ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownblock diagramAVDDDRV DVDD DDCOUTCLK Timing CircuitryCOUTI +Sample& HoldI –DA(7–0)3-State8 BITBUSMUX ..
THS0842IPFB ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownTHS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTERWITH SINGLE OR DUAL PARALLE ..
THS10064 ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerFEATURES DESCRIPTION* High-Speed 6 MSPS ADCThe THS10064 is a CMOS, low-power, 10-bit, 6 MSPS* 4 Ana ..
THS10064CDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTHS10064DGND to D ..
THS10064CDAR ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerELECTRICAL CHARACTERISTICS over recommended operating conditions, AV = 5 V, DV = BV = 3.3 V, f = ..
THS10064IDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low Powermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..

TDA7437T
DIGITALLY CONTROLLED AUDIO PROCESSOR
TDA7437
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- FOUR STEREO, ONE MONO INPUT, AND
ONE DIFFERENTIAL INPUT
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
FULLY PROGRAMMABLE LOUDNESS
FUNCTION
VOLUME CONTROL IN 1dB STEPS INCLUD-
ING GAIN UP TO 16dB
ZERO CROSSING MUTE, SOFT MUTE AND
DIRECT MUTE
BASS AND TREBLE CONTROL
FOUR SPEAKER ATTENUATORS
- FOUR INDEPENDENT SPEAKERS
CONTROL IN 1dB STEPS FOR
BALANCE AND FADER FACILITIES
PAUSE DETECTOR PROGRAMMABLE
THRESHOLD
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
DESCRIPTION
The audioprocessor TDA7437 is an upgrade of
the TDA731X audioprocessor family.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained. Several new features like
softmute, and zero-crossing mute are imple-
mented.
The soft Mute function can be activated in two
ways:
1 Via serial bus (Mute byte, bit D0)
2 Directly on pin 28 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
PIN CONNECTION
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
QUICK REFERENCE DATA
TDA7437
2/23
BLOCK DIAGRAM
TDA7437
ELECTRICAL CHARACTERISTICS (AVDD, DVDD = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C;
all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
TDA7437
4/23
ELECTRICAL CHARACTERISTICS (continued)
TDA7437
ELECTRICAL CHARACTERISTICS (continued)
Note 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold
Note 2: Internall pullup resistor to Vs/2; "LOW" = softmute active
Note: The ANGND and DIGGND layout wires must be kept separated. A 50Ω resistor is recommended to be put as far as possible
from the device.
The CLD - and CDR - can be shortcircuited in applications providing 3 wires CD signal
CLD - = DIFFINLGND
CDR - = DIFFINRGND
TDA7437
6/23
Figure 4: Timing Diagram of I2 CBUS
Figure 3: Data Validity on the I2 CBUS2 C BUS INTERFACE
Data transmission from microprocessor to the
TDA7437 and viceversa takes place thru the 2
wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception
of each byte, otherwise the SDA line remains at the
HIGH level during the ninth clock pulse time. In this
case the master transmitter can generate the
STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the μP can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 5: Acknowledge on the I2 CBUS
TDA7437
AUTO INCREMENT
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled
SUBADDRESS (receive mode)
TRANSMITTED DATA
Send Mode
P = Pause (Active low)
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chipaddress.
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte,(the LSB bit determines
read (=1)/write (=0) transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
CHIP ADDRESS SUBADDRESS DATA 1 to DATA n
MSB LSB MSB LSB MSB LSB
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
MAX CLOCK SPEED 500kbits/s
ADDRpin open A = 0
ADDRpin close to Vs A = 1
TDA7437
8/23
DATA BYTE SPECIFICATION
(*) Selected when using a 3 wires differential source (pins 5 and 13 shorted)
(**) Selected when using 4 wires differential source
(1) OUTR-INR (OUTL-INR) short circuited internally (no need external connection)
Input Selector
Loudness
TDA7437
Mute
Volume
TDA7437
10/23
Speaker
TDA7437
Bass Treble
TDA7437
12/23

Partno	Mfg	Dc	Qty	Available	Descript
TDA7437T		N/a	2	avai	DIGITALLY CONTROLLED AUDIO PROCESSOR