TDA7429S ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIXapplications in TV and Hi-Fi systems. obtained.PIN CONNECTION (TQFP44)44 43 42 41 40 39 38 37 36 35 ..
TDA7429T ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIXBLOCK DIAGRAM (TDA7429T)4/202.7K 5.6K5.6nF 18nF 22nF 100nF 100nF5.6nF 680nF 100nF 4.7nF 22nF 22nF2. ..
TDA7430 ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLERTDA7430TDA7431®DIGITALLY CONTROLLED AUDIO PROCESSOR WITHSURROUND SOUND MATRIX AND VOICE CANCELLER1 ..
TDA7430 ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLERBLOCK DIAGRAM (TDA7431)mmmmm m3/212.7K 5.6K5.6nF 18nF 22nF 100nF 100nF NB15.6nF 680nF 100nF 4.7nF 2 ..
TDA7430TR ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLERAbsolute Maximum RatingsSymbol Parameter Value UnitV Operating Supply Voltage 11 VST Operating Ambi ..
TDA7431 ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLERBLOCK DIAGRAM (TDA7430)2/212.7K 5.6K5.6nF 18nF 22nF 100nF 100nF5.6nF 680nF 100nF 4.7nF 22nF 22nF2.2 ..
THS0842 ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownblock diagramAVDDDRV DVDD DDCOUTCLK Timing CircuitryCOUTI +Sample& HoldI –DA(7–0)3-State8 BITBUSMUX ..
THS0842IPFB ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownTHS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTERWITH SINGLE OR DUAL PARALLE ..
THS10064 ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerFEATURES DESCRIPTION* High-Speed 6 MSPS ADCThe THS10064 is a CMOS, low-power, 10-bit, 6 MSPS* 4 Ana ..
THS10064CDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTHS10064DGND to D ..
THS10064CDAR ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerELECTRICAL CHARACTERISTICS over recommended operating conditions, AV = 5 V, DV = BV = 3.3 V, f = ..
THS10064IDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low Powermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
TDA7429S-TDA7429T
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX
TDA7429S
TDA7429TDIGITALLY CONTROLLED AUDIO PROCESSOR
WITH SURROUND SOUND MATRIX
3 STEREO/4 STEREO INPUTS
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
TREBLE MIDDLE AND BASS CONTROL
THREE SURROUND MODES ARE AVAIL-
ABLE:
- MUSIC: 4 SELECTABLE RESPONSES
- MOVIE AND SIMULATED:
256 SELECTABLE RESPONSES
FOUR SPEAKERS ATTENUATORS:
- 4 INDEPENDENT SPEAKERS CONTROL
IN 1dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
DESCRIPTIONThe TDA7429 is volume tone (bass middle and
treble) balance (Left/Right) processors for quality
audio applications in TV and Hi-Fi systems.
It reproduces surround sound by using program-
mable phase shifters and a signal matrix. Control
of all the functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
PIN CONNECTION (TQFP44)
PIN CONNECTION (SDIP42)
TEST CIRCUIT (TDA7429S)
TDA7429S - TDA7429T2/20
QUICK REFERENCE DATA
TEST CIRCUIT (TDA7429T)
TDA7429S - TDA7429T3/20
BLOCK DIAGRAM (TDA7429T)
TDA7429S - TDA7429T4/20
BLOCK DIAGRAM (TDA7429S)
TDA7429S - TDA7429T5/20
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz
unless otherwise specified)
SUPPLY
THERMAL DATA
ABSOLUTE MAXIMUM RATINGS
TDA7429S - TDA7429T6/20
ELECTRICAL CHARACTERISTICS (continued)SURROUND SOUND MATRIX
TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1
TDA7429S - TDA7429T7/20
ELECTRICAL CHARACTERISTICS (continued)
TDA7429S - TDA7429T8/20
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7429 and viceversa takes place through the
2 wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 3: Data Validity on the I2 CBUS
Figure 4: Timing Diagram of I2 CBUS
Figure 5: Acknowledge on the I2 CBUS
TDA7429S - TDA7429T9/20
SOFTWARE SPECIFICATIONaddress
A subaddress bytes
ACK = Achnowledge
S = Start
P = Stop
A = Address
B = Auto Increment
EXAMPLES
No Incremental BusThe TDA7429 receives a start condition, the cor-
rect chip address, a subaddress with the MSB = 0
(no incremental bus), N-datas (all these datas
concern the subaddress selected), a stop condi-
tion.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU306
SUBADDRESS DATA
Incremental BusThe TDA7429 receive s a start condition, the cor-
rect chip address, a subaddress with the MSB = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
SUBADDRESS from "1XXX1010" to "1XXX1111"
of DATA are ignored.
The DATA 1 concern thesubaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU307
SUBADDRESS DATA 1 to DATA n
TDA7429S - TDA7429T10/20
