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TDA7429T ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIXBLOCK DIAGRAM (TDA7429T)4/202.7K 5.6K5.6nF 18nF 22nF 100nF 100nF5.6nF 680nF 100nF 4.7nF 22nF 22nF2. ..
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TDA7429L
3 BAND EQUALIZER AUDIO PROCESSOR WITH SUBWOOFER CONTROL
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TDA7429LAugust 2000 3 STEREO INPUTS AUXILIARY MONO INPUT INPUT ATTENUATION CONTROL IN 0.5dB
STEP TREBLE MIDDLE AND BASS CONTROL FOUR SPEAKERS ATTENUATORS:
- 4 INDEPENDENT SPEAKERS CONTROL IN
1dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION SUBWOOFER OUTPUT (L+R) CONTROLLED
IN 1dB STEP INPUTS ALL FUNCTIONS PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTIONThe TDA7429L is volume tone (bass middle and tre-
ble) balance (Left/Right) processors for quality audio
applications in TV and Hi-Fi systems, providing also
an additional subwoofer control.
The AC signal setting is obtained by resistor networks
and switches combined with operational amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are ob-
tained.
3 BAND EQUALIZER AUDIO PROCESSOR
WITH SUBWOOFER CONTROL
Figure 1. Test Circuit
TDA7429L 2/16
Figure 2. Pin Connection
Table 1. Quick Reference Data
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TDA7429L
Figure 3. Block Diagram.
TDA7429L 4/16
Table 2. Thermal Data
Table 3. Absolute Maximum Ratings
Table 4. Electrical Characteristics(refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,Vin = 1Vrms; RG = 600Ω, all controls flat
(G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified).
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TDA7429L
Table 4. Electrical Characteristics(refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,Vin = 1Vrms; RG = 600Ω, all controls flat
(G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified).
TDA7429L 6/16
1.0I2 C BUS INTERFACEData transmission from microprocessor to the TDA7429L and viceversa takes place through the 2 wires I2C
BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be
connected).
1.1 Data ValidityAs shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
1.2 Start and Stop ConditionsAs shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
1.3 Byte FormatEvery byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
1.4 AcknowledgeThe master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5).
The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock
pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
1.5 Transmission without AcknowledgeAvoiding to detect the acknowledge of the audioprocessor, the μP can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 4. Data validity on the I2 C bus
Figure 5. Timing Diagram of I2 C bus
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TDA7429L
Figure 6. Acknowledge on the I2 C bus
2.0 SOFTWARE SPECIFICATION
2.1 Interface ProtocolThe interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7429L address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P)
3.0 EXAMPLES
3.1 No Incremental BusThe TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incre-
mental bus), N-datas (all these datas concern the subaddress selected), a stop condition.
3.2 Incremental BusThe TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental
bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2
concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment
TDA7429L 8/16
Table 5. Function SelectionThe first byte (subaddress)
<1> B = 1 incremental bus; active
B = 0 no incremental bus;
<2> X = indifferent 0,1
Table 6. Input Attenuation Selection
