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TDA7427AD-TDA7427AD1
AM-FM RADIO FREQUENCY SINTHESIZER AND IF COUNTER
TDA7427AAM-FM RADIO FREQUENCY SYNTHESIZER
AND IF COUNTER
ON-CHIP REFERENCE OSCILLATOR AND
PROGRAMMABLE IF COUNTER
VHF INPUT AND PRECOUNTER FOR FRE-
QUENCIES UP TO 290MHz (SUITABLE FOR
DAB APPLICATION)
HF INPUT FOR FREQUENCIES UP TO
64MHz (SHORT WAVE BAND)
IN-LOCK DETECTOR FOR SEARCH/STOP
STATION FUNCTION
STAND-BY MODE FOR LOW POWER CON-
SUMPTION
HIGH CURRENT SOURCE FOR 0.5ms
LOCK-IN TIME
DIGITAL PORT EXTENSION WITH SIX OUT-
PUTS FOR FLEXIBILITY IN APPLICATION
FULLY PROGRAMMABLE BY I2 C BUS
DESCRIPTIONThe TDA7427A is a PLL frequency synthesizer
with an additional IF counting system that per-
forms all the functions needed in a complete PLL
radio tuning system for conventional and high
speed RDS tuners. The device has dedicated out-
puts for IN-LOCK detection and Search/Stop sta-
tion.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
TDA7427A2/21
PIN DESCRIPTION* Pin function is selectable by software (see software specification)
TDA7427A3/21
ELECTRICAL CHARACTERISTICS (Tamb = 25°C; VDD1 = 5V; VDD2 = 10V; fOSC = 4MHz; unless other-wise specified).
TDA7427A4/21
ELECTRICAL CHARACTERISTICS (continued)1) PD = Phase Detector
(*) LP_FM and LP_HC pins only
TDA7427A5/21
GENERAL DESCRIPTIONThis circuit contains a frequency synthesiser and
a loop filter for use in FM/AM radio tuning sys-
tems. Only a VCO is required to build a complete
PLL system. For auto search/stop operation an IF
counter system is available.
For FM and SW AM application, the counter
works in a two-stage configuration. The first stage
is a swallow counter with a two modulus (:32/33)
precounter. The second stage is an 11-bit pro-
grammable counter.
For LW and MW application, a 16-bit programma-
ble counter is available.
The circuit receives the scaling factors for the pro-
grammable counters and the values of the refer-
ence frequencies via a I2 C bus interface.
The reference frequency is generated by an inter-
nal XTAL oscillator followed by the reference di-
vider. The device can operate with XTAL oscilla-
tor between 4 and 13MHz either in master mode
and in slave mode.
The reference and step frequencies are free se-
lectable. (XTAL frequency divided by an integer
value). The outputs signals of the phase detector
are switching the programmable current sources.
The loop filter integrates their currents to a DC
voltage.
Values of the current sources are programmable
by 6 bits also received via the I2 C bus.
To minimize the noise induced by the digital part
of the system, a separate power supply supplies
the internal loop filter amplifier. The loop gain can
be set for different conditions by setting the cur-
rent values of the charge/pump generator.
IF COUNTER SYSTEMTwo separate inputs are available for AM and FM
IF signals. The level of integration is adjustable
by six different measuring cycle times.
The tolerance of the accepted count value is ad-
justable, to reach an optimum compromise for
search speed and precision of the evaluation.
For the FM range the center frequency of the
measured count value is adjustable in 32 steps,
to get the possibility of fitting the IF filter toler-
ance. In the AM range an IF frequency of 448 to
479KHz ( 10.684 to 10.715MHz for AM up-con-
version) with 1KHz steps is available.
PLL FREQUENCY SYNTHESIZER
Input AmplifiersThe signals applied on AM and FM inputs are am-
plified to get a logic level in order to drive the fre-
quency dividers.
The typical input impedance for FM and AM in-
puts is 4kΩ.
Table 1. Address Organization
TDA7427A6/21
Table 2. Control Register Functions.
Figure 1. FM and AM (SW) operation (swallow mode)
TDA7427A7/21
DIVIDER FROM VCO FREQUENCY TO
REFERENCE FREQUENCYThis divider provides a low frequency fSYN which
phase is compared with the reference frequency
fREF. It is controlled by the registers PC0 to PC4
and PC5 to PC15
OPERATING MODESFour operating modes are available fo PLL; they
are user programmable with the Mode PM regis-
ters (see table below).
- Standby mode: in this mode all device func-tions are stopped. This allows low current
consumption without loss of information in all
registers. The pin LP-OUT is forced to 0V,
and all data registers are set to EFH. The os-
cillator keeps running.
- FM and AM (SW) Swallow Mode (SW):in this mode the FM or AM signal is applied to
a 32/33 prescaler, which is controlled by a 5
bit divider ’A’.The 5 bit register (PC0 to PC4)
controls this divider. In parallel the output of
the prescaler is connected to a 11 bit divider
’B’. (PC5 to PC15).
fOSC = (R+1)⋅ fREF
Dividing range calculation :
fVCO = [ 33 ⋅ A + (B + 1 - A) ⋅ 32 ] ⋅ fREF
fVCO = (32 ⋅ B + A + 32) ⋅ fREF
Important: for correct operation A ≤ 32, B ≥ A, with
A and B variable values of the dividers).
- AM direct mode: the AM signal is applied di-rectly to the 16 bit static divider ’C’. (PC0 to
PC15)
fOSC = (R + 1) ⋅ f REF
Dividing range:
fVCO = (C + 1) ⋅ fREF
THREE STATE PHASE COMPARATORThe phase comparator generates a phase error
signal according to phase difference between
fSYN and fREF. This phase error signal drives the
charge pump current generator (fig. 3)
CHARGE PUMP CURRENT GENERATORThis stage generates signed pulses of current.
The phase error signal decides the duration and
polarity of those pulses.
The current absolute values are programmable by
A0, A1, A2 registers for high current and B0, B1,
registers for low current.
LOW NOISE CMOS OP-AMPAn internal voltage divider at pin VREF connects
the positive input of the low noise Op-Amp. The
charge pump output connects the negative input.
This internal amplifier in cooperation with external
components can provide an active filter.
Figure 2. AM direct mode operation for SW, MW and LW
TDA7427A8/21
Figure 4. IF Counter internal block diagram
Figure 3. Phase comparator waveforms
TDA7427A9/21
The negative input is switchable to three input
pins ( LPIN 1, LPIN 2 and LPIN 3) to increase the
flexibility in application. This feature allows two
separate active filters for different applications
A logical "1" in the LPIN 1/2 register activates
pin LPIN 1, otherwise pin LPIN 2 is active. While
the high current mode is activated LPIN 3 is
switched on.
INLOCK DETECTORThe charge pump can be switched in low current
mode either via software or automatically by the
inlock detector by setting bit LDENA to "1".
The charge pump is forced in low current mode
when a phase difference of 10-40 μsec is
reached.
A phase difference larger then the programmed
values will switch the charge pump immediately in
the high current mode.
Programmable delays are available for inlock de-
tection.
IF COUNTER SYSTEM (AM/FM/AM - UPC MODES)The if counter works in modes controlled by IFCM
register (see table):
Typical input impedance for IF inputs is 4KΩ.
A sample timer to generate the gate signal for the
main counter is build with a 14-bit programmable
counter to have the possibility to use any crystal
oscillator frequency. In FM mode 6.25KHz in AM
mode a 1KHz signal is generated. This is followed
by an asynchronous divider to generate different
sampling times (see fig. 4).
Intermediate Frequency Main CounterThis counter is a 11/21 bits synchronous autore-
load down-counter. Four bits are programmable
to have the possibility for an adjust to the fre-
quency of the CF filter. The counter length is
automatically adjusted to the chosen sampling
time and the counter mode (AM, FM, AM-UPC).
At the start the counter will be loaded with a de-
fined value which is an equivalent to the divider
value (tsample ⋅ fIF).
If a correct frequency is applied to the IF counter
frequency inputs IF-AM IF-FM, at the end of the
sampling time the main counter is changing its
state from 0 H to 1FFFFFH.
This is detected by a control logic. The frequency
range inside which a successful count results is
detected is adjustable by bits EW 0,1,2.
Adjustment of the Measurement Sequence
TimeThe precision of the measurements is adjustable
by controlling the discrimination window .
This is adjustable by programming the control
registers EW0...EW2.
The measurement time per cycle is adjustable by
setting the Register IFS0 - IFS2.
Adjust of the Frequency ValueThe center frequency of the discrimination win-
dow is adjustable by the control register "CF0" to
"CF4". (see data byte specification).
Port Extension and additional functionsFive digital open collector outputs and one digital
push-pull output are available in application
mode. This digital ports are controlled by the data
bits DOUT1-DOUT6.
Figure 5. I2 C Bus timing diagram
TDA7427A10/21
2 C BUS INTERFACE DESCRIPTIONThe TDA7427A supports the I2C bus protocol.
This protocol defines any device that sends data
into the bus as a transmitter and the receiving de-
vice as the receiver. The device that controls the
transfer is the master and the device being con-
trolled is the slave. The master always initiates
data transfer and provides the clock to transmit or
receive operations.
Data TransitionData transition on the SDA line must only occur
when the clock SCL is low. SDA transitions while
SCL is high will be interpreted as START or
STOP condition.
Start ConditionA start condition is defined by a HIGH to LOW
transition of the SDA line while SCL is at a stable
HIGH level. This START condition must precede
any command and initiate a data transfer onto the
bus. The TDA7427A continuously monitors the
SDA and SCL lines for a valid START and will not
response to any command if this condition has
not been met.
Stop ConditionA STOP condition is defined by a LOW to HIGH
transition of the SDA while the SCL line is at a stable
HIGH level. This condition terminate the communica-
tion between the devices and forces the bus interface
of the TDA7427A into the initial condition.
AcknowledgeIndicates a successful data transfer. The transmit-
ter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the
SDA line to LOW level to indicate it has receive
the eight bits of data correctly.
Data transferDuring data transfer the TDA7427A samples the
SDA line on the leading edge of the SCL clock.
Therefore, for proper device operation the SDA
line must be stable during the SCL LOW to HIGH
transition.
Device AddressingTo start the communication between two devices,
the bus master must initiate a start instruction se-
quence, followed by an eight bit word correspond-
ing to the address of the device it is addressing.
The most significant 6 bits of the slave address
are the device type identifier.
The TDA7427A frequency synthesizer device
type is fixed as "110001"
The next significant bit is used to address a par-
ticular device of the previous defined type con-
nected to the bus. The state of the hardwired A0
pin defines the state of this address bit. So up to
two devices could be connected on the same bus.
The last bit of the instruction defines the type of
operation to be performed:
- When set to "1", a read operation is selected
- When set to "0", a write operation is selectedThe chip selection is accomplished by setting the
bit of the chip address to the corresponding status
of the A0 input.
All TDA7427A connected to the bus will compare
their own hardwired address with the slave ad-
Figure 6. Application with two loop filters
TDA7427A11/21
