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TDA7348D013TR
DIGITALLY CONTROLLED AUDIO PROCESSOR
TDA7348DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- THREE STEREO AND ONE MONO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
VOLUME CONTROL IN 0.3dB STEPS IN-
CLUDING GAIN UP TO 20dB
ZERO CROSSING MUTE AND DIRECT
MUTE
PAUSE DETECTOR WITH PROGRAMMABLE
THRESHOLD
SOFT MUTE CONTROLLED BY SOFTWARE
OR HARDWARE PIN
BASS AND TREBLE CONTROL
FOUR SPEAKER ATTENUATORS
- FOUR INDEPENDENT SPEAKERS
CONTROL IN 1.25dB STEPS FOR
BALANCE AND FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
DESCRIPTIONThe TDA7348 is an upgrade of the TDA7318
audioprocessor.
Thanks to the used BIPOLAR/CMOS technology,
very low distortion, low noise and DC-stepping
are obtained.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained Several new features like
softmute, zero-crossing mute and pause detector
are implemented.
The Soft Mute function can be activated in two
ways:
1 Via serial bus (bit D0, Mute Byte)
2 Directly on pin 22 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
BLOCK DIAGRAM
TDA73482/14
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
QUICK REFERENCE DATA
PIN CONNECTION
TDA73483/14
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat(G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.)
INPUT SELECTOR
VOLUME CONTROL (1 + 2)
ZERO CROSSING MUTE
SOFT MUTE
TDA73484/14
ELECTRICAL CHARACTERISTICS (continued)
BUS INPUTSNote 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold
Note 2: Internal pullup resistor to Vs/2; "LOW" = softmute active
TDA73485/14
Figure 4: Timing Diagram of I2 CBUS
Figure 3: Data Validity on the I2 CBUS
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7348 and viceversa takes place thru the 2
wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data ValidityAs shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop ConditionsAs shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte FormatEvery byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
AcknowledgeThe master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without AcknowledgeAvoiding to detect the acknowledge of the audio-
processor, the μP can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 5: Acknowledge on the I2 CBUS
TDA73486/14
AUTO INCREMENTIf bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled
SUBADDRESS (receive mode)CHIP ADDRESS SUBADDRESS DATA 1 to DATA n
MSB LSB MSB LSB MSB LSB
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
MAX CLOCK SPEED 500kbits/s
TRANSMITTED DATASend Mode
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chipaddress.
SOFTWARE SPECIFICATION
Interface ProtocolThe interface protocol comprises:
A start condition (s) chip address byte,(the LSB bit determines
read/write transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
TDA73487/14
