TDA7345 ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIXELECTRICAL CHARACTERISTICS Ω(refer to the test circuit Tamb =25°C, VS = 9V, RL = 10K ,ΩR = 600 , al ..
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TDA7345D ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIXELECTRICAL CHARACTERISTICS (refer to the test circuit T = 25°C, V = 9V, R = 10KΩ,amb S LR = 600Ω, ..
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TDA7345
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX
TDA7345DIGITALLY CONTROLLED AUDIO PROCESSOR
WITH SURROUND SOUND MATRIX STEREO INPUT
VOLUME CONTROLIN 1.25dB STEP
TREBLE AND BASS CONTROL
THREE SURROUND MODES ARE AVAIL-
ABLE: MOVIE, MUSIC AND SIMULATED
FOUR SPEAKER ATTENUATORS:4 INDEPENDENT SPEAKERS CONTROL 1.25dBSTEPS FOR BALANCE FACILITY INDEPENDENTMUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
DESCRIPTIONThe TDA7345isa volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applicationsin car radio and Hi-Fi systems. reproduces surround sound by using phase
shifters anda signal matrix. Controlof all the
functionsis accomplishedby serial bus.
The AC signal settingis obtainedby resistor net-
works and switches combined with operational
amplifiers.
Thanksto the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained.
November 1999
HP2
L-in
BASS-LA
BASS-LB
TREBLE-L
REC_OUT_R
REC_OUT_L
Lout
Rout
AGND
SCL
SDA
TREBLE-R
DIG GND
BASS-RB
BASS-RA
R-in
REAR OUT23
D94AU191A
CREF
PS2
PS1
LP1
HP1 REARIN
PS4
PS3
PIN CONNECTION
ORDERING NUMBER: TDA7345D
SO281/18
L-in
RLP1
L-R
SUPPLY
AGND
CREF
VOL
100nF
BASS
5.6K
BASS-LA
BASS-LB
100nF
TREBLE
5.6nF
TREBLE(L)
MUTE
D94AU192A
MUTE
BUS
DECODER
LATCHES
SPKR
ATT
SPKR
ATT
VOL
BASS
TREBLE
100nF
100nF
5.6K
5.6nF
TREBLE(R)
MUTE
SPKR
ATT
MUTE
SPKR
ATT
SCLSDADIG
GND
ROUT REC_
OUT_R
LOUTREC_OUT_L
C5
50K
RHP1
LP1
HP1
HP2
5.6nF
680nF
R-in
50K
PS1
90Hz
100nF
PS1
RPS1 SIM
MOVIE/
MUSIC
MUSIC OFF
PS2
4KHz
PS3
400Hz
PS4
400Hz
PHASE
SHIFTER
100nF
PS2
RPS2
22nF
PS3
RPS3
22nF
PS4
RPS4
MOVIE/SIM
MIXING
AMP
LPF
9KHz
EFFECT
CONTROL
MIXING
AMP
REAR
1.2nF
BASS-RA
BASS-RB
REAR
OUT 161718 14 12
BLOCK DIAGRAM
TDA73452/18
680nF
C16
HP1
HP2
L-in0.47μF
C17
BASS-LA
C20 100nF
C21 100nF
BASS-LB
R2
5.6K
TREBLE-L
5.6nF
C22
LOUT ROUT AGND SCL SDA DIG GND
LP1 PS1 PS2 CREF VS
22nFC4
PS3
1.2nF
R-in 0.47μFC7
BASS-RA
C10100nF
C11 100nF
BASS-RB
R1
5.6K
TREBLE-R
5.6nF
C12
22nFC5
PS4
5.6nFC15 100nFC14 22μFC3 100nFC2100nFC13 10μFC1
2.2μF
REARIN
REAR OUT
TDA7345
D94AU193A 14 15 1716 1827128234
REC OUTR
REC OUTL
TEST CIRCUIT
THERMAL DATA
Symbol Description Value UnitRth j-pins Thermal Resistance Junction-pins Max. 85 °C/W
QUICK REFERENCE DATA
Symbol Parameter Min. Typ. Max. Unit Supply Voltage 7 9 10.5 V
VCL Max. input signal handling 2 Vrms
THD Total Harmonic DistortionV= 1Vrmsf= 1KHz 0.02 0.1 %
S/N Signalto Noise RatioVout= 1Vrms (made= OFF) 106 dB Channel Separationf= 1KHz 70 dB
Volume Control 1.25dBstep -78.75 0 dB
Treble Control (2db step) -14 +14 dB
Bass Control (2db step) -14 +14 dB
Balance Control 1.25dB step REC-OUTL&R -38.75 0 dB
Balance Control 1.25dB step (LOUT, ROUT) -78.75 0 dB
Mute Attenuation 90 dB
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit Operating Supply Voltage 11 V
Tamb Operating Ambient Temperature -10to85 °C
Tstg Storage Temperature Range -55to +150 °C
TDA73453/18
ELECTRICAL CHARACTERISTICS (referto the test circuit Tamb =25°C,VS= 9V,RL= 10KΩ,= 600Ω, all controls flat(G= 0),Effect Ctrl= -6dB, MODE= OFF;f= 1KHz
unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. UnitSUPPLY Supply Voltage 7 9 10.5 V Supply Current 20 25 35 mA
SVR Ripple Rejection LCH /RCHout, Mode= OFF 60 80 dB
INPUT STAGE
RII Input Resistance 35 50 65 KΩ
VCL Clipping Level THD= 0.3%;Linor Rin 2 2.5 Vrms
THD= 0.3%; Rin+Lin(2) 3.0 Vrms
CRANGE Control Range 19.68 dB
AVMIN Min. Attenuation -1 0 1 dB
AVMAX Max. Attenuation 18.68 19.68 20.68 dB
ASTEP Step Resolution 0.11 0.31 0.51 dB
VDC DC Steps adjacentatt. step -3 0 3 mV
VOLUME CONTROL
CRANGE Control Range 70 75 dB
AVMIN Min. Attenuation -1 0 1 dB
AVMAX Max. Attenuation 70 75 dB
ASTEP Step Resolution Av=0to -40dB 0.5 1.25 1.75 dB Attenuation Set Error Av=0to -20dB= -20to -60dB
-1.5 1.5 Tracking Error 2dB
VDC DC Steps adjacent attenuation steps -3 0 3 mV
BASS CONTROL (1) Control Range Max. Boost/cut +11.5 +14.0 +16.0 dB
BSTEP Step Resolution 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ
TREBLE CONTROL (1) Control Range Max. Boost/cut +13 +14 +15 dB
TSTEP Step Resolution 1 2 3 dB
EFFECT CONTROL
CRANGE Control Range -21 -6 dB
SSTEP Step Resolution 0.5 1 1.5 dB
TDA73454/18
ELECTRICAL CHARACTERISTICS (continued)
SURROUND SOUND MATRIX
Symbol Parameter Test Condition Min. Typ. Max. UnitGOFF In-phase Gain (OFF) Mode OFF, Input signalof
1kHz, 1.4 Vp-p,Rin→ Rout
Lin→ Lout
-1.5 0 1.5 dB
DGOFF LR In-phase Gain Difference
(OFF)
Mode OFF, Input signalof
1kHz, 1.4 Vp-p
(Rin→ Rout),(Lin→ Lout)
-1.5 0 1.5 dB
GMOV1 In-phase Gain (Movie1) Moviemode, Effect Ctrl= -6dB
Input signalof 1kHz, 1.4 Vp-p
Rin→ Rout,Lin→ Lout
7dB
GMOV2 In-phase Gain (Movie2) Moviemode, Effect Ctrl= -6dB
Input signalof 1kHz, 1.4 Vp-p
Rin→ Rout,Lin→ Lout
8dB
DGMOV LR In-phase Gain Diffrence
(Movie)
Moviemode, Effect Ctrl= -6dB
Input signalof 1kHz, 1.4 Vp-p
(Rin→ Rout)–(Lin→ Lout)
0dB
GMUS1 In-phase Gain (Music1) Music mode, Effect Ctrl= -6dB
Input signalof 1kHz, 1.4 Vp-p
(Rin→ Rout)–(Lin→ Lout)
6dB
GMUS2 In-phase Gain (Music2) Music mode, Effect Ctrl= -6dB
Input signalof 1kHz, 1.4 Vp-p
Rin→ Rout,Lin→ Lout
7.5 dB
DGMUS LR In-phase Gain Difference
(Music)
Music mode, Effect Ctrl= -6dB
Input signalof 1kHz, 1.4 Vp-p
(Rin→ Rout)–(Lin→ Lout)
0dB
LMON1 SimulatedL Output1 Simulated Mode, EffectCtrl= -6dB
Input signalof 250Hz,
1.4 Vp-p,Rin andLin→ Lout
4.5 dB
LMON2 SimulatedL Output2 Simulated Mode, EffectCtrl= -6dB
Input signalof 1kHz,
1.4 Vp-p,Rin andLin→ Lout4.0 dB
LMON3 SimulatedL Output3 Simulated Mode, EffectCtrl=-6dB
Input signalof 3.6kHz,
1.4 Vp-p,Rin andLin→ Lout
7.0 dB
RMON1 SimulatedR Output1 Simulated Mode, EffectCtrl= -6dB
Input signalof 250Hz,
1.4 Vp-p,Rin andLin →Rout4.5 dB
RMON2 SimulatedR Output2 Simulated Mode, EffectCtrl= -6dB
Input signalof 1kHz,
1.4 Vp-p,Rin andLin →Rout
3.8 dB
RMON3 SimulatedR Output3 Simulated Mode, EffectCtrl= -6dB
Input signalof 3.6kHz,
1.4 Vp-p,Rin andLin→ Rout
–20 dB
RLP1 Low Pass Filter Resistance 7.5 10 12.5 KΩ
RPS1 Phase Shifter1 Resistance 13.5 17.95 22.5 kΩ
RPS2 Phase Shifter2 Resistance 0.30 0.40 0.50 KΩ
RPS3 Phase Shifter3 Resistance 13.6 18.08 22.6 KΩ
RPS2 Phase Shifter4 Resistance 13.6 18.08 22.6 KΩ
RHPI High Pass Filter Resistance 45 60 75 KΩ
RLPF LP Pin Impedance 7.5 10 12.5 KΩ
TDA73455/18
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. UnitSPEAKER ATTENUATORS (REC_OUT_L, REC_OUT_R)
Crange Control Range 35 37.5 40 dB
SSTEP Step Resolution 0.5 1.25 1.75 dB Attenuationset error -1.5 1.5 dB
AMUTE Output Mute Attenuation 80 90 dB
VDC DC Steps adjacentatt. steps -3 0 3 mV
SPEAKER ATTENUATORS (LOUT, ROUT)
Crange Control Range 70 75 dB
SSTEP Step Resolution Av=0to -40dB 0.5 1.25 1.75 dB Attenuationset error Av=0to 20dB -1.5 0 1.5 dB= -20to -60dB -3 0 2 dB
VDC DC Steps adjacentatt. steps -3 0 3 mV
AMUTE Output Mute Attenuation 80 90 dB
AUDIO OUTPUTS (LOUT, ROUT, REC_OUT_L, REC_OUT_R)
VOCL Clipping Level d= 0.3% 2 2.5 Vrms
ROUT Output resistance 100 200 300 Ω
VOUT DC Voltage Level 4.2 4.5 4.8 V
GENERAL
NO(OFF) Output Noise (OFF) BW= 20Hzto 20KHz
Output LOUT, ROUT,
Output: REC-OUT-L,
REC-OUT-R
μVrms
μVrms
NO(MOV) Output Noise (Movie) Mode =Movie,= 20Hzto 20KHz
Rout and Lout measurement μVrms
NO(MUS) Output Noise (Music) Mode= Music,= 20Hzto 20KHz,
Rout and Lout measurement μVrms
NO(MON) Output Noise (Simulated) Mode= Simulated,= 20Hzto 20KHz
Rout and Lout measurement μVrms Distorsion Av=0;Vin= 1Vrms 0.02 0.1 % Channel Separation 60 70 dB
BUS INPUTS
VIL Input Low Voltage 1V
VIH Input High Voltage 3 V
IIN Input Current -5 +5 μA Output Voltage SDA
Acknowledge= 1.6mA 0.4 0.8 V
Note:
(1)Bassand Trebleresponse: Thecenter frequencyandthe resonance qualitycanbe choosenby
the external circuitry.A standardfirst order bass responsecanbe realizedbya standard feedbacknetwork.
(2)The peack voltageofthetwo inputsignals mustbe less then VS:
(Lin+ Rin)peak•AVin
TDA7345
6/18
2C BUS INTERFACEData transmission from microprocessorto the
TDA7345 and viceversa takes place through the wiresI2C BUS interface, consistingof the two
lines SDA and SCL (pull-up resistorsto positive
supply voltage mustbe connected).
Data Validity shownin fig.3, the dataon the SDA line must stable during the high periodof the clock. The
HIGH and LOW stateof the data line can only
change when the clock signal on the SCL lineis
LOW.
Start and Stop Conditions shownin fig.4a start conditionisa HIGHto
LOW transitionof the SDA line while SCLis
HIGH. The stop conditionisa LOWto HIGH tran-
sitionof the SDA line while SCLis HIGH.
Byte Format
Every byte transferredon the SDA line must con-
tain8 bits. Each byte mustbe followedby an ac-
knowledge bit. The MSBis transferred first.
Acknowledge
The master (μP) putsa resistive HIGH levelon the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges hasto pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAlineis stable LOW duringthis clock pulse.
The audioprocessor which has been addressed
hasto generatean acknowledge after the recep-
tionof each byte, otherwise the SDA line remains the HIGH level during the ninth clock pulse
time.In this case the master transmitter can gen-
erate the STOP informationin orderto abort the
transfer.
Transmission without Acknowledge
Avoidingto detect the acknowledgeof the audio-
processor, the μP can usea simpler transmission:
simplyit waits one clock without checking the
slave acknowledging, and sends the new data.
This approachof courseis less protected from
misworking and decreases the noise immunity.
Figure3: Data Validityon theI2 CBUS
Figure4: Timing DiagramofI2 CBUS
Figure5: Acknowledgeon theI2 CBUS
TDA7345
7/18
INTERFACE FEATURES Dueto the fact that the MSBis usedto select the byte transmittedisa subaddress (func-
tion)ora data (value), betweena start and
stop condition,is possibleto receive, how
many subaddressesand datasas wanted. The subaddress (function)is fixed untila new
subaddressis transmitted, so the TDA7345
can receive how many dataas wantedfor the
selected subaddress (without the need fora
new start condition)If TDA7345 receivesa subaddress with the
LSB=1 the incremental busis selected,soit
entersina loop condition that means that
every acknowledge will increase automat-
ically the subaddress (function) andit re-
ceives the data relatedto the new subad-
dress.
EXAMPLES NO INCREMENTAL BUS
TDA7345 receivesa start condition, the correct
chip address,a subaddresswith the LSB=0 (no
incremental bus), N-datas (all these datas con-
cern the subaddress selected),a new subad-
dress, N-data,a stop condition.it can receiveina single transmission how
many subaddress are necessary, and for each
subaddresshow many data are necessary. INCREMENTAL BUS
TDA7345 receivesa start condition, the correct
chip addressa subaddress with the LSB=1 (in-
cremental bus): nowitisina loop condition with autoincreaseof the subaddress.
The first data thatit receives doesn’t concern the
subaddress sended but the next one, the second
one concerns the subaddress sended plus twoin
the loop etc, andat the endit receives the stop
condition. the pictures there are some examples:= start
ACK= acknowledge=1 incremental bus,B=0no incremental bus= stop
SOFTWARE SPECIFICATION
InterfaceProtocol
The interface protocol comprises: start condition(s) chip address byte, containing the TDA7345
address (the 8thbitof the byte mustbe 0).
The TDA7345 must always acknowledgeat
the endof each transmitted byte. subaddress (function) bytes (identifiedby the
MSB=0) sequenceof dates and subaddresses (N
bytes+ achnowledge. The dates are identified MSB=1, subaddressesby MSB=0) stop condition (P) 10000010 ACK A2 ACK DATA ACK P
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D94AU195
0A0A1 A3XX0 1
SUBADDRESS DATA1... DATAn one subaddress, withn data concerning that subaddress (no incremental bus)
ACK= Achnowledge= Start= Stop 10000010 ACK DATA ACK DATA ACK S
MSB LSB MSB LSB MSB LSB
Data Transferred (N-bytes+ Acknowledge)
TDA7345 ADDRESS
D94AU194
TDA7345
8/18
MSB LSB SUBADDRESS A1 A2 A3 B
0000 X X X B VOLUME ATTENUATION&
LOUDNESS
0100 X X X B SURROUND& OUT&
EFFECT CONTROL
0010 X X X B BASS
0110 X X X B TREBLE
0001 X X X B REC-OUT-R
0101 X X X B REC-OUT-L
0011 X X X B ROUT
01110 X X B LOUT
01111 X X B INPUT STAGE CONTROL=1 yes incremental bus;=0 no incremental bus;= indifferent 0,1
The first byte select the function,itis identifiedby the MSB=0
DATA BYTES
FUNCTION SELECTION
FIRST BYTE (subaddress) 10000010 ACK A2 ACK DATA ACK P
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D94AU196
0A0A1 A3XX1 1
SUBADDRESS DATA1... DATAn one subaddress, (with incrementalbus), withn data (data1 that concerns subaddress +1, data2
that concerns subaddress+2 etc.) 10000010 ACK A2 ACK DATA
MSB LSB MSB LSB MSB LSB
CHIPADDRESS
D94AU197
0A0A1 A3XX0 1
SUBADDRESS DATA1... DATAn
ACK A2 ACK DATA ACK1
MSB LSB MSB LSB
0A0A1 A3XX0 1
SUBADDRESS DATA1 ...DATAn more subaddress with more data
TDA7345
9/18
