TDA7340G Fast Delivery |IC PHOENIX CO.,LIMITED

TDA7340G ,AUDIO SIGNAL PROCESSORTDA7340G®AUDIO SIGNAL PROCESSORAUDIOPROCESSOR:MUTE, SOFT MUTE AND ZERO CROSSINGMUTEONE DIFFERENTIAL ..
TDA7340G ,AUDIO SIGNAL PROCESSORFEATURES:±7 x 2dB STEPSINTERNAL 2nd ORDER HIGH-PASS FILTER2nd ORDER SYMMETRICAL OR NON SYM-NOISE RE ..
TDA7340G ,AUDIO SIGNAL PROCESSORELECTRICAL CHARACTERISTICS (VS = 9V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz;CREF = 22μF; ..
TDA7340P ,AUDIO SIGNAL PROCESSORTDA7340 AUDIO SIGNAL PROCESSORAUDIOPROCESSOR:MUTE, SOFT MUTE AND ZERO CROSSINGMUTEONE DIFFERENTIAL ..
TDA7342 ,DIGITALLY CONTROLLED AUDIO PROCESSORELECTRICAL CHARACTERISTICS (V = 9V; R = 10KΩ; R = 50Ω; T = 25°C; all gains = 0dB;S L g ambf = 1KHz. ..
TDA7342N ,DIGITALLY CONTROLLED AUDIO PROCESSORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Operating Supply Voltage 10.5 VST Operating Am ..
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TDA7340G
AUDIO SIGNAL PROCESSOR
TDA7340G
AUDIO SIGNAL PROCESSOR
AUDIOPROCESSOR:
MUTE, SOFT MUTE AND ZERO CROSSING
MUTE
ONE DIFFERENTIAL, TWO STEREO AND
TWO MONO INPUTS
DIFFERENTIAL PHONE INPUT
VOLUME, BASS, TREBLE AND LOUDNESS
CONTROL
FOUR SPEAKER ATTENUATORS WITH IN-
DEPENDENT ATTENUATION CONTROL
STEREODECODER:
ROLL-OFF ADJUSTMENT
ADJUSTMENT FREE INTEGRATED 456KHz
VCO
HIGH CUT CONTROL
STEREO BLEND
NOISE BLANKER:
INTEGRATED HIGH-PASS FILTER
NOISE RECTIFIER OUTPUT FOR QUALITY
DETECTION
PROGRAMMABLE TRIGGER THRESHOLD
DEVIATION AND FIELD STRENGTH DE-
PENDENT TRIGGER ADJUSTMENT
PAUSE DETECTOR:
PROGRAMMABLE THRESHOLD
ALL FUNCTIONS PROGRAMMABLE VIA I2 C BUS
DESCRIPTION
The TDA7340G I2 C bus controlled audio signal
processor contains all signal processing blocks of
a high performance car radio, including audio-
processor, stereodecoder, noise blanker, pause
detector and different mute functions.
The use of BICMOS technology allows the imple-
mentation of several filter functions with switched
capacitor techniques like fully integrated, adjust-
ment free PLL Loop filter, pilot detector with inte-
grator and pilot cancellation.
This minimizes the number of external compo-
nents.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained also in the stereodecoder
part. The audioprocessor contains several new
features like softmute, zero-crossing mute and
pause detector.
Very low DC stepping is obtained by use of a
BICMOS technology.
FEATURES:
Input Multiplexer:
DIFFERENTIAL CD STEREO INPUT
CASSETTE STEREO INPUT
FM STEREO INPUT FROM STEREODE-
CODER
AM INPUT:
MONO OR STEREO MODE (PROGRAMMA-
BLE)
BEEP INPUT (ONLY IN AM MONO MODE)
TELEPHONE DIFFERENTIAL MONO INPUT
GAIN PROGRAMMABLE IN 3 x 3.75dB
STEPS
Loudness:
FULLY PROGRAMMABLE
15 x 1.25dB STEPS
Volume Control:
1.25dB COARSE ATTENUATOR
0.31dB FINE ATTENUATORS
MAX GAIN 20dB
MAX ATTENUATION 59.7dB (PLUS LOUD-
NESS)
Bass Control
±7 x 2dB STEPS
2nd ORDER SYMMETRICAL OR NON SYM-
METRICAL CUT FREQUENCY RESPONSE
Treble Control
±7 x 2dB STEPS
Speaker Control
4 INDEPENDENT SPEAKER CONTROL IN
1.25dB STEPS
CONTROL RANGE 37.5dB
INDEPENDENT SPEAKER MUTE
Mute Functions
DIRECT MUTE
ZERO CROSSING MUTE WITH PROGRAM-
MABLE THRESHOLD
SOFT MUTE WITH EXTERNAL DEFINED
SLOPE
SOFT MUTE VIA I2 C BUS OR EXTERNALLY
CONTROLLED
Pause Detector
PROGRAMMABLE THRESHOLD
DELAY TIME DEFINED BY AN EXTERNAL
CAPACITOR
FEATURES:
INTERNALLY ADJUSTABLE ROLL-OFF
COMPENSATION (I2 C BUS CONTROLLED)
INTEGRATED PILOT CANCELLATION
ON CHIP FILTER FOR PILOT DETECTOR
AND PLL
ADJUSTMENT FREE VOLTAGE CONTROL-
LED OSCILLATOR
AUTOMATIC PILOT DEPENDENT
MONO/STEREO SWITCHING
VERY HIGH INTERMODULATION AND IN-
TERFERENCE SUPPRESSION2 C BUS CONTROLLED (STD OFF, FORCED
MONO, STEREO)
HIGH CUT CONTROL
STEREO BLEND
FEATURES:
INTERNAL 2nd ORDER HIGH-PASS FILTER
NOISE RECTIFIER OUTPUT FOR SIGNAL
QUALITY DETECTION
PROGRAMMABLE TRIGGER THRESHOLD
TRIGGER THRESHOLD DEPENDENT ON
HIGH FREQUENCY NOISE
BLANKING TIME PROGRAMMABLE BY EX-
TERNAL CAPACITOR
VERY LOW OFFSET CURRENT DURING
HOLD TIME DUE TO OPAMPS WITH MOS
INPUTS
LEVEL INPUT FOR ADDITIONAL SPIKE DE-
TECTION ON FIELD STRENGTH WITH IN-
TERNAL 1st ORDER + 20KHz HIGH PASS
FILTER
NOISE RECTIFIER OUTPUT FOR QUALITY
DETECTION
CIRCUITS FOR DEVIATION AND FIELD
STRENGTH DEPENDENT TRIGGER AD-
JUSTMENT
TDA7340G
2/27
BLOCK DIAGRAM
TDA7340G
3/27
ELECTRICAL CHARACTERISTICS (VS = 9V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz;
CREF = 22μF; unless otherwise specified, refer to the Test Circuit.)
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
TDA7340G
4/27
ELECTRICAL CHARACTERISTICS (continued.)
(1) WIN represents the MUTE programming bit pair D6,D5 for the zero crossing window threshold
TDA7340G
5/27
ELECTRICAL CHARACTERISTICS (continued.)
(1) WIN represent the MUTE programming bit paIr D6,D5 for the zero crossing window threshold
TDA7340G
6/27
STEREO DECODER PART
ELECTRICAL CHARACTERISTICS (VS = 9V; modulation frequency: 1KHz; de-emphasis time:
T = 50μs; nominal MPX input voltage: VMPX = 0.5VRMS (75KHz deviation); GI = 3.5dB; Tamb = 27°C; un-
less otherwise specified)
TDA7340G
7/27
ELECTRICAL CHARACTERISTICS (continued)
NOTES TO THE CHARACTERISTICS
1) INTERMODULATION SUPPRESSION
α2 = VO (signal) (at1KHz)
VO (spurious) (at1KHZ) ; fs = (2 x 10KHz) - 19KHz
α3 = VO (signal) (at1KHz)
VO (spurious) (at1KHZ) ; fs = (3 x 13KHz) - 38KHz
measured with : 91% mono signal; 9% pilot signal; fm=10KHz or 13KHz
2) TRAFFIC RADIO (V.F.) suppression
α57 (V.W.F.) = VO(signal) (at1KHz)
VO (spurious) (at1KHZ ±23Hz)
measured with : 91% stereo signal; 9% pilot signal; fm=1KHz; 5% subcarrier
(f=57KHz, fm = 23Hz AM, m = 60%)
TDA7340G
8/27
NOTES TO THE CHARACTERISTICS (continued)
3) SCA (SUBSIDIARY COMMUNICATIONS AUTHORIZATION)
α67 = VO(signal) (at1KHz)
VO (spurious) (at9KHZ) ; fs = (2 x 38KHz) - 67KHz
measured with : 81% mono signal; 9% pilot signal; fm=1KHz;
10% SCA - subcarrier (fs = 67KHz, unmodulated)
4) ACI (ADJACENT CHANNEL INTERFERENCE)
α114 = VO (signal) (at1KHz)
VO (spurious) (at4KHZ) ; fs = 110KHz - (3 x 38KHz)
α190 = VO (signal) (at1KHz)
VO (spurious) (at4KHZ) ; fs = 186KHz - (5 x 38KHz)
measured with : 90% mono signal; 9% pilot signal; fm=1KHz; 1% spurious signal
(fs = 110KHz or 186KHz, unmodulated)
5) Control range typ 11% of VR (see figure 2)
6) Control range typ 30% of VR (see figure 1)
7) All thresholds are measured by using a pulse with TR = 2μs, THIGH = 2μs and TF = 10μs.
The repetition rate must not increase the PEAK voltage.
8) NBT represent the STDEC bit pair D6, D5 for the noise blanker trigger threshold
NAT represent the SPKR_LF bit pair D7, D5 for the noise controlled trigger threshold
9) OVD represent the SPKR_LR bit pair D7, D6 for the over deviation detector
10) FSC represent the SPKR_RF bit pair D7, D6 for the field strength control
11) The TDA7340G has a dedicated internal circuitry providing a soft power-on. The I2C bus data
programmation must start after the reference DC level has reached the target Vs/2 value,
otherwise a pop can be generated. The Cref pin and Out pins rise time at power on are riported
in Figg.4, 5, 6 for Cref values of 4.7uF, 10uF, 22uF.
12) The CDL- and CDR- can be shortcircuited in applications providing 3 wires CD signal.
13)The AGND and DGND layout wires must be kept separated. A 50Ω resistor is recommend to be put
as far as possible from the device.
TDA7340G
9/27
Figure 1: High Cut Control
-0.4 -0.3 -0.2 -0.1 VSB-VR(V)
D94AU056
SEP
(dB)
Figure 2: Stereo Blend2 C BUS INTERFACE PROTOCOL
The interface protocol comprises:
A start condition (s)
A chip address byte, (the LSB bit determines
read/write transmission).
A subaddress byte
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
I = Autoincrement
MAX CLOCK SPEED 500kbits/s
Autoincrement
If bit I in the subaddress byte is set to "1", the autoincrement of subaddress is enabled.
Figure 3
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D95AU216
SUBADDRESS DATA 1 ... DATA n
TDA7340G
10/27
T = Testmode I = Autoincrement X = Not Used
SUBADDRESS (RECEIVE MODE)
TRANSMITTED DATA (SEND MODE)
P = Pause (low active)
ZM =Zero Crossing Muted (HIGH = active)
SM = Soft mute activated (HIGH = active)
ST = Stereo (HIGH = active)
X = Not used
The transmitted data is automatically updated af-
ter each 9th clock pulse.
Transmission can be repeated without new chi-
paddress.
DATA BYTE SPECIFICATION
X = not relevant; set to "1"during testing
INPUT SELECTOR
For example to select quasi diff CD input with a gain of 7.5dB the Data Byte is: XXX01000
TDA7340G
11/27
For example to select -17.5dB loudness the Data Byte is: XXX01110
Note (1):
If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency response. D0 to D3 determine the
attenuation level
An additional direct mute function is included in the Speaker Attenuators
(*) BIT D4 = 1disables the zero cross mute and pause detector, otherwise always active
TDA7340G
12/27
SPEAKER ATTENUATORS
For example an attenuation of 25dB on a selected output is given by: 11110100
Note:
If the speaker attenuator bytes the three MSBs are used for additional Noise blanker Roll off programming
STEREO DECODER
For example pilot threshold low, noise blanker threshold 3 (NTB = 10), Stereo decoder ON, 6dB input
gain is given by: 11000010.
TDA7340G
13/27
NOISE BLANKER: SPKR LR
NOISE BLANKER: SPKR RF
NOISE BLANKER: SPKR RR
*) See Noise blanker description
TDA7340G
14/27

Partno	Mfg	Dc	Qty	Available	Descript
TDA7340G	ST	N/a	72	avai	AUDIO SIGNAL PROCESSOR
TDA7340G	ST ?	N/a	59	avai	AUDIO SIGNAL PROCESSOR
TDA7340G	PHI	N/a	30	avai	AUDIO SIGNAL PROCESSOR