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TDA7339
3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
TDA73393 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
PRODUCT PREVIEWTHREE STEREO INPUT
ONE RECORD OUTPUT
ONE STEREO OUTPUT
TWO INDEPENDENT VOLUME CONTROL IN
1.0dB STEPS
TREBLE, MIDDLE AND BASS CONTROL IN
1.0dB STEPS
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
DESCRIPTIONThe TDA7339 is a volume and tone (bass , mid-
dle and treble) processor for quality audio appli-
cation in car radio and Hi-Fi system.
Control is accomplished by serial I2C bus micro-
processor interface.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/MOS Technology,
Low Distortion, Low Noise and Low DC stepping
are obtained.
BLOCK DIAGRAMABSOLUTE MAXIMUM RATINGS
THERMAL DATA
QUICK REFERENCE DATA
PIN CONNECTION
TDA7339
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; f = 1KHz; all control = flat (G = 0); Tamb =
25°C Refer to the test circuit, unless otherwise specified.)
TDA73393/12
ELECTRICAL CHARACTERISTICS (continued)NOTE 1: the device is functionally good at Vs = 5V. A step down, on VS, to 4V does’t reset the device.
TDA7339
Timing Diagram of I2 CBUS
Data Validity on the I2 CBUS2 C BUS INTERFACEData transmission from microprocessor to the
TDA7319 and viceversa takes place thru the 2
wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data ValidityAs shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop ConditionsAs shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte FormatEvery byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
AcknowledgeThe master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without AcknowledgeAvoiding to detect the acknowledge of the audio-
processor, the μP can use a simplier transmis-
sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Acknowledge on the I2 CBUS
TDA73395/12
POWER ON RESET:
1st volume = 2nd volume = Mute
Treble = Middle = Bass = -14dB
Mutmux = Active Input IN 1
FUNCTION CODESTDA7339 ADDRESS
MSB first byte LSB MSB LSB MSB LSB
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATIONChip address
A = Logic level ON pin ADDR
SOFTWARE SPECIFICATION
Interface ProtocolThe interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7339
address (the 8th bit of the byte must be 0). The
TDA7339 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
TDA7339
