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TDA7326-TDA7326D
AM-FM RADIO FREQUENCY SYNTHESIZER
TDA7326AM-FM RADIO FREQUENCY SYNTHESIZER
FM INPUT AND PRECOUNTER FOR UP TO
140MHz
AM INPUT FOR UP TO 40MHz
6-BIT SWALLOW COUNTER, 8-BIT PRO-
GRAMMABLE COUNTER FOR FM AND SW
14-BIT PROGRAMMABLE COUNTER FOR
LW AND MW
THREE WIRES 8-BIT SERIAL INTERFACE
ON-CHIP REFERENCE OSCILLATOR AND
COUNTER
PROGRAMMABLE SCANNING STEPS FOR
AM AND FM
DIGITAL PHASE DETECTOR AND LOOP FIL-
TER
TWO SEPARATE FREE PROGRAMMABLE
FILTER APPLICATIONS AVAILABLE
TUNING VOLTAGE OUTPUT 0.5 TO 9.5V
PROGRAMMABLE CURRENT SOURCES TO
SET THE LOOP GAIN
ON-CHIP POWER ON RESET
STANDBY MODE
DESCRIPTIONThe TDA7326 is a PLL frequency synthesizer in
CMOS technology that performs all the function of
a PLL radio tuning system for FM and AM (LW,
MW, SW)
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION Figure 1:Input Sensitivity
TDA7326
ELECTRICAL CHARACTERISTICS (Tamb = 25°C ; VDD1 = 5V; VDD2 = 9V fOSC = 4MHz; RISET = 68KΩ;unless otherwise specified.)
RF INPUT (AMIN FMIN)
OSCILLATOR
PLL CHARACTERISTICS
LOOP FILTER INPUT (LPIN1, LPIN2 = PIN 15,16)
TDA7326
ELECTRICAL CHARACTERISTICS (continued)
LOOP FILTER OUTPUT (LPOUT = PIN 14)
CHARGE PUMP CURRENT GENERATION (LPIN1, LPIN2 = PIN 15, 16)
DOUT1 OPENDRAIN OUTPUT(PIN 9)
BUS INTERFACE
BUS INTERFACE, WAITING TIME (see fig. 5) The Data is Acquired at the High → Low Clock Transition
BUS INTERFACE, DATA REPETITION TIME (see fig. 5)
BUS INTERFACE, SETUP TIME (see fig. 5)
BUS INTERFACE, HOLD TIME (see fig. 5)
TDA7326
2.0 GENERAL DESCRIPTIONThis circuit contains a frequency synthesizer and
a loop filter for an FM and AM radio tuning sys-
tem. Only a VCO is required to build a complete
PLL system.
For FM and SW application, the counter works in
a two stages configuration.
The first stage is a swallow counter with a four
modulus (:32/33/64/65) precounter.
The second stage is an 8-bit programmable
counter.
For LW and MW application, a 14-bit programma-
ble counter is available.
The circuit receives the scaling factors for the pro-
grammable counters and the values of the refer-
ence frequencies via a three line serial bus inter-
face.
The reference frequency is generated by a 4MHz
XTAL oscillator followed by the reference divider.
An external oscillator (f = 4MHz) can be used in-
stead of the internal one; it must be connected to
OSCIN (pin 7).
The reference step-frequency is 1 or 2.5kHz for
AM. For FM mode a step frequency of 12.5 and
25kHz can be selected.
The circuit checks the format of the received data
words.
Valid data in the interface shift register are stored
automatically in buffer registers at the end of
transmission.
The output signals of the phase detector are
switching the programmable current sources.
Their currents are integrated in the loop filter to a
DC voltage.The values of the current sources are
programmable by two bits also received via the
serial bus.
The loop filter amplifier is supplied by a separate
positive power supply, to minimize the noise in-
duced by the digital part of the system.
The loop gain can be set for different conditions.
After a power on reset, all registers are reset to
zero and the standby mode is activated.
In standby mode, oscillator, reference counter,
AM input and FM input are stopped. The power
consumption is reduced to a minimum.
3.0 DETAILED DESCRIPTION OF THE PLL
FREQUENCY SYNTHESIZER
3.1 INPUT AMPLIFIERSThe signals applied on AM and FM input are am-
plified to get a logic level in order to drive the fre-
quency dividers.
3.1.1 Input ImpedanceThe typical input impedance: for the FM input
is 200Ω and for AM input is 1.4kΩ.
3.1.2 Input sensitivity(see Figures 1a and 1b).
3.2 DATA AND CONTROL REGISTER
3.2.1 Register LocationThe data registers (bit2...bit7) for the control
register and the data registers PC7...PC0,
SC5...SC0 for the counters are organized in
four words, identified by two address bits (bit 7
and bit 6), bit 7 is the first bit to be sent by the
controller, bit0 is the last one. The order and
the number of the bytes to be transmitted is
free of choice. The modification of the
PC7...PC0 registers is valid for the internal
counters only after transmission of byte 4
(SC5...SC0).
3.2.2 CONTROL AND STATUS REGISTERS
Register Configuration
TDA7326
