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TD62C805
48BIT THERMAL HEAD DRIVER
TOSHIBA
TD62C805F
TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TD62C805F
48BIT THERMAL HEAD DRIVER
The TD62805F is a general purpose 48bit driver IC
consisting of 8 block 8bit shift register and 48bit drivers
(Open Drain).
This device is best suited as a 48 dot thermal printer
head drivers.
FEATURES
8bit parallel input and 6 block 8bit shift register
CMOS compatible input.
High driverability ... 30V/100mA/ch
Built in monostable multivibrator for head protection
16 steps gray scale operating with 4bit data
48bit open drain outputs
Package ............ pPFP-80PIN
QFP80-P-1420-0.80C
Weight : 1.53g (Typ.)
961001EBA2
O TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing
TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss
of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the
TOSHIBA Semiconductor Reliability Handbook.
0 The products described in this document are subject to foreign exchange and foreign trade control laws.
o The information contained herein is presented only as a guide for the apflications of our products. No responsibility is assumed by TOSHIBA
the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
o T e information contained herein is subject to change without notice.
CORPORATION for any infringements of intellectual property or other rights 0
1998-05-15 1/12
TOSHIBA
TD62C805F
PIN CONNECTION (TOP VIEW)
0T8 l:
Vssm) E
Vssw) E
oi-s8C
Vss(0) C
os-csc
os-USC
Vssw) l:
rsuoi,IseitoIr,oi,-i,CItoIrsIasIrnIstItoIruI,-
alalal2l2lthlawtlullu/lu)luplu2luJluJlu)
li:iliiil)iiliiliiil(iili:ji, ''j'liili':i'llgliiliiliilii)
f-lf-lf-lf-ll-ll-ll-ll-ll-ll-lf-lf-lf-ll-ll-ll-l
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cl Vss(o)
Ll VSS(O)
Cl 073
Cl Vss(o)
Cl 077
Cl og-u,
Cl os-us
Ll t:V2
Cl Vss(o)
Ll VDD
Cl MMV/E
Ll F.CLK
Cl WRITE-E
s(l;EL-ietsesy?.Ci5,t.TDsLrr,;Est."e
,cjlr,ir,iifti:1trati'-tti-r,'rei-tti-ii:-Htri,i.cjrr',,
ru-'',tig?iit?:t?:t?:'ig',ii:h8yii:t?:tl'ik" $0
-r- r-
1998-05-15 2/12
TOSHIBA TD62C805F
BLOCK DIAGRAM
MO o-Fi-o-FI ot8-ot: OD8--OD1
20-13 11--4 1,80-7
WRITE-CLK
DATA 1
DATA 5
COUNTER-CLK
WRITE-E
46--53 55--62 65--72
MMV/E m~OA8 W~O_BB o-cr-o-o
1998-05-15 3/12
TOSHIBA
TD62C805F
PIN FUNCTION
PIN No. PIN NAME FUNCTION
24 CLK "f " : Data shift
25 WRITE-CLK "H" : enable clock signal, "L" : disable clock signal pull-up input terminal
"L" : all outputs "OFF", reset PWM counter reset PWM counter and MMV
37 RESET circuit
Pull-up input terminal
Input terminals for output data
28--36 DATA1--8 "H" : output "ON", "L" : output "OFF"
And input terminals for PWM data
- "H" : enable output data for shift register
26 OUT/PWM "L" : enable PWM data for counter
38 PWM "L" : output enable (PWM operating)
39 COUNTER.CLOCK Input terminal for clock of PWM counter and for trigger of MMV
40 OUT? "L" : all outputs "ON"
42 E-CLK "1 " : outputs "OFF" when OUT-E is "High". Outputs "ON" when OUT-E
is "Low". Pull-up input terminal
41 WRITE-F "H" : enable E-CLK signal pull-up input terminal
43 MMV/E CR connection terminal for MMV
22 MO ON/OFF monitor terminal of output t5rrg
23, 44 VDD Supply voltage terminal for control logic
- vss (O) GND terminals for driver
PIN No. : 2, 3, 12, 21, 45, 54, 63, 64, 73
27, 32 VSS(L) GND terminals for control logic
1998-05-15 4/12
TOSHIBA TD62C805F
(1) Data Input
Dr-Di, of Input Dates are entered to shift Register by the clock signal with the timing of rise.
Outputs are latched by holding the WRITE-CLK "Low" or to stop the clock signal.
PWM Data (DATA1--4) are latched by OUT/PWM signal "Low".
T1 T2 T3 T4 T5 T6
CLK -f-LFLfVllLfVLlVLVLl'Vl,
DATAI-8 L o1)(o2)(D3)(o4XDs)(o6)(D7)- -----
WRITE-CLK l-- CLK DISABLE, OUTPUT DATA LATCH
OUT/PWM
- PWM DATA LATCH
(2) Output Enable
Outputs become "OFF" at the first rising edge of E-CLK after the OUT.E to "High", and become
"ON" at the first rising edge of E.CLK after the OUT-E to "Low".
Output ON/OFF duty is controlled by controlling OUT-E signal directly or to change the timing
of WRITE-E and E.CLK.
1998-05-15 5/12
TOSHIBA TD62C805F
(3) PWM Control
Outputs ON/OFF duty are controlled by OUT-T? and PWM DATA of DI--D4 PWM control is
performed by comparing the internal 4bit PWM Counter out and PWM DATA of D1--D4.
For example, when PWM DATA is 7, 50% Output Duty is obtained.
(Refer to tables below.)
T1 T3 T1'
COUNTER-DATA: (o)(0(2)(3Xei)(6)(7X8)(9)(AXss)(c)(D)(EXF] (0X0(2)(3)(9(5)(6)(7X8X9XA)(0(c)(D)(E)(Fl
|_Il—I
m L - I
OUTPUT CONTROL BY OUT-E (DUTY 50%) J PWM CONTROL (DUTY 50%)
PWM DATA 0 1 2 3 4 5 6 7 8 9
Duty (%) o 6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25
PWM DATA A B c D E F
Duty (%) 62.50 68.75 75.00 81.25 87.50 100.00
1998-05-15 6/12
TOSHIBA TD62C805F
MMV OPERATION
MMV output of Q becomes "L" when the MMV/E voltage becomes less than Vref(L) after the first
rising edge of INTERNAL CLOCK.
And becomes "H" when the MMV/E voltage above Vref(H) after re-charging of external
capacitance connect to MMV/E. The external capacitance and Resistor connect to MMV/E control
MMV Output "ON" period.
So Output Load is protected from burn-out. It's required enough discharging time of external
capacitance. (Refer to figure below)
couNmrccrLrLrL----hrLrLrLrLrL----JLrLrlfLln
OUTPUT OFF BY MMV -
0 Pulse width of MMV
PULSE-WIDTH - EXTERNAL CAPACITOR
Ta=25°C
1 VDD-- 5V, VOUT= 30V
A COUNTER-CLK=400kHz
E 5 RL=37SQ : Typ.
i-ii?, 1
Ll'?' 0.5
(LE) 0.3
30 100 300 1000 3000 10000
EXTERNAL CAPACITOR (pF) (FILM CONDENSER)
1998-05-15 7/12
TOSHIBA
INPUT CIRCUIT
1. DATA1~8, CLK, COUNTER-CLK, OUT/PWM, OUT-E
TD62C805F
VDD C .
OUT/W gr
DATAI-8
CLK 015.9 T'
COUNTER-CLIS L.
OUT.E 1r
vss C) .
2. TMLK, RESET, WRITE'E WRITE'CLK
VDD C - '
WRITE~E 'ii lr
LtESET o 159 T'
WRITE-CLK L,
vss 0 .
VDD C .
pu-m, o ‘59 r'
Vss O v .
OUTPUT CIRCUIT
1. OA1--8--OFI--8
C ' - -
VDD o oA1--8--OF1-8
D C L, =
VSS(L) C . —0 V55(0)
1998-05-15 8/12
TOSHIBA TD62C805F
MAXIMUM RATINGS (Ta =25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD 7 V
Output Voltage VDS 30 V
Output Current IDS 100 mA/ch
Input Current 'IN i 5 mA
Input Voltage VIN -0.4--VDD+-0.4 V
Power Free Air P 1.0 W
Dissipation On PCB (Note) D 1.3
Operating Temperature Topr -40-85 "C
Storage Temperature Tstg - 55--150 "C
(Note) On Glass Epoxy PCB (100x100x1.6mm, Cu 40%)
RECOMMENDED OPERATING CONDITIONS (Ta-- -40--85oC)
CHARACTERISTIC SYMBOL TEST CONDITION MIN TYP. MAX. UNIT
Output Voltage l/DS - - - 26 V
Supply Voltage VDD - 4.5 - 5.5 V
Duty 50% - - 33.3
Output Current IDS Duty 80% - - 26.4 mA/ch
Duty 100% - - 23.6
Input Voltage VIN - GND - VDD V
Operating Clock Frequency fCLK Duty 50% - - 5 MHz
Clock Pulse Width tw COUNTER-CLK 50 - - ns
D - Ti
ata Set P. Ime tsetup - 20 - - ns
Data Hold Time thold
TOSHIBA TD62C805F
ELECTRICAL CHARACTERISTICS (Ta = 25°C, VDD = 5.5V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
"H" Level VIH - - 3.5 - VDD+0.4
Input Voltage "L" Level VIL - - -0.4 - 1.5 V
WRITE-CLK
E-CLK, RESET IINH - VIN = ov, VDD = 51/ - 34 - 70 - 145
Input Current WRITE-F prA
PWM IINL - VIN = 5v, VDD = SV 34 70 145
O t t Volta e V 0 OF8 IDs---80mA - - 960 mV
u pu g DS - AI-- IDS = 50mA - - 600
Output On Resistor RON - bs = 50mA - - 12.0 n
Output Leak Current log - VDS = 30V - - 10 ,uA
Quiescent Current IDD - - - - 20 prA
. VDD = 5V, fCLK = SMHz
Operating Supply Current IDDWr - Output OPEN - - 5 prA
1998-05-15 10/12
TOSHIBA TD62C805F
SWITCHING CHARACTERISTICS (VDD=5.5V, VDS=26V, Ta=25°C)
CHARACTERISTIC SYMBOL COLEDSITI'ION MIN. TYP. MAX. UNIT
Maximum Operating Clock Frequency fMAX Duty 50% 10 - - MHz
cLK-t5Crtfi, wRmiyCLK-t5Trrif - 80 -
. FSH-W - 100 -
'lro.pagetion COUNTER, CLK-OUTn (Note) - 110 -
Delay Time - - - - tpLH
"L"-"H" f?urEf..l.l.lT...r), WRITE-E-OUTn - 100 -
E-CLK-OUTn Duty 50%
MMV/E-OUTn VIN (H) =4.5v - 130 -
CLK-OUTn, WRITE-CLK-OUTn VIN(L) =ov - 60 -
Propagation RESET-OUTn RL=3750 - 100 -
. COUNTER, CLK-OUTn (Note) CL=15pF - 90 -
Delay Time - - - - tpHL
"H"-"L" l"rre?rtn, WRITE-E-OUTn - 70 - ns
E-CLK-OUTn
MMV/E-m - 80 -
Minimum Clock Pulse Width tw 25 -
DATA-OUT/PWM
Data Set Up Time DATA-CLK tsetup - - 10 -
OUT-E-E-CLK
DATA-OUT/W
Data Hold Time DATA-CLK thold - - IO -
OUT-E-ECLK
. . . COUNTER-CLK
Maximum Rise Time CLK tr - - - 1
. . COUNTER-CLK
Maximum Fall Time CLK tf - - - 1 ,us
Output Rise lime U7tr, tor - - 0.02 1
Output Fall Time tof - - 0.05 0.4
MMV Pulse Width tMMV - - 3 - ms
(Note) COUNTER DATA=F
PRECAUTIONS for USING
Utmost care is necessary in the design of the output line, VCC and GND line since IC may be
destroyed due to short-circuit between outputs, air contamination fault, or fault by improper
grounding.
1998-05-15 11/12
TOSHIBA TD62C805F
OUTLINE DRAWING
QFP80-P-1420-0.80C Unit : mm
24.3i0.3
1 .OTYP
9x tfir!,-','..
l I 0.985i0.2
Weight : 1.53g (Typ.)
1998-05-15 12/12
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