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TC9434AFN
SUMM-DELTA MODULATION DA CONVERTER WITH BUILT-IN 8-TIMES OVERSAMPLING DIGITAL FILTER/DIGITAL BASS BOOST/ANALOG FILTER
TOSHIBA
TC9434AFN
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9434AFN
2-A MODULATION DA CONVERTER WITH BUILT-IN 8-TIMES
OVERSAMPLING DIGITAL FILTER/DIGITAL BASS BOOST/ANALOG
FILTER
The TC9434AFN is second-order E-n modulation system 1-
bit DA converters incorporating an 8-times oversampling
digital filter, an analog filter and digital bass boost
function developed for digital audio equipment.
Because the IC includes an analog filter, it can output a
direct analog waveform, thus reducing the size and cost
of the DA converter.
FEATURES
Built-in 8-times oversampling digital filter.
Low-voltage operations (2.7V) possible.
Built-in digital de-emphasis filter.
In serial control mode, output amplitude can be set in
128 steps of resolution using microcontroller commands.
In parallel control mode, soft mute can be set for the
output signal in 64 steps in 20ms.
Built-in LR common digital zero detection output circuit.
DAC converter oversampling ratio (OSR) : 192fs.
Two types of built-in digital bass boost function.
Sampling frequency .' 44.1kHz.
Built-in third-order analog filter.
SSOP24-P-300-0.65A
Weight : 0.14g (Typ.)
The digital filter and DA converter characteristics are shown on the next page.
TOSHIBA TC9434AFN
DIGITAL FILTER
DF'ICE'TTE/EL PASSBAND RIPPLE TRANSIENT BANDWIDTH ATTENUATION
Standard
. 8fs i0.11dB 20k--24.1kHz -26dB or less
Operation
DA CONVERTER (VDD = 5.0V)
OSR NOISE DISTORTION S/N RATIO
Standard
. 192fs - 85dB (T .) 96dB (T .)
Operation yp yp
PIN CONNECTION BLOCK DIAGRAM
(L32) (L31) (EMP) (SM)
LRCK BCK DATA F1DET ATT SHIFT LATCH VDX XO XI GNDX MCK
V (23(ii)(i"2)(G)(i0)6"9)(i2CQ6is)6is)(iib(i'3)
VOD [1 ME] LRCK
TIr2 W, 1‘1f1 41 1 1 I 1H
P/S E 3 22 u DATA Data ‘Inte‘: ace 'MtlchOntr'olle'rt Oscillator circuit
VDA I: 4 21 U FIDET(LB2) arcul " In er ace Clrcul
R0 r 5 20 a ATT(LB1) ,
GNDA E 6 19 a SHIFT(EMP) Digital filter circuit Timi
VR E 7 18 n LATCH (SM) digital bass boost circuit I Ing
GNDA E 8 17 a VDx attenuator circuit generator
LO r 9 16 El xo de-emphasis filter circuit
VDA r 10 15 [l XI . I
ZD Ell MUGNDX ' .
GNDD E 12 13 a MCK E-d modulator circuit
rr) __________ h; - -,
I Output Output l
J/C, I circuit circuit 'v.",-
L"1 l l l
I Analog Analog I
i filter filter E
L-- - - ---- - __J
VDD T1 w? VDA RO GNDA VR GNDA LO VDA ZD GNDD
2 2001-07-04
TOSHIBA TC9434AFN
PIN FUNCTION
PIN No. SYMBOL I/O FUNCTION REMARKS
1 VDD - Digital block power supply pin.
2 T1 I Test pin. Always set at to "Low".
3 ptr; I Parallel/serial mode select pin.
4 VDA - Analog power supply pin.
5 RO 0 Right channel analog signal output pin.
6 GNDA - Analog GND pin.
7 VR - Reference voltage pin.
8 GNDA - Analog GND pin.
9 LO o Left channel analog signal output pin.
10 VDA - Analog power supply pin.
11 ZD o Zero data detection output pin common to left and right
channels.
12 GNDD - Digital GND pin
13 MCK o System clock output pin.
14 GNDX - Crystal oscillator GND pin.
15 XI I Crystal oscillator connecting pins. 4%
16 xo 0 Generate the clock required by the system. XI XO
17 VDX - Crystal oscillator power supply pin.
18 LATCH I In serial mode, data latch signal input pin. Schmidt
(SM) In parallel mode, soft mute control pin. input
19 SHIFT I In serial mode, shift clock input pin. Schmidt
(EMP) In parallel mode, de-emphasis filter control pin. input
20 ATT I In serial mode, data input pin. Schmidt
(LB1) In parallel mode, dynamic bass boost mode control pin 1. input
21 F1DET I/O In serial mode, FLAT1 mode detection output pin
(LB2) In parallel mode, dynamic bass boost mode control pin 2.
22 DATA I Data input pin.
23 BCK I Bit clock input pin.
24 LRCK I LR clock input pin.
3 2001-07-04
TOSHIBA TC9434AFN
DESCRIPTION OF BLOCK OPERATIONS
Crystal oscillator circuit and timing generator
The clock required for internal operations is generated by connecting a crystal and condensers as
shown in the diagram below.
The IC will also operate when a system clock is input from an external source through the XI pin
(pin 15). However, in this situation, due consideration must be given to the fact that waveform
characteristics, such as jitter and rising/falling characteristics of the system clock, significantly affect
the DA converter's noise distortion and the S/N ratio.
To internal circuit
_ii; (l)"?.),
GNDX XI xo VDX MCK
ll 16.9344MH2
CL; ’ch CL=10~33pF
Use a crystal with a low Cl value and favorable start-up characteristics.
Fig.1 Crystal oscillator circuit configuration
The timing generator generates the clocks and calculation process timing signals required for such
functions as digital filtering and de-emphasis filtering.
Data input circuit
DATA and the LRCK are loaded to the LSI internal shift registers on the BCK signal rising edge. It is
consequently necessary for the DATA and LRCK signals to be synchronized and input on the BCK
signal falling edge as indicated in the timing example below. Also, as DATA has been designed so
that the 16 bits before the change point of LRCK are regarded as valid data, the data must be
input afterwards when the BCK is 48fs or 64fs, etc.
LRCK -l. L-ch ! I-
DATA Nsd15i14i131121110 9 8 7 6 5 4 3 2 LSB'VISBl‘IS 14 13112.11 10i9 8'7 sis 4 3 Z'LSB‘
Fig.2a Input timing chart
4 2001-07-04
TOSHIBA TC9434AFN
When the BCK is 48fs or Mfs, the data is to be input afterwards as shown in the diagram below.
BCK 11 I IHII I I 1 I I I I I I I I I I I I I J 1 HM I I I I I I I H I I I I I I I I 1 J
The 8-times oversampling IIR digital filter eliminates the noise returned from outside the bandwidth
during standard operations.
TabIe-1. Basic characteristics of digital filter
SET MODE PASSBAND RIPPLE TRANSIENT BANDWIDTH ATTENUATION
Standard Operations 10.011dB 20.0k~24.1kHz -26dB or less
The characteristics of the digital filter frequencies are shown below.
I I | |
.0 .0 .o o
U) N A
tl. !ll.. -0.
E g -0
0 44.1 88.2 132.3 176.4 0 2.0 4.0 6.0 8.0 10.012.0 14.016_0 18.0 20022.0 24.0
FREQUENCY (kHz) FREQUENCY (kHz)
Fig.3 Digital filter frequency characteristics
5 2001-07-04
TOSHIBA TC9434AFN
4. De-emphasis filter
ON/OFF is controlled in the parallel mode (P/T=''H'') with the SHIFT (EMP) pin (pin 19).
This is set in the serial mode (P/§="L") with a microcontroller or other equipment. (Refer to 11-2
Microcontroller setting mode for further details on serial mode settings.)
Table-2. De-emphasis filter settings
(when in the parallel mode)
SHIFT (EMP) PIN H L
De-emphasis filter ON OFF
The digitalization of the de-emphasis filter eliminates the need for such external components as
resistors, condensers and analog switches. In addition to this, the coefficients are aligned to reduce
error in the de-emphasis filter characteristics.
The filter structure and characteristics are shown below.
(b +b 2-1)
Transferfunction : Ha)--"""'"-'",'' “T1 1/T2
(1-a12-1) TI=50ps, T2=15ys
Fig.4 IIR digital de-emphasis filter Fig.5 Filter characteristics
5. Digital bass boost circuit
It is possible to select between two types of bass boost with the following pin settings.
TabIe-3. Bus boost mode setting 12
LB1 (20 pin) LB2 (21 pin) Mode E. 8
L L Flat2 ii
L H Bass boost 1 E 4
H L Bass boost 2 3 Bass boost1
H H Flat 1 E 0
0 Bass boost 2
100 1k 10k 20k
FREQUENCY (Hz)
Note : Bass boost 2 matches with
flat 2 when 1kHz or more
Fig.6 Bass boost characteristics
6 2001-07-04
TOSHIBA
6. DA conversion circuit
TC9434AFN
The IC incorporates a second-order E-A modulation DA converter for two channels (simultaneous
output type).
The internal structure of this is shown in fig.7.
Data ()4)
) Output data
(Bit-stream 1-bit DA conversion data)
Second-order 2-n converter: Y(Z) =X(Z) +(1 -2-1)2Q (2)
Fig.7 2-n modulation DA converter structure
The 2-4 modulation clock has been designed to operate at 192fs.
The noise shaping characteristics are shown in fig.8.
NOISE POWER (dB)
0 500k
FREQUENCY (Hz)
Fig.8 Noise shaping characteristics
7. Data output circuit
The output circuit is equipped with a third-order analog Iow-pass filter.
This enables direct analog signals to be acquired from the IC's RO (pin 5) and LO (pin 9) output
PDM signals -vrirari-yr,
Fig.9 Analog filter circuit
RO (LO)
TOSHIBA TC9434AFN
8. Soft mute circuit
The IC is equipped with a soft mute function, and this enables a soft mute to be set for the DA
converter output by switching the SM pin from the "L" level to the "H" level when in the parallel
mode (P/§=”H"). The soft mute's ON/OFF function and the DA converter output are shown in
fig.10.
The Soft mute ON/OFF control function is disabled during level transition.
SM pin input -k ,-.
OFF l ON : OFF
DA converter I I
output level I I
I - I l
I . . I
I Approximately 20ms l l Approximately 20ms I
Fig.10 Changes in the soft mute DA converter output level
9. Zero data detection output circuit
The IC is equipped with a zero data detection output circuit, and pin © is switched from "L" to
"H" when data for both the left channel and the right channel becomes zero data for
approximately 350ms or longer.
This is fixed at "L" when the data for the left channel and right channel is not zero data.
10.FLAT1 mode detection output circuit
The IC is equipped with a FLAT1 mode detection function. The F1DET pin is switched from "H" to
"L" when the FLAT1 mode is detected when in the serial mode (P/§=L).
This pin will remain at "H" when in any bus boost mode other than FLAT1.
8 2001-07-04
TOSHIBA
TC9434AFN
11.Description of internal control signals
The p/T' pin can be used to switch between the parallel control mode (P/ff pin="High" in DC
setting mode) and the serial mode (P/§ pin="Low" with the microcontroller setting mode). The
control settings are described below.
11-1 Parallel mode (P/T ="H" : DC setting mode)
Pins 18, 19, 20 and 21 are used as the mode setting pins shown in the table below when in
the parallel mode
TabIe-4. Pin names at the parallel mode
PINNo. PIN NAME PIN DESCRIPTION
18 SM Soft mute control pin
19 EMP De-emphasis control pin
20 L31 Digital bass boost mode setting pin 1
21 L32 Digital bass boost mode setting pin 2
11-2 Serial mode (P/§="L" : Microcontroller setting mode)
It is possible to make the various settings with a microcontroller when in the serial mode.
Pins 18, 19, 20 and 21 are used as the command input pins shown in the table below when
in the serial mode.
TabIe-5. Pin names at the serial mode
PIN No. PIN NAME PIN DESCRIPTION
18 LATCH Data latch signal input pin
19 SHIFT Shift clock signal input pin
20 ATT Data input pin
21 F1DET FLAT1 mode detection output pin
The LATCH signals and ATT signals are loaded to the LSI internal shift registers on the SHIFT
signal rising edge. It is consequently necessary for the data input from the ATT pin on the
shift signal rising edge to be valid as indicated in the timing example in fig.11. It is also
necessary for the LATCH pulse to rise at least 1.5ps after the final clock rising edge input
from the SHIFT pin. Operating the shift clock with LATCH low destabilizes the internal state,
which may lead to malfunctions, so it must therefore be set to the low level after loading D7
to the register.
SHIFT i i i t l
ATT |D0|D1|Dz
A= 1.5ps or higher
B= 1.5ps or higher
Fig.11 Example of Data setting timing in the serial mode
9 2001-07-04
TOSHIBA TC9434AFN
The various control settings when in the control mode are shown in the table below.
Ensure that all control bits are set when the power supply is turned on.
TabIe-6. Serial mode control settings
SERIAL INPUT DATA CONTROL SIGNALS
MODE 1 MODE 2
D7 0 1
D6 AT6 -
D5 ATS PEMP ATO--6 : Attenuation level setting
D4 AT4 PLBI #EMP : De-emphasis ON/OFF switch
D3 AT3 pd-Bit pLB1 : Digital bass boost mode setting 1
D2 AT2 MONO pLB2 : Digital bass boost mode setting 2
D1 AT1 CHS MONO : Stereo/monauralsetting
D0 ATO - CHS : Output channel setting
11-2-1 Serial setting mode 1
Serial setting mode 1 is enabled when D7="L".
C) Digital attenuator
The digital attenuation command is enabled when D7="L". The attenuation data can
be set in 128 different ways. The relationship with the command's output is shown
below.
Table-7. Attenuation data/audio data output
ATTENUATION DATA
D6--DO AUDIO OUTPUT
7F (HEX) - 0.000dB
7E (HEX) - 0.069dB
01 (HEX) -42.076dB
oo (HEX) - oo
01 (HEX) to 7E (HEX) : The attenuation value is obtained with the following equation.
ATT=20€og (input data/127) dB
Example : When the attenuation data is 7A
ATT=20€og (122/127) dB = -0.349di?
10 2001-07-04
TOSHIBA TC9434AFN
11-2-2 Serial setting mode 2
Serial setting mode 2 is enabled when D7="H".
C) Digital de-emphasis filter
Controlled with the pliMP and the PBS signals.
TabIe-8. Digital de-emphasis filter setting
PO/li' H L
De-emphasis filter ON OFF
© Digital bass boost mode settings
Controlled with PLB1 and PLM.
TabIe-9. Digital bass boost mode settings
PLB1 H L H L
PLB2 H H L L
Mode Flat 1 Bass boost 1 Bass boost 2 Flat 2
When FLAT1 is selected in the serial mode, pin 21 will become the "L" level.
© Stereo/monaural output channel settings
Set with MONO and CHS.
TabIe-10. Stereo, monaural and channel select settings
MONO L H H
CHS M L H
L, R-ch output Stereo output L-ch monaural output R-ch output
(*) "H" or "L"
Note : The F1DET (LB2) pin (pin 21) will become the output pin in the serial mode and
the input pin in the parallel mode.
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
VDD -0.3-6.0
Power Supply Voltage VDA -0.3--6.0 V
VDX -0.3--6.0
Input Voltage Vin -0.3--VDD+0.3 V
Power Dissipation PD 200 mW
Operating Temperature Topr - 35--85 ''C
Storage Temperature Tstg - 55--150 ''C
11 2001-07-04
TOSHIBA TC9434AFN
ELECTRICAL CHARACTERISTICS (Unless otherwise specified Ta = 25°C, VDD = VDX = VDA = 5.0V)
DC CHARACTERISTICS
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
O eratin Po er s I VDD 4.5 5.0 5.5
p g pp y VDX - Ta = - 35~85°C 4.5 5.0 5.5 v
Voltage (1)
VDA 4.5 5.0 5.5
. VDD 2.7 3.0 5.5
Operating Power Supply vDX - Ta = -15--50oc 2.7 3.0 5.5 v
Voltage (2)
VDA 2.7 3.0 5.5
Current Consumption IDD - XI =16.9MHz - 12 20 mA
Input "H" Level VIH VDDXO.7 - VDD V
Voltage "L" Level VIL 0 - VDDXO.3
Input "H" Level IIH - -10 - 10 pA
Current L Level lit.
AC CHARACTERISTICS (Oversampling Ratio-- 192fs)
CHARACTERISTIC SYMBOL CIR- TEST MIN TYP. MAX UNIT
. . . 1kHz sine wave, full-scale input - - -
Noise Distortion 1 THD + N1 1 VDD = VDX = VDA = 5.0V 85 80 dB
. . . 1kHz sine wave, full-scale input - - -
Noise Distortion 2 THD + N2 1 VDD = VDX = VDA = 3.0V 85 78 dB
S/N Ratio S/N 1 88 96 - dB
. 1kHz sinewave,
Dynamic Range DR 1 -60dB input conversion 90 95 - dB
Crosstalk CT 1 1kHz sine wave, full-scale input - -95 -90 dB
Analog Output Level 1kHz sine wave, full-scale input
1 Aout 1 1 VDD = VDX = VDA = 5.0V - 1150 - mVrms
Analog Output Level 1kHz sine wave, full-scale input
2 Aout 2 1 VDD = VDX = VDA = 3.0V - 700 - mVrmS
Operating Frequency fopr - VDD=VDA =VDX; 4.5V 16.1 16.9344 17.8 MHz
In t Fre enc fLR LRCK duty cycle =50% 41.9 44.1 46.3 kHz
pu qu y fBCK - BCK duty cycle = 50% 1.34 2.1168 2.96 MHz
Rise Time tr LRCK BCK . (109f 90%) - - 15
Fall Time tf - ' pm o tl - - 15 ns
Delay Time td - BCK ‘Ledge -9 LRCK, DATA - - 40 ns
12 2001-07-04
TOSHIBA TC9434AFN
It TEST CIRCUIT 1 : With the use of a sample application circuit
DATA LOUT 20kHz Distortion
S G BCK Application circuit factor
LRCK ROUT Ideal LPF gauge
SG : Anritsu : MG-22A or equivalent
LPF .' Shibasoku : Built-in 725C distortion factor gauge filter
Distortion : Shibasoku : 725C or equivalent
PARAMETER JifjlflRJfi1ytfiR& A weight : IEC-A or equivalent
MEASURED A WEIGHT
THD + N, CT OFF
S/N, DR ON
0 AC CHARACTERISTICS STIPULATED POINT (INPUT SIGNAL STIPULATION .' LRCK, BCK, DATA)
10% 90% 10% 90%
BCK -l-hs?(-,
50% tr tf
DATA X X ... X X X
APPLICATION CIRCUIT EXAMPLE
—C MCK GNDD D-t
it--( jGNDx ZD ( )——o ZD Pin
3OEF C'.?,
1693374M= XI VDA 3 DD 5V
ir-ar-CTI- LL LL '"" fu, - o L-ch Analo OUT
30pF I 1 CXO L034 + 1 a [i' 9
8 a I 8 g t,
5V
LATCH(SM) m VR -,
" SHIFT(EMP) GNDA I '--ri-t
XI _i'e-C yd I :1
a + C) 2200
EMPH _,"s--o-CATT(Lisl) RO cy S N. lg a OR-ch Analog OUT
TC9236AF u 8 .2
single-chip _i'e-C)F1DET(cis2) VDA cy tr 5V Je' 3
processor for m -
CD players AOUT —C DATA P/S C)
BCK -C BCK T1 cy t t
CHCH —C LRCK A VDD + -tr 5V
13 2001-07-04
TOSHIBA TC9434AFN
PACKAGE DIMENSIONS
SSOP24-P-3204(.)-0.65A 13 Unit : mm
R'"""""""'"""'; . h-
HHH"HHHHHH_____4;
0.325TYP 0.222+0.1
=! " C 0.13
M 8.3MAX
_ 7.8:t0.2 =
31 ii: iii"
l Cs!“ (0
1l1lulllllllll:lulllul C.).:':,)),..,...-',?.'..] 'e.'.
IL? l l O.45i0.2
Weight : 0.14g (Typ.)
14 2001-07-04
TOSHIBA TC9434AFN
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
15 2001-07-04
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