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TC9409BF
SINGLE CHIP KARAOKE LSI
TOSHIBA TC9409BF
TENTATIVE TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9409BF
SINGLE CHIP KARAOKE LSI
This IC is single chip KARAOKE LSI for LD/CD player,
Mini compo, VTR.
As built-in ADC/DAC, Sound Field Control and bass
treble(DSP effect), Mic echo, Vocal cancel, and
keycontrol, this IC constructs KARAOKE function.
FEATURES
0 Built-in 3channel AD converter.
THD : -65dB S/N '. 78dB (typ.)
Built-in Ope Amp for Pre-filter. QFP44-P-1414-0.80D
o Built-in 2channel DA converter. Weight 1 I.07g (Typ.)
THD : -85dB S/N .' 93dB (typ.)
Built-in 3rd Analog filter.
It Input : 3 Analog channel, 1 Digitel stereo port.
Digital Input format .' MSB first 16, 18, 20bit effective data before change point of LRCK or PS.
It Output : 2 Analog Output/l Digitel stereo port.
Digital Output format : MSB first 16, 20bit effective data before change point of LRCK or PS.
o Built-in 64Kbit delay RAM.
0 KARAOKE function
Mic echo or Sound field control : Delay time variable.
Vocal cancel : suppress vocal signal from stereo source.
Double Audio source : Digital input and Analog input (addition L-ch and R-ch)
Vocal change : According to Mic signal input or not input, effective vocal
cancel or not effective vocal cancel.
Key control : 14step (MAXi1octave)
Bass treble
0 Package is OFF 44pins.
1 2001-06-19
2001 -06-1 9
BLOCK DIAGRAM [APPLICATION CIRCUIT
TAZOHS
MIC amplifier
MIC IN
OCINE)
1353M l/m
.. . . f
6 "'1 l ‘2
MItTHRU l 3
MICOM IIF F6 CD, LD. MD, etc
Delay RAM J— BCKI Processov
Analog input LINE L-
Tape, Tuner, 5
LD (FM), etc DATA
Hm“) { 3th I
Digital Output
Another
DSP, DAC, etc
Timing Gene.
Zch A 255 / 384
I o512l768 L ______________
1/2 CKS L
vvv V091
Mic THRU ©—I
(o Kali
(si ZVOA
Kt-y-ar-e
L-ch OUT
© ‘. .
Analog OUTPUT l
R-ch OUT I;
G I. ..
TCSflOQBF - 2
TOSHIBA
TC9409BF
TOSHIBA TC9409BF
TERMINAL DESCRIPTION
No. TERMINAL IO FUNCTION REMARK
1 VDA1 - ADC Voltage supply terminal.
2 MICI I MIC LPF input terminal.
3 LPFO1 O MIC LPF output terminal.
4 VRA1 - ADC reference voltage terminal.
5 AIL I LPF input terminal for L-ch Line input.
6 LPF02 O LPF output terminal for L-ch Line input.
7 VRA2 - ADC reference voltage terminal.
8 AIR I LPF input terminal for R-ch Line input.
9 LPFO3 O LPF output terminal for L-ch Line input.
10 GNDA1 - ADC GND terminal.
11 LI I L-ch Analog additional input terminal.
(When not using : OPEN)
12 L2 0 L-ch Digital input 0 detect terminal.
13 GNDA2 - DAC GND terminal.
14 AOL O L-ch DAC output terminal.
15 VR2 - DAC reference voltage terminal.
16 AOR O R-ch DAC output terminal.
17 VDA2 - DAC voltage supply terminal.
18 R2 0 R-ch Digital input 0 detect terminal.
19 RI I R-ch Analog additional input terminal.
(When not using : OPEN)
20 VDX - Crystal oscillator voltage supply terminal.
21 XI I Crystal oscillator connection terminal.
(256, 384, 512, 768fs)
22 XO o Crystal oscillator connection terminal.
23 GNDX - Crystal oscillator GND terminal.
24 VDD1 - Digital voltage supply terminal.
Master clock select terminal.
25 CKS I (H : 256/384fs, L : 512/768fs)
26 MCK2 O 1/2 divider clock output terminal.
27 MCK1 O Oscillator clock output terminal.
28 SDO 0 Digital Audio Data output terminal.
29 BCKO 0 Bit clock output terminal.
30 LRCKO 0 Channel clock output terminal.
31 SDI I Digital Audio Data input terminal.
32 BCKI I Bit clock input terminal.
33 LRCKI I Channel clock input terminal.
34 GNDD - Digital GND terminal.
35 RESET I Reset terminal. ("L" Reset active) pull-up resister
36 IFD I p-COM I/F data input terminal.
37 IFS I p-COM l/F data shift clock input terminal.
38 IFL I p-COM l/F latch pulse input terminal.
De-emphasis filter setting terminal.
39 EMP I ("H" : De-emphasis filter ON)
2001 -06-1 9
TOSHIBA TC9409BF
No. TERMINAL I/O FUNCTION REMARK
40 EXTO O Extend output terminal.
41 TEST I Test terminal. Usually "H" pulI-up resister
42 VDD2 - Digital Voltage supply terminal.
43 VDL - Digital Voltage supply terminal for DRAM.
44 GNDL - Digital GND terminal for DRAM.
Block operating description
1. Operating Clock
Master clock (Input or oscillating XI terminal) is 768/512/384/256fs. These mode are selected by
CKS terminal, and 256fs or 384fs, 768fs or 512fs select is auto detect by this IC.
But following internal synchronize mode can not use 384/768fs, can only use 256/512fs.
And DSP calculate steps don't concern master clock, but DA converter operating clock change by
master clock. DAC is 2-n modulation method and operates oversampling, If 256fs is selected,
Oversampling ratio is 128fs and so became worse S/N, THD+N.
Table.1-1 Master clock select and DAC oversampling ratio.
CKS MASTER CLOCK DAC OVERSAMPLING RATIO
L 768fs 192fs
512fs 256fs
H 384fs 192fs
256fs 128fs
2. Digital Audio Input/Output
Synchronize mode
Data input/output Bit clock is selected internal synchronize or external synchronize by
"SYNM1", "SYNM2". (p-COM l/F bit)
Table.2-1-1 Synchronize mode and Input/Output Bit clock.
SYNM2 SYNM1 SYNCHRONIZE BCKI BCKO
0 0 internal (*) 64fs (**)
0 1 external 32fs BCKI
1 0 external 48fs BCKI
1 1 external 64fs BCKI
(*) Table 2-2-1 shown.
(**) Internal clock divider.
2001 -06-1 9
TOSHIBA
TC9409BF
Input/Output channel clock (LRCKI, LRCKO) data is selected by p-COM I/F. (RLS bit)
Table.2-1-2 Channel clock
OPERATE
LRCKI, LRCKO : "H" Level, L-ch data input/output
LRCKI, LRCKO : "L" Level, L-ch data input/output
2.2 Data Input format
Data input format is Table.2-2-1 and Fig.1.
Selecting use IBIT1 and IBIT2. (p-COM I/F)
Table.2-2-1 Data input format
SYNM2 SYNM1 IBIT2 IBIT1 FORMAT BCKI
o o o o _J§ MSBfirst 16bit 32fs--128fs
o o o 1 2‘3 MSBfirst 18bit 36fs--128fs
o o 1 o 35 MSBfirst 20bit 40fs--128fs
0 0 1 1 -2-, HS MAX20bit 64fs only
0 1 0 0 MSBfirst 16bit 32fs
O 1 0 1 Lu not use 32fs
0 1 1 0 !i) not use 32fs
0 1 1 1 0 not use 32fs
a: . .
1 0 0 O 5 MSBfirst 16bit 48fs
1 0 0 1 , MSBfirst 18bit 48fs
1 0 1 0 C' MSBfirst 20bit 48fs
1 0 1 1 g not use 48fs
1 1 0 0 E MSBfirst 16bit 64fs
1 1 o 1 Q MSBfirst 18bit 64fs
1 1 1 0 MSBfirst 20bit 64fs
1 1 1 1 HS MAX20bit 64fs
5 2001-06-19
TOSHIBA TC9409BF
l8IT1--" L" Iblr2=' L"
MSB LS8 :.'
IiyT1--"H"IBlr2="L" :
SDI CTTErrrrT1CmTITm
_BlT1--"L"lBlr2rr"H" é MSB L58 EEDJIIIIIIIIII I I I |
Hy 1:11:13: 'siFmz1z1z1zmzm11
lBlT1--"H"lBlT2."H" MSit maaazma:m:rmazi,
SDI ':,t:rTazEEmzIzmaa:m '',laazazaazmaaaz:m g
MSB L53 iazTTTITT
Fig.1 Example Data input timing (RLS= "H", SYNM1= "H", SYNM2="H")
2.3 Digital Zero detect function
Table.2-3-1 Digital Zero detect judge time
fs 32kHz M.lkHz 48kHz
Judge Time 1024ms 743ms 683ms
2.4 Stereo / Mono setting
This IC can input Double music source by "MONO", "CHS" bit. (tr-COM I/F)
And this IC can input Double music source by software coefficient, too. Please show Program manual,
Table.2-4-1 Stereo/Mono setting
MONO CHS STEREO / MONO
0 o stereo
o 1 ZERO Detect not use ("L" output only)
1 0 L-ch (CH1) MONO OUTPUT
1 1 R-ch (CH2) MONO OUTPUT
2.5 Data output formats
Table.2-5-1 Data Output formats
SYNM2 SYNM1 OBITZ OBIT1 FORMAT BCKO
o o o 0 4g MSBfirst 16bit 64fs
o o o 1 ".iis',i, MSBfirst 20bit 64fs
o o 1 0 'Ire, us 16bit 64fs
o o 1 1 E; IIS 20bit 64fs
o 1 o o MSBfirst 16bit 32fs f = BCKI)
0 1 0 1 LIJ not use 32fs(=BCKI)
O 1 1 0 "'si' " 16bit 32fs(=BCKI)
0 1 1 1 2 not use 32fs(=BCKI)
1 o o o 5 MSBfirst 16bit 48fs(=BCKI)
1 O 0 1 , MSBfirst 20bit 48fs(=BCKI)
1 0 1 0 I' " 16bit 48fs(=BCKI)
1 o 1 1 g us 20bit 48fs(=BCKI)
1 1 o o E MSBfirst 16bit 64fs(=BCKI)
1 1 o 1 ta MSBfirst 20bit 64fs(=BCKI)
1 1 1 o ug us 16bit 64fst=BCKI)
1 1 1 1 " 20bit 64fs ( = BCK0
TC94098F - 6
6 2001-06-19
TOSHIBA TC9409BF
o8lT1w'1"08IT?--"L'' 5
MSB LSB
(2Blr1--"H"o8lT2--"L'' 2
soc tTrr1TmTrrrmTrrr1 t:ITIrrrE1CrrrrEEITrIT1
MSB LSB
03111='L' OBITZ='H' ;
SOO . cmTEE1zmTrm 3 ETITTTmTITEEm IIIIEIIII
_ EMsa L53 5 3
oiuT1="H'08i"H : , 1
SDD 5 C1TEEEEET2a=rrrrrr1 i l Cmzrrrr
MSB LSB
Fig.2 Example Data Output Timing (RLS= "H", SYNM1= "H", SYNM2 ="H")
3. ps-COM HP
3.1 Setting
y-COM I/F setting is 5 Items.
Command is variable length 7--26bits. (effective data before change point Latch pulse)
When command is 8bits unit, setting is LSB first.
In this case, not using LSB data is not effective.
Example, KEYCOM +300cent setting by 8bit unit.
LSB MSB
- 1 1 0 0 0 0 0
not effective
All this ICs setting change at internal program cycle beginning, but without digital attenuator setting, please mute
output signal at changing program setting.
So Coefficient setting and offset RAM writing is one word at a fs.
When many word change, please by careful.
Table.3-1-1 g-COM l/F setting
KEYCON MODE FUNC. ATT. CRAM
D25 0 o o 0 1
D24 0 o o 1 AD6
D23 o 1 1 AL13 A05
D22 K3 0 1 AL12 A04
D21 K2 CHS EMS AL11 AD3
D20 K1 MONO EM2 AL10 A02
019 K0 OBIT2 EM1 AL09 ADI
D18 - 03111 cm AL08 ADO Me
D17 - 13112 cm AL07 0117
D16 - 13111 CTDW ALOG DT16
015 - SYNM2 CTUP ALOS 0115
D14 - SYNM1 MUTE AL04 0114
D13 - RLS EXTO AL03 0113
D12 - LSM VCS AL02 0112
011 - ADLIM DF2 AL01 DTII
D10 - ADPD DFI ALOO DTIO Me
D09 _ - - - - 0109
D08 - _ - - DT08
D07 - - - - 0107
005 - - - - DT06
005 - - - - DT05
D04 - - - - 0104
D03 - - - - 0103
002 - _ _ 0102 Lbyte
001 - - - - 0101
000 - - - - DTOO
TC9409BF - 7
7 2001-06-19
TOSHIBA TC9409BF
(a) Key Control Setting (7bit command)
IFS -1-C" ..... I I I I I I I I I I I I I I I I i
IFD don't care X K0 X K1 X K2 X K3 y 0 0 0 ‘ don't care
IFL ..... . i
Valid data (7bit)
(b)Coefficient offset RAM writing (26bit command)
IFS I I I I I I I I I : l: I I I I I I I I .i
i I I i
IFD denl't. Eare X DTOO X DT01 x l E X AD4 X ADS X ADS X 1 N don't care
IFL .'. .i-t
. Valid data (26bit) J
Fig.3 Example p-COM I/F
3.2 Key control setting [KEYCON]
Table.3-2-1 Key control setting
[key Up] [key Down]
KB :0] CHANGE KEY KB :0] CHANGE KEY
3210 (cent) 3210 (cent)
0111 +1200 1000 0
0110 +600 1001 -100
0101 +500 1010 -200
0100 +400 1011 -300
0011 +300 1100 -400
0010 +200 1101 -500
0001 +100 1110 -600
0000 0 1111 -1200
8 2001-06-19
TOSHIBA
TC9409BF
SYNM1, 2
IBIT1, 2
OBIT1, 2
Operating mode setting [MODE]
Please set these mode at voltage supply.
When RESET is "L", these data is clear.
: ADC power down (H : power down)
Digital Attenuator soft mute time select (H :twice)
.' Channel clock select (H .' LRCK="L" is L-ch data)
.' DATA input/output synchronize clock select
: Input DATA format select
: Output DATA format select
: MONO DATA input select
: At MONO Setting, channel select, At stereo setting, zero detect setting
DSP setting [FUNC]
At RESET terminal is "L" level, these data is clear.
DF1, 2 , SFC, Mic echo desimetion ratio select
VCS : Vocal cancel characteristic select
EXTO : Expand output terminal OUTPUT DATA
MUTE .' OUTPUT mute CH'' : mute, ATT setting is hold)
CTUP : Vocal change attack time select
CTDW : Vocal change release time select
CEF1 : "L"
CEF2 : Vocal change effect select
EM1, 2 : De-emphasis filter select
EMS : De-emphasis filter block select
Table.3-4-1 De-emphasis setting
TERMINAL I/F SETTING
EMP EMS EM2 EM FUNCTION
0 0 - - OFF
1 0 0 0 de-emphasis 1 44.1kHz
1 o 0 1 DIGITAL INPUT OFF
1 0 1 0 de-emphasis 1 48kHz
1 0 1 1 de-emphasis 1 32kHz
0 1 - - OFF
1 1 0 0 de-emphasis 2 44.1kHz
1 1 0 1 DAC DF OFF
1 1 1 O de-emphasis 2 48kHz
1 1 1 1 de-emphasis 2 32kHz
9 2001-06-19
TOSHIBA TC9409BF
3.5 Digital Attenuator Setting [ATT]
Table.3-5-1 Digital Attenuator level setting
AL [13 : 00] OUTPUT LEVEL
3FFFH - 0.000dB .
3FFDH -0.001dB [Level S.Ettm] * A
3FFBH -0.002dB AL [13 . 00] =3FFFH 10 (LEVEL/20)
2D4EH - 3.000dB
2013H - 6.000dB
0002H - 78.268dB
0001 H - 84.288dB
0000H - codB
Table.3-5-2 Digital Attenuator mute time
LSM 32kHz 44.1kHz 48kHz
0 32ms 23ms 21ms
1 64ms 46ms 42ms
OdB (3FFFH) ---cxadB (0000H) Changing Time
3.6 Coefficient, Offset RAM writing [CRAM]
Coefficient and offset RAM writing operate one word at a fs.
RAM is 128wordx18bit.
Delay RAM Address offset data format is as follows.
Detail setting, please show soft ware manual.
DT17 16 15 14 13 12 11 IO 09 08 07 06 05 04 03 02 01 oo
l2l1l0l2l1liol11l10l09l08l07l06l0slio4lio3l02lio1l00l
MAL I DECI I DLOF I
MAL [2:0] : Delay RAM setting select
DECI [2:0] : Decimation ratio select
DLOF [11 :00] : Offset Address select
Fig.4 Coefficient, Offset RAM, Offset Address Setting
10 2001-06-19
TOSHIBA TC9409BF
4. AD converter
Built-in Line input L-ch and R-ch AD converter, and Mic signal input AD converter.
Mic input signal convert Digital signal and DSP make digital echo signal.
Mic signal add this echo signal by LI, RI terminal or external Op-amp.
It is necessary to open LI and RI terminal at the using Op-amp. When not using AD converter,
please short circuit interval each terminal MlCl-LPFO1, AIL-LPFO2 and AIR-LPF03.
5. DA converter
This is 2-d modulation 1bit DA converter.
Built-in 3'rd Analog Filter.
It is possible to add analog through signal (LI and RI Terminal) at the output portion of DAC.
6. Timing
6.1 Reset Timing
At power supply, please set RESET terminal "L" level at one time.
Power ON Reset Timing is as follows.
Fig.5 Power on Reset Timing
6.2 p-COM l/F Timing
:u-Ts-iu- TS-L.
T1 .' Setup time>lps
T2 : Hold time>1ps
T3, T4, T6 , Clock pulse width>1lus
T5 : Hold time>lps
Fig.6 p-COM I/F Timing
11 2001-06-19
TOSHIBA TC9409BF
MAXIMUM RATINGS
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.r-6.0 V
Input Voltage Vin -0.r-VDD+0.3 V
Power Dissipation PD 500 mW
Operating Temperature Topr -40--85 "C
Storage Temperature Tstg - 55-150 "C
ELECTRICAL CHARACTERISTICS (DC)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply Voltage VDD - Ta = -40--85oc 4.5 5.0 5.5 V
Power Supply Current IDD - Xl=16SMHz, Output No-Ioad - 48 70 mA
"H" Level VIH :9ng - VDD
Input Voltage - Digital input terminal . V V
" " - DD
L Level " 0 x 0.2
"H" Level IIH . . . . - - 1.0
In t C rrent - D tal n t term nal
pu u "L" Level IIL 'g' I pu I - 1.0 - - pA
"H" L I I - . -
Output Current 1 " " eve OHI - LRCKO, BCKO, SDO 3 5 mA
L Level IOL1 - - 2.0
"H" L I I - . -
Output Current 2 " " eve 0H2 - MCK1, MCK2 5 0 mA
L Level IOLZ - - 3.0
Output Current 3 "H" Level IOH3 - EXTO -2.0 - mA
L Level IOL3 - - 2.0
Pull-up Resistance RUP - RESET, TEST - 50 - k0
2001 -06-1 9
TOSHIBA TC9409BF
ELECTRICAL CHARACTERISTICS (AC)
AD converter
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Maximum Input Level Ain - vDD=5.ov - 1.1 - vrms
. -30di? 1kHz
S/(N+D) Ratio S/N(AD) - Sine wave input (*) 68 78 - dB
Total. Harmonic Distortion THD (AD) - _-.0dhs Ikriz - - 65 - 55 dB
+Noise Sine wave input
Cross-talk CT(AD) - - - -68 -60 dB
(*) A-Weight : ON (Typ.)
DA converter
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Output Level Aout - - - 1.2 - Vrms
S/N Ratio S/N(DA) - TOdB Ikriz 87 93 - dB
Sine wave input
-0dB 1kHz
Total Harmonic Distortion THD1 (DA) Sine wave input - -83 -78 dB
N . - -
+ olse THD2(DA) .OdB 10k.HZ - -83 -75
Sine wave input
Cross-talk CT(DA) - - - -88 -83 dB
13 2001-06-19
TOSHIBA TC9409BF
Timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
. . - LRCKO, BCKO, SDO, EXTO - - 15
Rise Time tr - MCK1, MCK2 - - 8
. - LRCKO, BCKO, SDO, EXTO - - 15
Fall Time tf - MCK1, MCK2 - - 8
- LRCKI-9LRCKO - - 30
(External clock synchronous)
- BCKl-yBCKO - - 20 ns
(External clock synchronous)
Delay Time td - BCKO-9SDO - - 10
- MCK1-9LRCKO - - 50
(Internal clock synchronous)
- MCKI-9BCKO - - 20
(Internal clock synchronous)
XI=256fs 8.0 11.3 12.5
Operating Frequency fopr - XI=384fs 10.0 16.9 18.5 MHz
Xl=512fs 16.0 22.6 25.5
XI = 768fs 24.0 33.9 34.0
(Note 1) At the external clock synchronous, LRCKO and BCKO output signal are same as
LRCKI and BCKI input signal.
At the internal clock synchronous, LRCKO and BCKO output signal are output
synchronously with the falling edge of MCK1.
(Note 2) Measured with the output load CL=10pF.
(Note 3) At the XI clock is 256fs, 384fs and 512fs, it is operated with the fs=32kHz,
44.1kHz and 48kHz. At the XI clock is 768fs, it is operated with the fs=32kHz and
44.1kHz.
(Note 4) Delay RAM applications has limitations with the how to control the DRAM. Show
the software manual.
AC CHARACTERISTIC POINT (Input signal : LRCK, BCK, DATA)
BCK -y/'-vs
2001 -06-1 9
TOSHIBA TC9409BF
PACKAGE DIMENSIONS
QFP44-P-1414-0.80D Unit : mm
18.9i0.3
14.0i0.2
3.0TYP
m tiiTululululu3t-
o-ie eo"
1 .352t0.2
Weight : 1.07g (Typ.)
15 2001-06-19
TOSHIBA TC9409BF
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
16 2001-06-19
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