TC9404FN ,SUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTERTC9404FNT(‘QAnAFNv I v I I I‘Z-A MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTERTC9404FN is a 2'n ..
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TC9404FN
SUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTER
TOSHIBA
TC9404FN
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9404FN
Z-A MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTER
TC9404FN is a 2'nd order E-et modulation system 1-bit DA
converter incorporating an 8-times over sampling digital
filter and analog filter developed for digital audio
equipment.
Because the IC includes an analog filter, it can output a
direct analog waveform, thus reducing the size and cost
of the DA converter.
FEATURES
Built-in 8-times over sampling digital filter
Low-voltage operates (2.7-5.5 V) possible
Built-in digital de-emphasis filter
In serial mode, output amplitude can be set in 128 steps
of resolution using microcontroller command.
In parallel mode, soft mute can beset for the output
signal in 64 steps in 20 ms.
Built-in LR common digital zero detection output circuit
Over sampling ratio (OSR) of E-d modulation circuit is 192 fs
Support double speed operation
Sampling frequency : 44.1 kHz, 32 kHz, 48 kHz
Built-in 3'rd order analog filter
The digital filter and DA converter characteristics are as follows
SSOP24-P-300-0.65A
Weight : 0.14g (Typ.)
2001 -06-1 9
TOSHIBA TC9404FN
DIGITAL FILTER (fs = 44.1 kHz)
DIGITAL PASS-BAND TRANSIENT STOP BAND
FILTER RIPPLE BAND WIDTH SUPPRESSION
Standard Operation 8fs -+0.11di? 20 k~24.1 kHz -26dB or less
Double Speed Operation 8fs 10.11dB 20 k~24.1 kHz -26dB or less
DA CONVERTER (VDD = 5V)
OSR DISTORTION S/N
Standard Operation 192 fs -85dB (Typ.) 96 dB (Typ.)
Double Speed Operation 96 fs -85di? (Typ.) 86 dB (Typ.)
PIN CONNECTION BLOCK DIAGRAM
- (SM) (EMP) (BS)
LRCK BCK DATA s ATT SHIFT LATCH VDX xo XI GNDX MCK
GD f2 f2 (ii) (ii) (ii) fiis) fir) (ii) 65 fit) ®
V ty 2all LRCK
'il UzsuscK l 1 l I-l-l-i-l I IH
P ps- E 3 22 El D_ATA Interface circuit PCON Interface OSC
VDA [4 21 [1 HS
RD E 5 20 " ATT(SM) 9 j
GNDA Es 190 SHIFT(EMP) Di it I me irc it
Igl a I r Clr UI
6N5: E; 13% tgchBS) ATT circuit Timing Gen.
LO E 9 16 a XO De-emphasis filter circuit
VDA Elo 15 L1 XI I
20!“ 14EIGNDX ' ' '
GNDD E12 13 n MCK E-d modulation circuit
r--] -
___: ______ -|
Test I Output Output
circuit I circuit circuit
'--n, l l ,
I Analog Analog l
i filter filter ,'
L-- - - - - __J
o.oo.oo.oof2,,rl.,rlrlf.,rls.1,.ro,
VDD T1 PE VDA R0 GNDA VR GNDA LO vDA ZD GNDD
2001 -06-1 9
TOSHIBA TC9404FN
PIN FUNCTION
PIN No. SYMBOL I/O FUNCTION REMARKS
1 VDD - Digital block power supply pin.
2 T1 I Test pin. Always set to "Low" level.
3 p/T; I Parallel/serial mode select pin.
4 VDA - Analog power supply pin.
5 RO C) Right channel analog signal output pin.
6 GNDA - Analog GND pin.
7 VR - Reference voltage pin.
8 GNDA - Analog GND pin.
9 LO o Left channel analog signal output pin.
10 VDA - Analog power supply pin.
11 2D o Digital zero detection output pin.
12 GNDD - Digital GND pin.
13 MCK 0 System clock output pin.
14 GNDX - Crystal oscillator GND pin.
15 XI I . . .
Crystal oscillator connecting pm. $7
16 XO o Generates the clock required by the system. XI XO
17 VDX - Crystal oscillator power supply pin.
18 LATCH I Serial mode : Data latch signal input pin. SHUMITT
(BS) Parallel mode : De-emphasis filter mode select pin. INPUT
19 SHIFT I Serial mode : Shift clock input pin. SHUMITT
(EMP) Parallel mode : De-emphasis filter control pin. INPUT
20 ATT I Serial mode : Data input pin. SHUMITT
(SM) Parallel mode : Soft mute control pin. INPUT
21 Ft!, I Standard/double speed operation mode switching pin.
Standard operation at "H", double speed operation at "L".
22 DATA I Audio data input pin.
23 BCK I Bit clock input pin.
24 LRCK I LR clock input pin.
3 2001-06-19
TOSH I BA TC9404FN
DESCRIPTION OF BLOCK OPERATIONS
1. Crystal Oscillator Circuit and Timing Generator
The clock required for internal operations is generated by connecting a crystal and condensers as
shown in the diagram below.
The IC will also operate when a system clock is input from an external source through the XI pin
(pin 15). However, in this situation, due consideration must be given to the fact that waveform
characteristics, such as jitter and rising/falling characteristics of the system clock, significantly affect
the DA converter's noise distortion and the S/N ratio.
To internal circuit
-il) (l)"?),
GNDX XI xo VDX MCK
ll 16.9344MH2
E ch CL = 10-33 pF
Use a crystal with a low CI value and favorable start-up characteristics.
Fig. 1 Crystal Oscillation Circuit Configuration (when in the 384fs mode)
The timing generator generates the clocks and process timing signals required for such functions as
digital filtering and de-emphasis filtering.
2. Data Input Circuit
DATA and the LRCK are loaded to the LSI internal shift registers on the BCK signal rising edge. It is
consequently necessary for the DATA and LRCK signals to be synchronized and input on the BCK
signal falling edge as indicated in the timing example below. Also, as DATA has been designed so
that the 16 bits before the change point of LRCK are regarded as valid data, the data must be input
with Right-justified mode when the BCK is 48 fs or 64 fs, as shown in Fig.2b.
LRCK -l. L-ch I !'
DATA N5415i14i13-l12-I11I1OI9‘8'7'6'5'4l3i2iLSB'VISBI15'14I13l12.11'10'9|8l7'6i5i4iBiZILSBi
Fig.2a Example of Input Timing Chart
BCK lUlllllililililalzlslllilililalalslillllllllglslslslilillllalglslilililililzlgll
Fig.2b Example of Input Timing Chart
4 2001-06-19
TOSH I BA TC9404FN
3. Digital filter
The 8-times oversampling IIR digital filter eliminates the noise returned from outside the bandwidth
during standard and double speed operations.
TabIe-1 Basic Characteristics of Digital Filter
PASS-BAND TRANSIENT
RIPPLE BANDWIDTH ATTENUATION
Standard operation i0.11dB 20.0 k~24.1 kHz -26dB or less
Double speed operation 10.11dB 20.0 k~24.1 kHz -26dB or less
The characteristics of the digital filter frequencies are shown below.
- 10.00
- 20.00
- 30.00
- 40.00
- 50.00
Gain (dB)
- 60.00
Gain (dB)
- 70.00
- 80.00
- 90.00
-100-00 44.1 88.2 132.3 176.4 -1. 0 2.0 4.0 6.0 &010.012O14O16O18O 20022.0 24.0
Frequency (kHz) Frequency (kHz)
Fig.3 Digital filter frequency characteristics (fs = 44.1 kHz)
4. De-emphasis filter
The built-in digital de-emphasis circuit is available for three kind of sampling frequency, fs of 32
kHz, 44.1 kHz, and 48 kHz. These setting controlled in the parallel mode (P/T = "H") with the
LATCH (BS) pin (pin 18) and SHIFT (EMP) pin (pin 19).
This is set in the serial mode (P/T = "L") with a microcontroller or other equipment. (Refer to 9-2
Microcontroller setting mode for further details on serial mode settings.)
Table-2 De-emphasis Filter Setting (when in the parallel mode)
LATCH (BS) H H L L
SHIFT (EMP) H L H L
MODE (fs SELECT) 32 48 44.1 OFF (kHz)
5 2001-06-19
TOSH I BA TC9404FN
The digitalization of the de-emphasis filter eliminates the need for such external components as
resistors, condensers and analog switches. In addition to this, the coefficients are aligned to reduce
error in the de-emphasis filter characteristics.
The filter structure and characteristics are shown below.
Input data
IGUw)|
. (bo + b1Z-1) 1/T1 1/T2
Transfer function : H (Z) = -
(1 -a12-1) T1 =50ps,T2= 15ps
Fig.4 IIR Digital De-emphasis Filter Fig.5 Filter Characteristics
5. DA conversion circuit
The IC incorporates a 2'nd EAI modulation DA converter for two channels (simultaneous output
type). The internal structure of this is shown in Fig.6.
X Z =n' Z
Data ( ),r+h. . Q ( ) Output data
(Bit-stream 1-bit DA conversion data)
2'nd E-n converter .' Y(Z) = X(Z) + (1 - Z-1)2Q(2)
Fig.6. E-d modulation DA converter
The E-d modulation clock has been designed to operate at 192 fs. The noise shaping characteristics
are shown in Fig.7.
NOISE POWER (dB)
l l l 1 t A I l
0 500k IM
Frequency (Hz)
Fig.7 Noise Shaping Characteristics
6 2001-06-19
TOSH I BA TC9404FN
6. Data output circuit
The output circuit is equipped with a 3'rd analog Iow-pass filter. This enables direct analog signals
to be acquired from the IC's RO (pin 5) and LO (pin 9) output pins.
PDM signals-TNC'"" -
RO (LO)
Fig.8 Analog Filter Circuit
7. Soft mute circuit
The IC is equipped with a soft mute function, and this enables a soft mute to be set for the DA
converter output by switching the SM pin (pin 18) from the "L" level to the "H" level when in the
parallel mode (P/S = "H"). The soft mute's ON/OFF function and the DA converter output are
shown in Fig.9.
The Soft mute ON/OFF control function is disabled during level transition.
SM pin input ' '-
DA converter
output level t
Approximately 20 ms l l Approximately 20 ms
Fig.9 Changes in The Soft Mute DA Converter Output Level
7 2001-06-19
TOSH I BA TC9404FN
8. Common left channel/right channel digital zero data detection output circuit
The IC is equipped with a common left channel/right channel digital zero data detection output
circuit, and the 2D pin (pin 11) is switched from "L" to "H" when data for both the left channel
and the right channel becomes zero data for approximately 350 ms or longer.
This is fixed at "L'' when the data for the left channel and right channel is not zero data.
. Description of internal control signals
The p/T; pin can be used to switch between the parallel mode (P/T pin = "H" in DC setting mode)
and the serial mode (P/T pin = "L" with the microcontroller interface function).
9-1 Parallel mode (P/T = "H" : DC setting mode)
Pins 18, 19 and 20 are used as the mode setting pins shown in the table below when in the
parallel mode.
TabIe-3 Pin names at the parallel mode
PIN No. PIN NAME FUNCTION
18 BS De-emphasis filter mode select pin
19 EMP De-emphasis filter control pin
20 SM Soft mute control pin
9-2 Serial mode (P/ff = "L" : Microcontroller setting mode)
It is possible to make the various settings with a microcontroller when in the serial mode.
Pins 18, 19 and 20 are used as the command input pins shown in the table below when in
the serial mode.
TabIe-4 Pin names at the serial mode
PIN No. PIN NAME FUNCTION
18 LATCH Data latch signal input pin
19 SHIFT Shift clock signal input pin
20 ATT Data input pin
8 2001-06-19
TOSH I BA TC9404FN
The LATCH signals and ATT signals are loaded to the LSI internal shift registers on the SHIFT
signal rising edge. It is consequently necessary for the data input from the ATT pin on the
shift signal rising edge to be valid as indicated in the timing example in Fig.10. It is also
necessary for the LATCH pulse to rise at least 1.5ps after the final clock rising edge input
from the SHIFT pin. Operating the shift clock with LATCH low destabilize the internal state,
which may lead to malfunctions, so it must therefore be set to the low level after loading D7
to the register.
LATCH Cl
sHlFrltltltltltltltlt
aTrlo0lo1lD2lo3lo4loslo6lD7l
A = 1.5 As or higher, B = 1.5 ,us or higher
Fig.10 Example of data setting timing in the serial mode
The various control settings when in the serial mode are shown in the table below.
Ensure that all control bits are set when the power supply is turned on.
Table-S Serial mode control settings
SERIAL INPUT DATA CONTROL SIGNAL
D7 0 1
D6 AT6 PBS
D5 ATS PEMP
D4 AT4 -
D3 AT3 -
D2 AT2 - ATO~6 : Attenuation level setting
D1 AT1 - pM , De-emphasis mode select
D0 ATO - PEMP : De-emphasis ON/OF switch
9 2001-06-19
TOSH I BA TC9404FN
C) Digital attenuator
The digital attenuation command is enabled when D7 = "L". The attenuation data can be set in
128 different ways. The relationship with the command's output is shown below.
Table-6 Attenuation data/audio data output
ATTENUATION DATA
Dir-Do AUDIO OUTPUT
7F (HEX) -0.000 dB
7E (HEX) -0.069dB
01(HEX) -42.076dB
00 (HEX) - oo
01 (HEX) to 7E (HEX): The attenuation value is obtained with the following equation.
ATT = 20 fog (input data /127)dB
Example : In case of attenuator = 7A
ATT = 20 tog (122/127)dB = -0.349dB
© Digital De-emphasis filter
The Digital De-emphasis setting mode is enabled when D7 = "H".
Controlled with PEMP and #35 signal.
TabIe-7 Digital De-emphasis filter setting
PBS H H L L
PEMP H L H L
MODE 32 48 44.1 OFF (kHz)
10 2001-06-19
TOSH I BA TC9404FN
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
VDD -0.3--6.0
Supply Voltage VDA -0.3--6.0 V
VDX -0.3--6.0
Input Voltage Vin -0.3--VDD + 0.3 V
Power Dissipation PD 200 mW
Operating Temperature Topr - 35--85 "C
Storage Temperature Tstg - 55--150 "C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = 25°C, VDD = VDX = VDA = 5V)
DC CHARACTERISTICS
CHARACTERISTICS SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
O eratin Su I VDD 4.5 5.0 5.5
p g ppy VDX - Ta = -35~85°C 4.5 5.0 5.5 v
Voltage (1)
VDA 4.5 5.0 5.5
. VDD Ta = -15~55°C 2.7 3.0 5.5
It)',','),':,'),'"?,)'"" VDX - (Operation frequency 2.7 3.0 5.5 V
g VDA \12 MHz s fop, s 18.5 MHz 2.7 3.0 5.5
Power Dissipation IDD - XI = 16.9 MHz - 12 20 mA
Input "H" Level VIH VDD x 0.7 - VDD V
Voltage "L" Level VIL - o - VDD x 0.3
Input "H" Level IIH
- - - 1 A
Current "L" Level Ill, 10 0 ’u
11 2001-06-19
TOSHIBA TC9404FN
AC CHARACTERISTICS (Over-sampling ratio = 192 fs)
CHARACTERISTICS SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
Table Harmonic 1 kHz Sine wave, full-scale input
Distortion + Noise 1 THD + N1 1 VDD = VDX = VDA = 5.0V - -85 -80 dB
Table Harmonic 1 kHz Sine wave, full-scale input
THD N2 1 - - -7 B
Distortion + Noise 2 + VDD = VDX = VDA = 3.0V 85 8 d
S/N Ratio S/N 1 88 96 - dB
. 1 kHz Sine wave,
Dynamic Range DR 1 -60dB input conversion 90 95 - dB
Cross-talk CT 1 1 kHz Sine wave, full-scale input - -95 -90 dB
Analog Output Level 1 Aout1 1 1 kHz Sine wave, full-scale input - 1250 -
VDD = VDX = VDA = 5.0V mV
1kHz Sine wave, full-scale input rms
Analog Output Level 2 Aout2 1 VDD = VDX = VDA = 3.0V - 750 -
Operating Frequency fopr - VDD = VDA = VDX Ls 4.5V 10 16.9344 18.5 MHz
fLR LRCK duty cycle = 50% 30 44.1 100 kHz
Input Frequency -
fBCK BCK duty cycle = 50% 0.96 2.1168 4.3 MHz
Rise Time tr LRCK BCK (10U 90%) - - 15
Fall Time tf - ' 0 o - - 15 ns
Delay Time td - BCK-L Edge -oLRCK, DATA - - 40 ns
2001 -06-1 9
TOSHIBA
0 TEST CIRCUIT-1 : With the use of a sample application circuit
0 AC CHARACTERISTICS STIPULATED POINT (Input signal stipulation
APPLICATI
TC9404FN
DATA APPLICATION LOUT 20 kHz DISTORITION
S G BCK CIRCUIT EXAMPLE FACTORL
LRCK ROUT IDEAL LPF GAUGE
SG : ANRITSU MG-22A or equivalent
LPF : SHIBASOKU 725C built-in Filter
Distortion Factor Gauge :
MEASURING ITEM
DISTORTION FACTOR GAUGE
SHIBASOKU 725C or equivalent
FILTER SETTING A WEIGHT A weight : IEC-A or equivalent
THD + N, CT
S/N, DR
-y'-s, 50%
10% 90% 10% 90%
: LRCK, BCK, DATA)
"ii''"
ON CIRCUIT
50% tr
ii' X X
D L-ch Analog OUT
O R-ch Analog OUT
—0 MCK GNDD D--t
it C?, GNDX 2D C)--:) ZD
u. C XI VDA D F 5.0V
J,e 2200
18lpF t 't..t LCXO LO D-s + t ' luod f,1,
+ . o o
svn'-+2it"e-c, a GNDA D- t 0 l3 F
-C) LATCH (BS) V VR D-e
g 22 pF
r‘ SHIFT(EMP) GNDA
XI V U I t
h cs F- + o 2200
EMPH " VATNSM) RO cy ‘- M a
Single-chip HS HS VDA Ch ty 5_0V/lg Fe
processor - cu
for CD Player AOUT DATA PIS C)
TC9236AF
BCK —C BCK TI
LRCK A VDD
2001 -06-1 9
TOSH I BA TC9404FN
PACKAGE DIMENSIONS
SSOP24-P-300-0.65A Unit : mm
RflRRRilRRRRRfl d Tr
ii,i)njii 'file/tii-s-c-i-,-.-,-----,-.-,-'',-
0.325TYP " o.22+0.1
=1 ll" o 0.13
8.3MAX "
= 73:02 =
$1 tiii:.', a“?
tht. " e?
I'-.? l l 0.45Hh2
Weight : 0.14g (Typ.)
14 2001-06-19
TOSH I BA TC9404FN
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
15 2001-06-19
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