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TC9335F-001
2-CHANNEL DSP WITH 1-BIT DIGITAL TO ANALOG CONVERTER
TOSHIBA TC9335F-001
TENTATIVE TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9335F-0011
2-CHANNEL DSP WITH 1-BIT DIGITAL TO ANALOG CONVERTER
FEATURES
The TC9335F-001 is a 2-channel digital signal processor
developed for use in digital audio equipment.
It contains a 16 k-bit RAM for data delay operation,
allowing for 2-channel surround stereo reproduction.
Furthermore, it comes with digital tone control,
compressor, and bass boost functions, making it possible
to accomplish versatile digital effects.
What's more, as the TC9335F-001 incorporates a 8-times
oversampling filter and a 1-bit DA converter with a built-
in filter amp, it can output a direct analog waveform.
SSOP30-P-37S-1.00
Weight : 0.4g (Typ.)
Digital effect unit
Incorporates a 3-band tone control function.
Incorporates a selectable bass boost/compressor function.
The bass boost function provides two boost rates to choose from.
The compressor function provides two compression rates to choose from.
Incorporates a 16 k-bit delay RAM.
The decimation ratio can be selected from 1/2 or 1/4.
If you choose a 1/4 decimation, it gives you a 92.9 ms delay.
Incorporates a phase reversing type surround function that gives the listener a great expanse of
sound.
Digital filter unit
It Incorporates a 8-times oversampling digital filter.
0 Incorporates a digital emphasis function.
It Incorporates a digital attenuator function.
Output unit
0 Incorporates a second-order E-n modulation circuit.
It Incorporates a third-order filter amp.
THD + N : -80dB ; S/N ratio : 91 dB at VDD = 3.3V (Typ.)
1 2001-06-19
TOSHIBA TC9335F-001
Coefficient data can be set via microcomputer interface.
Digital data zero detect function is provided independently for the left and right channels.
The system clock can be selected from 384 fs or 512fs.
The device comes in a 30-pin flat package.
BLOCK DIAGRAM
GNDX XI XO VDX MCK MSEL EMP DATAI BCKI LRCKI LRCKO BCKO IFL IFS IFD
(iib(iiibafi7)6ib(irs)a(i"3)62(ir1)a(a6ib(i"i(iis)
II _1 III_1 III
Oscillator circuit timing Data input unit Microcomputer
generator interface unit
DSP unit -
- Digital filter unit -
E-d modulator unit
________'1 ________'1
t l t l
l DAC I I DAC l
I output LPF I I output LPF I
t l t l
I l I I I
ol,o,ooooi,d.,,djooe''.vol9ipc1.ipdopis,
TESTN OE RZ VDD VDA(R) RO GND(R) VR GND(L) LO VDA(L) GND LZ RLS RSTN
2 2001-06-19
TOSHIBA
PIN DESCRIPTION
TC9335F-001
tlf. PIN NAME I/O FUNCTION REMARKS
1 TESTN I Test mode setup pin.
2 OE I LRCKO and BCKO output enable pin. (Output is
enabled when "H" level ; disabled when "L" level.
3 R2 0 R-channel zero detect output pin.
4 VDD - Digital power supply pin.
5 VDA(R) - R-channel DAC power supply pin.
6 RO 0 R-channel analog pin.
7 GNDA(R) - R-channel DAC ground pin.
8 VR - DAC reference voltage pin.
9 GNDA(L) - L-channel DAC ground pin.
10 LO 0 L-channeloutput pin.
11 VDA(L) - L-channel DAC power supply pin.
12 GND - Digital ground pin.
13 L2 0 L-channel zero detect output pin.
14 RLS I Shannel clock polarity select pin. (L-ch = L when
H level)
15 RSTN I Reset pin
16 IFD I Microcomputer interface data input pin.
17 IFS I Microcomputer interface shift clock input pin
18 IFL I Microcomputer interface latch input pin.
19 BCKO o Bit clock output pin.
20 LRCKO 0 Channel clock output pin.
21 LRCKI I Channel clock input pin.
22 BCKI I Bit clock input pin.
23 DATAI I Digital audio data input pin.
24 EMP I Deemphasis setup pin.
25 MSEL I Slack output select pin. (Divide-by-2 clock when
L level)
26 MCK O Clock output pin.
27 VDX - Oscillation circuit power supply pin.
28 XO 0 Oscillator connecting pin.
29 XI I Oscillator connecting pin.
30 GNDX - Oscillation circuit ground pin.
3 2001-06-19
TOSHIBA TC9335F-001
CIRCUIT OPERATION
Crystal oscillator circuit and timing generator
The clock (384 fs or 512fs) required for internal device operation can be generated connecting a
crystal and capacitor to the device's XI and X0 pins as shown below. Or an external source to clock
the device can be fed through the XI pin. In this case, however, the external clock must be
carefully selected because its jitter, rise/fall characteristics, and duty cycle greatly affect the DA
converter's noise distortion and S/N ratio.
tre I {>0 To internal circuit
\J V '
XO VDX MCK
GNDX XI
if-sri')
d; X‘tal/ld
Use a crystal whose CI value is low and that has a good startup property.
Fig.1-1. Configuration of crystal oscillator circuit
The timing generator provides the clock required for the digital filter, deemphasis filter, digital
attenuator, and E-A modulator circuits, as well as timing signal for arithmetic and logic operations.
Clock selection between 384 fs and 512fs automatically accomplished.
Furthermore, the polarity of LRCK can be changed by setting the RLS pin as necessary.
Table.1-1. Selection of channel clock polarities
INPUT ON LRCK POLARITIES
RLS PIN L H
L R-channel data L-channel data
L-channel data R-channel data
In addition, the MCK output can be selected from two types as listed below.
Table.1-2. Selection of input clock
MSEL INPUT MCK OUTPUT
H XI clock is output directly.
L XI clock is output after dividing it by 2.
4 2001-06-19
TOSHIBA TC9335F-001
2. Data input circuit
DATAI and LRCKI are latched into the device at the rising edge of BCKI. Therefore, DATAI and
LRCKI must be input synchronously with the falling edge of BCKI as shown in Fig.2. Furthermore,
since the device is designed in such a way that 16, 18, or 20 bits of DATAI immediately before
LRCKI changes are accepted as valid data, data must be "tail-aligned" (with bits filled beginning
from the end of each block) as it is input to the device when you are using BCKI = 48 fs or 64 fs.
The number of input bits can be set via a microcomputer interface.
BCKI —'ji:i:[iiiiiiiiiiiflfliiiiIiifliiiiiiiiiiifl;
Fig.2-1. Data input timing chart (when input to RLS pin input the low lebel)
If BCKI is 48 fs or 64fs, make sure that data is "eil-aligned" as shown below.
BCKI iiiflfliiiiiiiifliiiiziiiiiiJiiiiiiiiiiiiiziiiziiiziziiiiflzfl
Fig.2-2. Example of input timing chart (When entering 16 bits of data)
5 2001-06-19
TOSHIBA TC9335F-001
3. Digital filter (DF) and various effects (DSP)
The charts below illustrate the configurations of the x8 oversampling FIR digital filter, digital
effect, and emphasis. Standard operation is accomplished by "DSP + DF" processing or "DF"
processing as shown in the flowcharts below. On the other hand, double-speed operation is
accomplished by only DF processing. These operations are set via a microcomputer interface.
0 Standard operation
(1) When using "DSP + DF'' processing (2) When using "DF" processing
Input data
Compressor or bass boost
Input data
x2 oversampling FIR filter
(65th-order)
Deemphasis IIR filter
Phase reversin t e surround
x2 oversampling FIR filter
Wth-order)
x2 oversampling FIR filter
x2 oversampling FIR filter Wth-order)
(65th-order)
Deemphasis IIR filter
x2 oversampling FIR filter
(9th-order)
x2 oversampling FIR filter
(5th-order)
o Double-speed operation
"DF" processing
Input data
x2 oversampling FIR filter
(65th-order)
Deemphasis IIR filter
x2 oversampling FIR filter
Wth-order)
x2 oversampling FIR filter
(5th-order)
(Note) .' Digital effects (DSP) cannot be used when operating at two times normal speed.
6 2001-06-19
TOSHIBA
(1) Digital effects (DSP)
OD Compressor and bass boost function
TC9335F-001
The DSP unit has compressor and bass boost functions whichever function can be enabled as
you select. These functions can be turned on and off under control via a microcomputer
interfase. Fig.3-1. shows the algorithm of compressor and bass boost on/off control. The
numbers prefixed by @ denote the coefficient/offset RAM address. denotes a 1-bit
shift operation.
L-ch input data C)
R-ch input data C)
L-ch output data
R-ch output data
fig.3-1. Compressor/bass boost algorithm
Table.3-1. Compressor/bass boost settings
CM1 CM0 SETTING
0 0 OFF
0 1 Compressor ON
1 0 Bass boost 1
1 1 Bass boost 2
When the compressor is enabled, its
compression rate can be selected between two
rate settings available. Fig.3-2. shows the
compressor's input/output characteristics for
each compression rate.
Table.3-2. Compression rate settings
EFFECT COMPRESSION RATE
0 +6dB
1 +12dB
OUTPUT LEVEL (dB)
Bass boost 1 and 2 allow you to
change the LPF characteristics.
EFFECT = 1
EFFECT = 0
-100 ...
-100 -50 0
INPUT LEVEL (dB)
Fig.3-2. Input/output characteristics of
compressor
2001 -06-1 9
TOSHIBA
TC9335F-001
Furthermore, when using the compressor and boss booster, it is possible to switch over the
attach time and release time as described below.
Table3-3. Attach time/release time settings
Attach time
EFFECT
CTUP 0 1
0 4 ms 6 ms
1 16 ms 24 ms
Release time
EFFECT 0 1
0 0.6 s 1 s
1 6 s 10 s
The output level when using the compressor and the boost add ratio when using the bass
booster can be changed by modifying each coefficient RAM data.
SFC function
The TC9335F-001 allows to perform SFC operation by using its internal 16 k-bit RAM.
The diagram below shows the algorithm of this operation.
input -4
input -4
i." @1CH @1DH
g @1EH @1FH
4 taps : Common
2 taps : Independent
Fig.3-3. Algorithm of SFC operation
2001 -06-1 9
TOSHIBA
TC9335F-001
The TC9335F-001 uses decimation technology to provide a large delay time. Decimation
settings are shown in the table below. By modifying this setting, it is possible to change
coefficients for the decimation and interpolation filters to accomplish decimation. Although
decimation gives a large amount of delay, the pass band is narrowed accordingly.
Table.3-4. Decimation ratio and add ratio settings
DECI1 DECIO "ill/tlf"' L ARISATFTOADD
0 0 1/2 (L + R)/2
0 1 1/2 (L - R)/2
1 0 1/4 (L + R)/2
The taps used for the SFC function are available for six taps each on left and right channels.
Of this, four taps are the same for both left and right channels. The delay position (offset
amount) and coefficient on each tap are set in RAM. The maximum delay time varies with
the decimation ratio selected. Table.3-5. lists the maximum amount of delay for each
decimation ratio.
Table.3-5. Decimation ratio and maximum amount of delay
DECI1 DECIO DECR'XT’TS'ON Atfgli)yg,
0 0 1 /2 46.4 ms
0 1 1 /2 46.4 ms
1 0 1 /4 92.9 ms
Tone control function
The TC9335F-001 has a tone control function whose algorithm is shown below. It consists of
primary IIR + secondary IIR + primary IIR independently for the left and right channels. All of
these coefficients are set to coefficient RAM.
Input data Output data
Fig.3-4. Algorithm of tone control function (Same coefficient for both left and right channels)
9 2001-06-19
TOSHIBA TC9335F-001
© Phase reversing type surround function
To provide a wide expanse of stereo sound reproduction, the DSP unit has in its last stage a
phase reversing type surround (stereo wide) function. Its algorithm is as shown below.
. L-ch output data
L-ch input data
R-ch input data . R-ch output data
Fig.3-5. Algorithm of phase reversing type surround function
Table.3-6. Phase reversing type surround settings
ROA1 ROAO SETTING
0 0 OFF_ The above IIR filter characteristics are
0 1 Stereo W1de 1 different for Stereo Wide 1 through
1 0 Stereo Iv..id.e 2 Stereo Wide 3.
1 1 Stereo Wide 3
10 2001-06-19
TOSHIBA
TC9335F-001
(2) Regarding oversampling filter
The oversampling digital filter is provided independently for three types of fs (44.1 kHz, 32 kHz,
and 48 kHz). Furthermore, two types of filters are available for the 44.1 kHz. Switching between
these types of filters are accomplished by control through the microcomputer interface.
The table below lists the characteristics of the 44.1 kHz oversampling filter.
Table.3-7. Basic characteristics of oversampling digital filter
RIPPLE WITHIN
THE BAND PASSBAND WIDTH ATTENUATION
i0.1dB 20 kHz--24 kHz -52dB
The following graphically illustrates the frequency responses of the oversampling digital filters
for each fs.
It 44.1 kHz filter 1
Fig.3-6.
60 80 100 120 140 160
fl- 0.200
- 0.400
- 0500
4 8 12 16 20 24
Frequency response of oversampling digital filter (1)
11 2001-06-19
TOSHIBA TC9335F-001
o 44.1 kHz filter 2
o 20 40 60 80 100120140 160 0 4 I i, 12 16 20 24
o 32 kHz filter
-30 -th100
fii" -50 fra"
-o.2oo
S?. -60 S?..'
-80 -0.300
-100 -0A00
2;.5 53:25: -0500 ',',',,'),'','.l,'
0 20 40 60 80 100 120 0 4 8 12 16 20 24
(kHz) (kHz)
It 48 kHz filter
, _ 0.100
0 ' i .+ ,
-10 ' . . 0 ----i,- -i- ----N--.g--m--u----Fs---
-20 , '
-30 -0.100
a" -50 E"
‘5 "e-thilt)"
v -60 V
-80 -0.300
-100 -0.400
1 i ' I E 3 -0500 ' '. ( ( , ( , , ' ' ;
o 20 40 60 80 100 120 140 160 180 0 4 8 12 16 20 24
(kHz) (kHz)
Fig.3-6. Frequency response of oversampling digital filter (2)
12 2001-06-19
TOSHIBA TC9335F-001
(3) Regarding deemphasis filter
Deemphasis filtering is performed during the oversampling filtering operation described above.
The deemphasis filter is available for each fs : 44.1 kHz, 32 kHz, and 48 kHz. The table below
shows how this filter is set up. This setup is accomplished by setting the external EMP pin and
microcomputer bits.
Table.3-8. Deemphasis filter setting
MI R MP TER
EEETEQL C OEPTS U DEEMPHASIS FILTER
EM1 EMO
o 0 0 OFF
0 0 44.1kHz
0 1 o 32 kHz
0 1 1 48 kHz
1 o o 44.1kHz
1 o 1 44.1kHz
1 1 o 44.1kHz
1 1 1 44.1kHz
|G(iw)|
Input data 'C, Output data 1/T1 1/T2 ' w
ao+a1Z'1 - -
Transfer coefficient = - T1 - 50 ps, T2 - 15ps
1 - b1Z'1
Fig.3-7. Configuration of deemphasis filter Fig.3-8. Filter characteristics
4. Regarding attenuation
The TC9335F-001 can control the digital attenuation by 7 bits of attenuate data via a
microcomputer. The transmit data consists of 7 bits AL6 through ALO. It is possible to set
attenuation in 128 steps from OdB to -rxy dB by using this data.
Table.4-1. Attenuate data and amount of attenuation
ATTENUATE DATA
AL6--0 OUPUT LEVEL
7F [HEX] OdB
7E [HEX] -0.14dB The output level changes from OdB to
7D [HEX] -0.21dB -co dB at a rate of 1024/fs seconds.
01[HEX] -42.1dB
00 [HEX] - 00 dB
13 2001-06-19
TOSHIBA
TC9335F-001
5. Internal control signals
The TC9335F-001 has the following control signals that can be via a 3-wire serial interface as shown
below.
Table.5-1. Microcomputer control bits
CONTROL SIGNAL
INPUT DATA COEFFICIENT/
ATTENUATOR MODE FILTER OFFSET
D23 0 0 0 1
D22 0 1 1 IFADR4
D21 AL6 0 1 IFADR3
D20 AL5 PSEL2 CM1 IFADRZ
D19 AL4 PSEL1 CMO IFADR1
D18 AL3 PSELO DECI1 IFADRO
D17 AL2 MONO DECIO |FRDT17
D16 AL1 CHS DLRF1 |FRDT16
D15 ALO BIT2 DLRFO IFRDT15
D14 - BITI ROA1 IFRDT14
D13 - - ROAO |FRDT13
D12 - - OSF1 IFRDT12
D11 - - OSFO |FRDT11
D10 - - EM1 1FRDT10
D09 - - EMO IFRDT09
D08 - - CTDW IFRDT08
D07 - - CTUP IFRDT07
D06 - - EFFECT IFRDT06
D05 - - - IFRDT05
D04 - - - IFRDT04
D03 - - - IFRDT03
D02 - - - IFRDT02
D01 - - - IFRDT01
D00 - - - IFRDT00
215/15 21.5,us
hh 'rt. ir"..
F-L: 215/15
l00l01l02l03liil17l18l19l20l21l22lo2s
A2 15,15,32 IS/ss
Fig.5-1.
Microcomputer data setup timing
2001 -06-1 9
TOSHIBA
TC9335F-001
Attenuate data settings
AL6--ALO OUTPUT LEVEL
7F [HEX] OdB
7E [HEX] -0.14dB
00 [HEX] - OD dB
Program & system clock selection
NORMAL/
PSEL2 PSEL1 PSELO PROGRAM SYSTEM CLOCK DOUBLE SPEED
0 0 0 DSP + DF 256 fs Normal speed
0 1 1 DF only 128 fs Normal speed
1 0 1 DF only 256fs Double speed
Selection of sound multiplex mode
Input bit settings
MONO CHS OUTPUT LEVEL BIT2 BITI NUMBER OF INPUT BITS
0 0 Stereo operation 0 0 16 bits
0 1 Stereo operation 0 1 18 bits
1 0 L-ch monaural 1 0 16 bits
1 1 R-ch monaural 1 1 20 bits
Selection of compressor/bass boost
Switching between compressor and bass boost
CM1 CM0 SETTING EFFECT GAIN (LARGE/SMALL)
0 0 OFF 0 Small (+6dB)
0 1 Compressor ON 1 Large (+ 12 dB)
1 0 Bass boost 1
1 1 Bass boost 2
Switching of compressor time constant
CTDW RELEASE TIME CONSTANT CTUP ATTACK TIME CONSTANT
0 Short (.001 dB/fs) 0 Short (.03 dB/fs)
Long (.0005 dB /fs)
Long (.13 dB/fs)
2001 -06-1 9
TOSHIBA TC9335F-001
Switching of decimation ratio Switching of feedback filter
DECI1 DECIO DEC/il/tlj'" DLRF1 DLRFO CUT-OFF FREQUENCY OF FILTER
o o 1 /2 o o 5.5 kHz
0 1 1 /2 o 1 5.5 kHz
1 o 1 /4 1 o 2.8 kHz
1 1 1.4 kHz
Switching of fs of oversampling filter
OSFI OSFO fs OF O¥IE$E§MPLING
0 0 44.1 kHz-I
0 1 44.1 kHz-2
1 0 32 kHz
1 1 48 kHz
ON/OFF of deemphasis filter
MI R MP TER
Elf2,R,',tL C OCBCIDT U DEEMPHASIS FILTER
EM1 EMO
0 0 0 OFF
0 0 1 44.1 kHz
0 1 0 32 kHz
0 1 1 48 kHz
1 0 O 44.1 kHz
1 0 1 44.1 kHz
1 1 0 44.1 kHz
1 1 1 44.1 kHz
The following explains how the coefficient and offset data are set to RAM. IFADR4 through 0 (D22
through 18) in microcomputer setup bits indicate the RAM addresses to which the data are written.
Similarly, IFRDT17 through 00 (D17 through 00) indicate the write data to RAM. Note that when
this 18 bits of data is used for offset, only 10 bits from the MSB are used for this purpose, with the
other 8 bits ignored.
COEFFICIENT DATA OFFSET DATA
IFADR4
... Write address Write address
IFADRO
IFRDT17
... 10 bits data
IFRDT08 .
IFRDT07 18 bits data
... Invalid
IFRDT00
16 2001-06-19
TOSHIBA TC9335F-001
6. Regarding data zero detect function
The TC9335F-001 has a function to detect digital zero in the input data.
If zero data continues for more than 21s/fs seconds (750 ms when fs = 44.1 kHz), the L2 and R2
pins are driven high.
The diagram shows the timing at which zero detection is cleared by releasing the L2 and R2 pins
back low.
DATA IZero dataIZero dataIZero datalZero datal Normal I Normal I Normal I Normal I Normal I Normal I Normal I Normal Normal
data data data data data data data data data
(*) Normal data : Sound data other than zero data
Fig.6-1. Timing at which zero detection is cleared
7. Channel clock and bit clock output
By driving the OE pin high, you can output the channel clock and bit clock to an external device.
The table below lists the clock signals thus output.
Table.7-1. Channel clock and bit clock output
OUTPUT PIN SIGNAL OUTPUT
LRCKO Clock equivalent to sampling period
BCKO Clock 64 times sampling period
17 2001-06-19
TOSHIBA
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
VDD -0.3--4.8 V
Power Supply Voltage VDA -0.3--4.8 V
VDX -0.3--4.8 V
Input Voltage Vin -0.3--VDD + 0.3 V
Power Dissipation PD 200 mW
Operating Temperature Topr - 35--85 "C
Storage Temperature Tstg - 55--150 "C
ELECTRICAL CHARACTERISTICS
(Referenced to VDD
DC CHARACTERISTICS
= VDX = VDA = 3.9V at Ta = 25°C unless otherwise noted)
TC9335F-001
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
. VDD 3.5 3.9 4.3
Operating Power Supply VDX - Ta = -35--85oc 3.5 3.9 4.3 v
Voltage (1)
VDA 3.5 3.9 4.3
. VDD Ta = -1r-5ooc 3.1 3.3 4.3
sgligat;”?2)P°wer Supply VDX - (Operating frequency , 3.1 3.3 4.3 v
g VDA 10MHzS few; 17 MHz 3.1 3.3 4.3
Current Consumption IDD - XI = 16.9 MHz, VDD = 3.3V - 15 25 mA
"H" Le el V - V
Input V IH - 0.7 DD v
Voltage "L'' Level VIL 0 - VDD x
Input ll' Level IIH - -10 - 10 pA
Current L Level 'IL
2001 -06-1 9
TOSHIBA TC9335F-001
AC CHARACTERISTICS (Oversampling rate = 192 fs)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
. . . 1 kHz sine wave, full-scale input
Noise Distortion THD + N 1 VDD = VDX = VDA = 3.3V - 80 78 dB
. 1 kHz sine wave, full-scale input
S/N Ratio S/N 1 VDD = VDX = VDA = 3.3V 84 91 - dB
. In terms of 1 kHz sine wave,
Dynamic Range DR 1 -60di? input 82 88 - dB
Crosstalk CT 1 1 kHz sine wave, full-scale input - -83 -78 dB
1 kHz sine wave, full-scale input
Analog Output Level Aout 1 VDD = VDX = VDA = 3.3V - 740 - mVrms
Operating Frequency fopr - VDD = VDA = VDX 2 3.1 V 10 16.9344 19.2 MHz
In ut Fre uenc fLR LRCKI duty cycle = 50% 30 44.1 100 kHz
p q y fBCK BCKI duty cycle = 50% 0.96 2.1168 4.3 MHz
Rise Time tr LRCKI and BCKI pins - - 15 ns
Fall Time tf (10% to 90%) - - 15
. BCKI-L falling edge
Delay Time td - -aLRCKl, DATAI - - 40 ns
19 2001-06-19
TOSHIBA
TC9335F-001
0 Test cicuit 1 : A Typ. application circuit is used.
Distortion
DATA LOUT 20 kHz
SG BCK Application circuit example
LRCK ROUT Ideal LPF
SG : Anritsu MG-22A or equivalent
LPF : Tsubasoku 725C distortion meter buiIt-in filter
Distortion meter :
Tsubasoku 725C or equivalent
MEASUREMENT DlsToRTKsol1iylflER FILTER
A WEIGHTING CURVE
THD + N, CT OFF
S/N, DR ON
A Weighting curve
: Equivalent to IEC-A
0 AC characteristics stipulated points (Input signals stipulation .' LRCKI, BCKI, and DATAI)
BCKI F
--'"--_, 50%
10% 90%
2001 -06-1 9
TOSHIBA TC9335F-001
APPLICATION CIRCUIT
Microcom puter RLS
VDA(L) 11
220 Q 3.3 prF
LRCKI LO L-ch OUT
BCKI , GND(L)
LSI for DATAl m VR
EMP ' GNDA R
RO R-ch OUT
VDA (R)
16.9334 MH
VDD GND
21 2001-06-19
TOSHIBA TC9335F-001
PACKAGE DIMENSIONS
SSOP30-P-375-1.00 Unit : mm
c'ihvvwinwmi1jil-"-
7 5:0 2
10.7:03
(375mil)
j? H H
EHHHJHHHHHH
15.9MAX J
[ 5ihr-- li
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22 2001-06-19
TOSHIBA TC9335F-001
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
23 2001-06-19
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www.loq.com
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