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TC9327F
DTS MICROCONTROLLER
TOSHIBA TC9327F
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9327F
DTS MICROCONTROLLER (DTS-21)
The TC9327F is a 4-bit CMOS microcontroller for
single-chip digital tuning systems, featuring a built-in
230-MHz prescaler, PLL, and LCD drivers.
The CPU has 4-bit parallel addition and subtraction
instructions (e.g., Al, SI), logic operation instructions (e.g.,
OR, AN), composite decision and comparison instructions
(e.g., TM, SL), and time-base functions.
The package is an 80-pin, 0.5mm-pitch compact package.
In addition to various input/output ports and a dedicated
key-input port, which are controlled by powerful
input/output instructions (IN1 to 3, OUT1 to 3), there are LQFP80-P-1212-0.50A
many dedicated LCD pins, a PWM output port, a BUZR Weight : 0.45g (Typ.)
port, a 6-bit A/D converter, a serial interface, and an IF
counter, etc.
Low-voltage and Iow-current consumption make this microcontroller suitable for portable DTS
equipment.
FEATURES
0 4-bit microcontroller for single-chip digital tuning systems.
0 Operating voltage VDD-- 1.8 to 3.6V, with low current consumption due to CMOS circuitry
(with only the CPU operating when VDD=3V, |DD=100pA Max.)
0 Built-in prescaler (1 /2 fixed divider +2 modulus prescaler : fmax2 230MHz)
0 Features built-in 1/4-duty, 1/2-bias LCD drivers and a built-in 3V booster circuit for the display.
0 Data memory (RAM) and ports are easily backed up.
. Program memory (ROM): 16bitx7168 steps
0 Data memory (RAM) : 4bitx256 words
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within sdecified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual propert or other rights of the third
parties which may result from its use. No license is granted by implication or ot erwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-23 1/80
TOSHIBA TC9327F
62-instruction set (all one-word instructions)
Instruction execution time : 40ps (with 75-kHz crystal) (MVGS, DAL instructions : 80ps)
Many addition and subtraction instructions (12 types each addition and subtraction)
Powerful composite decision instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN)
Data can be transmitted between addresses on the same row.
Register indirect transfer available (MVGD, MVGS instructions).
16 powerful general registers (located in RAM)
Stack levels : 2
Free branching (JUMP instructions) is allowed in the 7168 steps of program memory (ROM) as there
are no pages or fields.
16 bits of any address in the 1024 program memory steps (ROM) can be referenced (DAL
instructions).
Features independent frequency input pins (FMIN and AMIN) and two (DOI and D02) phase
comparator outputs for FM/VHF and AM.
Seven kinds of reference frequencies can be selected via software.
Powerful input/output instructions (IN1 to 3, OUT1 to 3).
Dedicated input ports (K0 to K3) for key input, 29 LCD drive pins (100 segments maximum)
available.
29 I/O ports : 27 input/output programmable in 1-bit units, 1 output-only port, and 1 input-only
port. The 2 IFlN, and DOI pins can be switched by instruction to IN1 (input-only) or 0T2
(output-only). In addition, 9 output LCD output pins for S17 to S25 can be switched to I/O port in
1-bit units.
Three backup modes available by instruction : only CPU operation, crystal oscillation only, clock stop.
Features a built-in 2-Hz timer F/F and a built-in 10/100Hz interval pulse outputs (internal port for
time base).
Allows PLL lock status detection.
Four of the LCD segment outputs (S22 to S25) can also operate as key return timing outputs (KRO
to KR3). The I/O ports are not dedicated for key return timing outputs but can have other uses as
Built-in 20-bit, general-purpose IF counters can detect stations during auto-tuning by counting the
intermediate frequencies of each band.
Built-in buzzer output circuit can output 8 kinds of frequencies in 4 modes : continuous output,
single-shot output, 10-Hz intermittent output, and 10-Hz intermittent 1-Hz interval output.
Features built-in 12-bit PWM circuit usable for easy-to-use D/A converter.
Features a built-in 3-channel, 6-bit A/D converter.
To prevent CPU malfunction, a built-in supply voltage drop detection circuit shuts down the CPU
when the voltage falls below 1.55V.
1997-06-23 2/80
TOSHIBA TC9327F
PlN-ASSIGNMENT
H F s. P
3 +13 o L
0. ors 44 w
r: the' c >
- ov2' _ CC
L C) - U
a) its a
I' Ers - a
3 E: w "s
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.- ll EAAA
2 AA ulrnrNe-
- A n:
n: EE¥A,.§§§
_ 2rzsjli3GC0c:rcrc:i
U mmmmmo<<<
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Iiiiiiililltliii1ill
ugiDayutrrarrarrasts;ts;ts;trrtetrnrryrNrNrNrNs-
tLtLtLtLtLtLtL0LtLrLrLrLrLtLtLtLrLtLrLrL
P6-3(CTRIN2) I/O port Pl-?
MUTE P1-1
TEST PI-O
lFIN(lN1/SCIN) K3
Phase comparator - DO1/OT2 ' K2
output (r-DOI D02 KEY input K1
Radio Power cr-Ho-cry K0
0T1 1 Output port Input port IN2
'- GND P9-3 H
Localescillator ---o- FMIN I PLL (os_zrrfil'l) IIO port P9-2 E.
signal ---o- AMIN P9-1 g
Battery') VDD S25(P9-0/KRO) ,
WET S24(P8-3/KR1) E
313% XOUT S23(P8-2/KR2) J,
34!; XIN S22(P8-1/KR3) g
it-er- vXT S21(P8-0) 'i,
it-n- VLCD S20(P7-3) >,
s:- C1 S19(P7-2) l'
E- C2 $18(P7-1)
it-et- VEE LCD driver (4x25= 100 segments max.) S17(P7-0)
1997-06-23 3/80
TOSHIBA
BLOCK DIAGRAM
iFtNriN1 ISCIN
TC9327F - 4
1 10He
CPU Timing Gene. 2H2 FIF
Reference Divider MPX/ La.
1kHz PSC PLL OFF
4bit Swallow
It15, " Counter/La.
20bit IF Counter
DATA BUS
CODE BUS
COLUMN
(16x7168 Step)
Prog. Counter
Stack Reg. (ZLevel)
LCD/IO ContJLa.
VLCD VLCD
COM Segment D
$17/P7-'0
Instruction
3bit AID
KEY La. KEY
riirer r La, Dec. La KEY Cont.
OMD .-eNetrqCte-eNtrt
"Ix" ..-z¥xxz
cox mmmi
n_\\ 13.0.0.
LOCK Detector
Phase Com.
13bit Programmable
Counter) La,
(lix256 word)
RPN Buf
TC9327F
DOI I 0T2
La. MUTE
MUTE Corn.
I [0-1
P6-3 ICI'RINZ
P6-2 ICTRIN'I
Pa-o t PWM
Bbit BUZR
Pr3 I BUZR
P3-2 1W
P3-1 ISO
PBA? I Sl
8bit Shift
Pitat DC-REF
P2-2 [ADI N 3
P2-1 I ADIN 2
P24] IAD IN 1
Ebit Al 0
RESET VDD
Doubler
Circuit
1997-06-23 4/80
TOSHIBA TC9327F
DESCRIPTION OF PIN FUNCTION
PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
Output common signals to LCD panels.
1 COM1 Through a matrix with pins SI to S25, a
maximum 100 segments can be
2 COM2 displayed. VLCD
LCD common Three levels, l/LCD, VEE, and GND, are '- VEE
output output at 62.5Hz every st. F
3 COM3 VEE is output after system reset and
CLOCK STOP are released, and a
4 COM4 common signal is output after the DISP
OFF bit is set to "o".
Segment signal output terminals for LCD VLCD
LCD segment panel. Together with COM1 to COM4, a
5--20 S1--S16 . . . F
output matrix IS formed that can display a
maximum of 100 segments.
S17/P7-0 LCD segment S17 to S25 are usable as I/O port by VLCD
21--25 , out ut/l/O ort program. -
S21/P8-0 p p Signals for key matrix and the segment C)-, "
S22/P8-1 signals from pins S22/KR3 to S25/KRO
LCD segment . . .
/KR3 t t/I/O rt are output on a time sharing basis.
26--29 I 7: pu t po 4x4= 16 key matrix can be created in
S25/P9-0/ /tiltiyrde urtn t conjunction with key inport ports KO to _ .
KRO I I g ou pu K3. Input Instruction
30--32 P9-1--P9-3 I/O port 9 3-bit l/O port, cbpable of input/output
setup for each bit vua software. f
33 lhl2 Input port 2 I-bit input port E
Inputins'truction
1997-06-23 5/80
TOSHIBA
TC9327F
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
Key input port
4-bit input port for key matrix input,
capable of inputting a maximum of
4x4= 16 key data in combination with
the key return timing outputs (KRO to
KR3) of an LCD segment pin.
Comprises an A/D comparator making it
possible to select high impedance with
pull-down and puII-up pins for inputs,
and to perform programming with a
3-bit input threshold. This allows various
key matrices to be formed.
Also usable as a 4-channel 3-bit A/D
converter with a successive comparison
formula via software.
When an "H" level is applied in key
input ports set to pull-down mode, WAIT
mode is canceled.
Com pa rator
RIN1 I
- Reference
voltage
P1-O~P1-3
l/O port1
The input and output of these 4-bit l/O
ports can be programmed in 1-bit units.
This pin is capable of outputting timing
signals for the key matrix by program.
It contains load resistance in N-ch, and
can form the matrix for a push-key
needing no diode for the key matrix.
By altering the input of I/O ports set to
input, the CLOCK STOP mode or the
WAIT mode can be released, and the
MUTE bit of the MUTE pin can be set to
1997-06-23 6/80
TOSHIBA TC9327F
PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
4-bit l/O ports, allowing input and
output to be programmed in 1-bit units.
Pins P2-0 to P2-2 can also be used for
analog input to the built-in 6-bit,
P2-0/ l/O port 2 3-channel A/D converter.
ADIN1 /AD analog The conversion time of the built-in A/D
voltage input converter using the successive
comparison method is 280ps. The
P2-1/ /AD analog necessary pin can be programmed to AD il-rr,Ti1t,ct-io,,
ADINZ voltage input analog input in 1-bit units, and P2-3 can
42--45 .
be set to the reference voltage input.
P2-2/ /AD analog Internal power supply (VDD) or constant
ADIN3 voltage input voltage (VEE) can be used as the ToA/Dconverter
reference voltage. So battery voltage,
P2-3/ /Reference etc., can be easily detected. The
DC-REF voltage input reference voltage input, for which a
built-in operational amp. is used, has
high impedance.
The A/D converter and all associated
controls are performed via sortware.
1997-06-23 7/80
TOSHIBA
TC9327F
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
P3-0/Sl
P3-1 /SO
P3-2 / SCK
P3-3/BUZR
I/O port3
/Serial data
/Serial data
output
/ Serial clock
/Buzzer output
4-bit l/O ports, allowing input and
output to be programmed in 1-bit units.
Pins P3-0 to P3-2 can also be used for
the HO terminals of serial interface
circuits (SIO).
SIO functions for 4-bit or 8-bit serial
data inputs from the SI pin and outputs
from the SO pin at the WR pin clock
The clock for serial operation (Sik) is
capable of internaI/external options and
rise/fall shift options. The so pin is also
capable of switching to serial inputs (SI),
facilitating the control of various LSl's
and communication between controllers.
All SIO inputs use built-in Schmitt
circuits.
P3-3 pins also functions as the output
for a built-in buzzer. The buzzer output
can select 8 kinds of 0.625 to 3kHz
frequencies with 4modes: continuous
output, single-shot output, 10-Hz
intermittent output, and 10-Hz
intermittent 1-Hz interval output.
SIO, buzzer, and all associated controls
can be programmed.
instruction
SIO ON
(excluding P3-3 pins)
P4-0 IW
P6-2 /
CTRIN1
P6-3 /
CTRINZ
I/O port 4
/ PWM output
I/O port 4
l/O port 6
/Counter input
16-bit I/O ports, allowing input and
output to be programmed in 1-bit units.
The P4-0 pin is also used for built-in
12-bit PWM outputs. The PWM outputs
pulse continuously at 73.26Hz, and can
change the duty of the pulses to 256
steps (8 bits), causing the added pulses
to be output using 4 bits for 16 cycles
(218.5ms).
The P6-2 and P6-3 pins are also used for
input purposes when using 20-bit IF
counters as 12-bit and 8-bit binary
counters.
The P6-2 pin can be used for 12-bit
binary counter inputs, and the P6-3 pin
for 8-bit binary counter inputs.
PWM outputs, counter inputs, and all
associated controls can be programmed.
instruction
(P4-0-P6-1)
(P6-2, P6-3)
1997-06-23 8/80
TOSHIBA
TC9327F
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
Mutiny output
1-bit output port, normally used for
muting control signal output.
This pin can set the internal MUTE bit to
"I" according to a change in the input
of HO port 1. MUTE bit output logic
can be changed: PLL phase difference
can also be output using this pin.
Test mode
control input
Input pin used for controlling TEST
"H" (high) level indicates TEST mode,
while "L" (low) indicates normal
operation.
The pin is normally used at low level or
in NC (no connection) state. (A pull-
down resistor is builtin).
IFIN/IN'I/
f signal input
/Input port
/Cycle
measurement
IF signal input pin for the IF counter to
count the IF signals of the FM and AM
bands and to detect the automatic stop
position.
The input frequency is between 0.35 to
12MHz (0.21/p-pmin). A built-in input
amp. and C coupling allow operation at
low-level input.
The IF counter is a 20bit counter with
optional gate times of 1, 4, 16 and
64ms. 20 bits of data can be readily
stored in memory. This counter is used
as a timer when the IF counter is not
The input pin can be programmed for
use as an input port (IN port). CMOS
input is used when the pin is set as an
IN port.
(Note) To set SCIN, use the pin with DC
coupling and rectangular wave
input.
1997-06-23 9/80
TOSHIBA TC9327F
PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
PLL phase comparator output pins.
When the prescaler output of the
programmable counter is higher than
the reference frequency, output is at
high level. When output is lower than
65 DO1/OT2 Phase the reference frequency, output is at low
comparator level.
output When output equals the reference
/Output port frequency, high impedance output is "
obtained. Because DOI and D02 are "
66 D02 Phase output in parallel, optional filter
comparator constants can be designed for the
output FM/VHF and AM bands.
Pin DOI can be programmed to high
impedance or programmed as an output
port (0T2). Thus, the pins can be used
to improve Iock-up time or used as
output ports.
1997-06-23 10/80
TOSHIBA
TC9327F
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
Hold mode
control input
Input pin for request/release hold mode.
Normally, this pin is used to input radio
mode selection signals or battery
detection signals.
Hold mode includes CLOCK STOP mode
(stops crystal oscillation) and WAIT mode
(halts CPU). Setting is implemented with
the CKSTP instruction or the WAIT
instruction. When the CKSTP instruction
is executed, request/release of the hold
mode depends on the internal MODE
bit. If the MODE bit is "0" (MODE-O),
executing the CKSTP instruction while
the HOLD pin is at low level stops the
generator and the CPU and changes to
memory back-up mode. If the MODE bit
is "I" (MODE-1), executing the CKSTP
instruction enters memory back-up mode
regardless of the level of the HOLD pin.
Memory back-up is released when the
FtoTro pin goes high in MODE-O, or
when the HOLD pin input changes in
MODE-1.
When memory back-up mode is entered
by executing a WAIT instruction, any
change in the HO-LD pin input releases
the mode.
In memory back-up mode, current
consumption is low (below 10PA), and
all the output pins (e.g., display output,
output ports) are automatically set to
low level.
Output port
1-bit output port.
(Note) This output goes high after reset,
and internal latch data is output
as is even when CLOCK STOP is
being executed.
1997-06-23 11/80
TOSHIBA TC9327F
PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
Pins to which power is applied.
Normally, VDD-- 1.8 to 3.6V is applied.
In back-up mode (when CKSTP
instructions are being executed), voltage
can be lowered to 1.0V. If voltage falls
below 1.55V while the CPU is operating, VDD
72 VDD the CPU stops to prevent malfunction o-f
(STOP mode). When the voltage rises
above 1.55V, the CPU restarts.
STOP mode can be detected by checking
the STOP F/F bit. If necessary, execute
initialization or adjust clock by program.
When detecting or preventing CPU
malfunctions using an external circuit,
STOP mode can be invalidated and
rendered non-operative by program. In
that case, all four bits of the internal
TEST port should be set to "I".
69 GND If more than 1.8V is applied when the (D-g GND
pin voltage is 0, the device system is
reset and the program starts from
address "o". (Power on reset)
(Note) To operate the power on reset,
the power supply should start up
in 10 to 100ms.
Using programmable counter input pins
for FM, VHF band.
The 1/2 +pulse swallow system (VHF
mode) and the pulse swallow system (FM
mode) are freely selectable by program.
At the VHF mode, local oscillation
Power-supply
FM local output (VCO output) of 50 to 230MHz -
7O FMIN oscillator signal [0.3Vp_p(Min)] is input, and at the FM
input mode, that of 40 to 130MHz [0.2Vp-p "
(Min)] is input.
A built-in input amp. and C coupling
allow operation at low-Ievel input.
(Note) When in the PLL OFF mode or
when set to AMIN input, the
input is pulled down.
1997-06-23 12/80
TOSHIBA
TC9327F
PIN No. SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
71 AMIN
AM local
oscillator signal
Programmable counter input pin for AM
The pulse swallow system (HF mode) and
direct dividing system (LF mode) are
freely selectable by program. At the HF
mode, local oscillation output (VCO
output) of 1 to 45MHz [0.2Vp-p(Min)] is
input, and at the LF mode, 0.5 to
12MHz [0.21/p-p (Min)] is input.
Built-in input amp. operates with
low-level input using a C coupling.
(Note) When in PLL OFF mode or when
set to FMIN input, the input is
pulled down.
Reset input
Input pin for system reset signals.
FiES-ET takes place while at low level; at
high level, the program starts from
address "o".
Normally, if more than 1.8V is supplied
to VDD when the voltage is 0, the
system is reset (power on reset).
Accordingly, this pin should be set to
high level during operation.
74 XOUT
75 XIN
76 VXT
Crystal oscillator
Crystal oscillator pins.
A reference 75-kHz crystal resonator is
connected to the XIN and XOUT pins.
The oscillator stops oscillating during
CKSTP instruction execution.
The VXT pin is the power supply for the
crystal oscillator. A stabilizing capacitor
(0.47PF typ.) is connected.
TOSHIBA TC9327F
PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
Voltage doubler boosting pin to drive
the LCD.
A capacitor (0.1 to 3.3PF typ.) is
connected to boost the voltage.
The VLCD pin outputs voltage (3.1V),
which has been doubled from the
constant voltage (VEE : 1.55V) using the
capacitor connected between C1 and C2. VLCD
This potential is supplied to the LCD Of
driver.
If the internal VLCD OFF bit is set to
"I" by program, an external supply can
be input through the VLCD pin to drive
the LCD.
At this time, the l/LCD/il potential,
whose VLCD voltage divided using
resisters, is output from the C2 pin.
1.55V constant voltage supply pin to
drive the LCD.
A stabilizing capacitor (0.47PF Typ.) is
connected. This is a reference voltage for -
the A/D converter, key input, and the
bias potential of the LCD common
output.
77 VLCD
Voltage doubler
78 C1 boosting pin
Constant voltage
80 VEE supply pin
(Note 1) When the device is reset (VDD=0V-a1.8V or higher or RESET="L"-9"H") I/O
ports are set to input, the pins for both LCD output and IIO ports and additional
functions (e.g., SIO, A/D converter) are set to I/O port input pins, while the IFIN/
|N1/SCIN pins become IF input pins.
(Note 2) When in PLL OFF mode (when the four bits in the internal reference ports are all
set to "I"), the IFIN/SCIN and FMIN, AMIN pins are pulled down, and DOI and
D02 are at high impedance.
(Note 3) When in CLOCK STOP mode (during execution of CKSTP instruction), the output
ports (excluding 0T1 output) and LCD output pins are all at low level, while the
constant voltage circuit (VEE), the voltage doubler circuit (I/LCD), and the power
supply for the crystal oscillator (VXT) are at VDD level.
(Note 4) When the device is being reset, the contents of the output ports and internal
ports are undefined and must be initialized via software.
(Note 5) When the pins for both LCD output and I/O ports are set to the I/O port, VLCD
potential is used as the power supply for the output, so the VLCD level is output
at "H" level. In addition, the input power supply is at VDD level, so it can be
used in the same way as for the other I/O port inputs.
1997-06-23 14/80
TOSHIBA TC9327F
DESCRIPTION OF OPERATIONS
C) CPU
The CPU consists of a program counter, a stack register, ALU, a program memory, a data memory, a
G-register, a data register, a carry F/F and a judgment circuit.
Program Counter (PC)
The program counter consists of a 13-bit binary up-counter and addresses the program memory
(ROM). The counter is cleared when the system is reset and the programs start from the 0
address.
Under normal conditions, the counter is increased in increments of one whenever an instruction
is executed, but the address specified in the instruction operand is loaded when a JUMP
instruction or CALL instruction is executed.
Also, when an instruction that is equipped with the skip function (AIS, SLTI, TMT, RNS
instructions, etc.) is executed and the result of this includes a skip condition, the program
counter is increased in increments of two and the subsequent instruction is skipped.
MSB LSB
PC PC12 PC11PC10 PC9 PC8 PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO
13-bit
. Stack Register (STACK)
A register consisting of 2x13 bits which stores the contents of the program counter +1 (the
return address) when a sub-routine call instruction is executed. The contents of the stack register
are loaded into the program counter when the return instruction (RN or RNS instruction) is
executed.
There are two stack levels available and nesting occurs with both levels.
ALU is equipped with binary 4-bit parallel add/subtract functions, logical operation, comparison
and multiple bit judgment functions.
This CPU is not equipped with an accumulator, and all operations are handled directly within the
data memory.
1997-06-23 15/80
TOSHIBA TC9327F
4. Program Memory (ROM)
The program memory consists of 16 bitsx7168 steps and is used for storing programs. The usable
address range consists of 7168 steps between address OOOOH and address 1BFFH.
The program memory is divided into 7168 separate steps and consists of pages 0 to 6. The JUMP
instruction can be freely used throughout all 7168 steps. However, the range of use for the CALL
instruction is limited to addresses 4OOH to 7FFH (page 1). It is also possible to use address OOOH
to 3FFH (page 0) in the program memory as a data area, and the 16-bit contents of this can be
loaded into the data register by executing the DAL instruction.
(Note) An address outside of the program loop must be set when establishing a data area within
the program memory.
lBFFH 0800H 0400H 0000H
CALL instruction DAL instruction
specification area specification area
16 bitsx 7168 steps
5. Data Memory (RAM)
The data memory consists of 4 bitsx256 words and is used for storing data. These 256 words are
expressed in row addresses (4 bits) and column addresses (4 bits). 192 words (row
address=addresses 4H to FH) within the data memory are addressed indirectly by the G-register.
Owing to this, it is necessary to specify the row address with the G-register before the data in
this area can be processed.
The addresses 00H to OFH within the data memory are known as general registers, and these can
be used simply by specifying the relevant column addresses (4 bit). These sixteen general registers
can be used for operations and transfers with the data memory, and may also be used as normal
data memories.
(Note) The column address (4 bit) that specifies the general register is the register number of the
general register.
(Note) All row addresses (addresses OH to FH) can be specified indirectly with the G-register.
1997-06-23 16/80
TOSHIBA TC9327F
COLUMN ADDRESS : DC
0123456789ABCDEF
l 0 General register
o l 1 (one from amongst addresses 00H to OFH)
'd,' l
Lu I 2
Indirect specification 9
of row addresses
(4H to FH) with the A
G-register B
* The indirect E
specification of row F
addresses=0H to FH is -
also possible RAM (4 bitsx256 words)
6. G-Register (G-REG)
The G-register is a 4 bit register used for addressing the row addresses (DR=4H to FH addresses)
of the data memory's 192 words.
The contents of this register are validated when the MVGD instruction or MVGS instruction are
executed, and are not affected through the execution of any other instructions. This register is
used as one of the ports, and the contents are set when the OUT1 instruction from amongst the
I/O instructions is executed. (-a Refer to section #1 in Register Ports.)
7. Data Register (DATA REG)
The data register consists of 1x16 bits and loads 16 bits of optional address data from amongst
addresses OOOH to 3FFH in the program memory when the DAL instruction is executed. This
register is used as one of the ports, and the contents are loaded into the data memory in units
of 4 bits when the IN1 instruction from amongst the I/O instructions is executed. (-s Refer to
section #2 in Register Ports.)
8. Carry F/F (CF/F)
This is set when either CARRY or BORROW are issued in the result of calculation instruction
execution and is reset if neither of these are issued.
The contents of carry F/F can only be amended through the execution of addition or subtraction
instructions and are not affected by the execution of any other instruction.
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TOSHIBA TC9327F
9. Judgment circuit (J)
This circuit judges the skip conditions when an instruction equipped with the skip function is
executed. The program counter is increased in increments of two when the skip conditions are
satisfied, and the subsequent instruction is skipped.
There are 29 instructions equipped with a wide variety of skip functions available. (-e Refer to
the items marked with a "W" symbol in the Table of Instruction Functions and Operational
Instructions in section 11.)
10.|nstruction Set Table
A total of 62 instruction sets are available, and all of these are single-word instructions. These
instructions are expressed with 6-bit instruction codes.
High order 2-bit 00 01 10 11
Low order 4-bit 0 1 2 3
0000 0 AI M, I AD r, M TMTR r, M SLTI M, I
0001 1 AIS M, I ADS r, M TMFR r, M SGEI M, I
0010 2 AIN M, I ADN r, M SEQ r, M SEQI M, I
0011 3 AIC M, I AC r, M SNE r, M SNEI M, I
0100 4 AICS M, I ACS r, M LD r, M TMTN M, N
0101 5 AICN M, I ACN r, M ST M, r TMT M, N
0110 6 ORIM M, I ORR r, M MVGD r, M TMFN M, N
0111 7 ANIM M, I ANDR r, M MVGS M, r TMF M, N
1000 8 SI M, I SU r, M lN1 M, C
1001 9 SIS M, I SUS r, M Ihl2 M, C
1010 A SIN M, I SUN r, M lhl3 M, C
1011 B SIB M, I SB r, M JUMP ADDR1 OUT1 C, M
1100 C SIBS M, I SBS r, M OUT2 C, M
1101 D SIBN M, I SBN r, M OUT3 C,
1110 E XORI M, I XORR r, M DAL ADDR3, r
RN, RNS, WAIT
1111 F MVIM M, I MVSR M1, M2 CALL ADDR2 CKSTP, NOOP
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TOSHIBA TC9327F
11.Table of Instruction Functions and Operational Instructions
(Description of the symbols used in the table)
M : Data memory address. Generally one of the addresses from amongst addresses
00H to 3FH in the data memory.
r : General register
One of the addresses from amongst addresses 00H to OFH in the data memory.
PC : Program counter (13 bits)
STACK : Stack register (13 bits)
G : G-register (4 bits)
DATA '. Data register (16 bits)
I : Immediate data (4 bits)
N : Bit position (4 bits)
- : ALL "o"
C : Port code No. (4 bits)
CN : Port code No. (4 bits)
RN : General register No. (4 bits)
ADDR1 : Program memory address (13 bits)
ADDR2 : Program memory address within page 1 (10 bits)
ADDR3 .' High order 6 bit of the program memory address within page 0
Ca : Carry
b : Borrow
|N1-IN3 : The ports used during the execution of instructions |N1 to lN3
OUTI-OUT3 : The ports used during the execution of instructions OUT1 to OUT3
( ) : Contents of the register or data memory
[ lc : Contents of the port indicating code No.C (4 bits)
[ ] : Contents of the data memory indicating the contents of the register or data
memory
[ ]p : Contents of the program memory (16 bits)
IC : Instruction code (6 bits)
* : Commands equipped with the skip function
Dc : Data memory column address (4 bits)
DR : Data memory row address (2 bits)
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TOSHIBA
TC9327F
MACHINE LANGUAGE
skip if not carry
INSTRUCTION MNEMONIC Fm: FUNCTION OPERATION (16 BITS)
GROUP TION DESCRIPTION DESCRIPTION f g E fi
( BITS) (BITS) (BITS) (BITS)
AI Add immediate
M, I - data to memory Me-(M)-rl 000000 DR DC I
Add immediate
AI M M I
l, I * data to memory, SkT(if)c:rr 000001 DR Dc I
' then skip if carry p y
Add immediate
AIN * data to memory, Me-(M) +I
M, I then skip if not Skip if not carry 000010 DR DC I
AIC Add immediate
M I - data to memory Me-(M)+l+ca 000011 DR DC I
' with carry
Add immediate
AICS * data to memory Me-(M) +l+ca
M, I with carry, then Skip if carry 000100 DR DC I
skip if carry
Add immediate
Al N M M I
CM I * daft: to menaory 'tff,,', +ca 000101 DR DC I
ADDITION ' wit f"T t en s Ip I not carry
INSTRUCTIONS AD ie: if not carry
memory to
r, M - general register re-(r)+(M) 010000 DR DC RN
Add memory to
ADS . M
r M * general register, 2;“); (ca; 010001 DR Dc RN
' then skip if carry p y
Add memory to
ADN * general register, re-(r)+(M)
1 1 D D R
r, M then skip if not Skip if not carry 0 00 0 R C N
AC Add memory to
r M - general register re-(r)+(M)-rca 010011 DR DC RN
' with carry
Add memory to
ACS * general register re-(r)+(M)+ca
r, M with carry,then Skip if carry 010100 DR DC RN
skip if carry
Add memory to
ACN * general register re-(r)+(M)-rca
r, M with carry, then Skip if not carry 010101 DR DC RN
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TOSHIBA
TC9327F
MACHINE LANGUAGE
borrow, then skip
if not borrow
INSTRUCTION MNEMONIC Fm: FUNCTION OPERATION (16 BITS)
GROUP TION DESCRIPTION DESCRIPTION f g E fi
( BITS) (BITS) (BITS) (BITS)
SI Subtract immediate
M,l - data from memory MEIMFI 001000 DR DC I
Subtract immediate
SIS * data from Me-(M) -l
M, I memory, then skip Skip if borrow 001001 DR DC I
if borrow
Subtract immediate
SIN * data from Me-(M) -l
M, I memory, then skip Skip if not borrow 001010 DR DC I
if not borrow
SIB Subtract immediate
M I - data from memory Me-(M)-1-b 001011 DR DC I
' with borrow
Subtract immediate
SIBS * data from memory Me-(M)-l-b
M, I with borrow, then Skip if borrow 001100 DR DC I
skip if borrow
Subtract immediate
'et I * (ee Lrom Ce,'')',,','' s',t.f)/f"1t-l,b, 001101 DR DC I
SUBTRACTION ' v31 .fomtavg, t en Ipl not orrow
INSTRUCTIONS S IPI no orr0w
SU Subtract memory
r M - from general re-(r)-(M) 011000 DR Dc RN
' register
Subtract memory
SUS * from general re-(r) -(M)
r, M register, then skip Skip if borrow 011001 DR DC RN
if borrow
Subtract memory
SUN * from general re-(r) -(M)
r, M register, then skip Skip if not borrow 011010 DR DC RN
if not borrow
Subtract memory
SB from general
r, M - register with re-(r) (M) b 011011 DR DC RN
borrow
Subtract memory
from general
SBS * register with rfr.(r). (M) b 011100 DR Dc RN
r, M . Skip if borrow
borrow, then skip
if borrow
Subtract memory
from general
SBN * . . re-ir) - (M) - b
r, M register with Skip if not borrow 011101 DR Dc RN
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TOSHIBA
TC9327F
MACHINE LANGUAGE
INSTRUCTION MNEMONIC F3112- FUNCTION OPERATION IC “GA "l c
GROUP TION DESCRIPTION DESCRIPTION 6 2 4 4
( BITS) (BITS) (BITS) (BITS)
SLTI Skip if memory is
M I * less than Skip if(M)
' immediate data
Skip if memory is
SGERIAI I * 2:38:38" or Skip if(M)2l 110001 DR DC I
immediate data
SEQI Skip if memory is
* equal to Skip if(M)=l 110010 DR DC I
COMPARISON M, I immediate data
INSTRUCTIONS SNEI Skip if memory is
M I * not equal to Skip if(M):sel 110011 DR DC I
' immediate data
SEQ Skip if general
r, M * register is equal to Skip if(r)=(M) 100010 DR DC RN
memory
SNE Skip if general
r M * register is not Skip if(r)=(M) 100011 DR DC RN
' equal to memory
LD r, M - 3222;112:1215? HM) 100100 DR Dc RN
ST Store general
M, r - register to memory Me-(r) 100101 DR DC RN
MVSR Move memory to
M1, M2 - memory in the (DR, DC1)e-(DR, DC2) 011111 DR DC1 DC2
same row
TRANSFER MVIM Move immediate
INSTRUCTIONS M, I - data to memory Mel 001111 DR DC I
Move memory to
destination
MVrGIIDVI - memory referring [(G),(r)le-(M) 100110 DR Dc RN
' to G-register and
general register
Move source
MVGS memory Ireferring
M r - to G-register and Me-[(G),(r)] 100111 DR Dc RN
' general register to
memory
INI Input INI port
l/O M, C - data to memory Me[|N1]C 111000 DR Dc CN
INSTRUCTIONS OUT1 Output contents of
c, M - merrtnory to OUT1 [OUT11ce-(M) 111011 DR Dc CN
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TOSHIBA TC9327F
MACHINE LANGUAGE
INSTRUCTION MNEMONIC Fm: FUNCTION OPERATION IC (123'ng c
GROUP TION DESCRIPTION DESCRIPTION 6 2 4 4
( BITS) (BITS) (BITS) (BITS)
"e,, c - 1'1"tl,N,2,d,C,, Me-flN21c 111001 DR DC CN
OUT2 Output contents of
HO C M - memory to OUT2 [OUT2lce-(M) 111100 DR Dc CN
' port
INSTRUCTIONS
Win, c - 1pdtl,N,3d,',rotr, Me-[IN3lc 111010 DR DC CN
OUT3 Output contents of
C M - memory to OUT3 [OUT31ce-(M) 111101 DR Dc CN
' port
ORR Logical OR .of,
r M - general register re-(r)N/(M) 010110 DR Dc RN
' and memory
ANDR Logical AND of
r M - general register re-(r)/N(M) 010111 DR Dc RN
' and memory
ORIM Logical OR of
- memory and Me-(M)VI 000110 DR Dc I
LOGICAL M, I immediate data
OPERATION Logical AND of
INSTRUCTIONS "Ill) - memory and Me-(M)Al 000111 DR Dc I
' immediate data
Logical exclusive
'er) - OR of memory and Me-(M)Ol 001110 DR Dc I
' immediate data
Logical exclusive
'T'l, - 2213:3223ral re-(r)O(M) 011110 DR Dc RN
memory
Test general
register bits by . .
TMTR * memory bits,then Skip l: r,,[N(M)] 100000 DR DC RN
r, M . . . =all 1
skip if all bits
specified are true
BIT Test general
JUDGMENT register bits by . .
INSTRUCTIONS TMFR * memory bits, then Skip if, r,,[N(M)] 100001 DR DC RN
r, M . . . =all 0
skip if all bits
specified are false
TMT Test memory bits,
M N * then skip if all bits Skip if M(N)=all "I" 110101 DR Dc N
' specified are true
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TOSHIBA
TC9327F
MACHINE LANGUAGE
INSTRUCTION MNEMONIC Fm: FUNCTION OPERATION IC (1: "l c
GROUP TION DESCRIPTION DESCRIPTION 6 2 4 4
( BITS) (BITS) (BITS) (BITS)
TMF Test memory bits,
* then skip if all bits Skip if M(N)=all "o" 110111 DR Dc N
M, N . .
specified are false
Test memory bits,
TMTN then not skip if all Skip if M (N)
oa,tiyJENT M, N * bits specified are =not all "I" 110100 DR DC N
INSTRUCTIONS true
Test memory bits,
TMFN then not skip if all Skip if M (N)
M, N * bits specified are =not all "0" 110110 DR DC N
CAALSDRz - Call subroutine ',',1tflt,gr''2c)+icind 101111 ADDR2(10 bits)
SUB-ROUTINE RN - $3221“ mam PCs-IST/ity) 111111 00 - -
INSTRUCTIONS .
Return to mam
RNS * routine and skip PCe-(STACK)and skip 111111 01 - -
unconditionally
MP JUMP Jum to the .
iNsleLi’icnoNs ADDR1 - addrpess specified PCt-ADDRI 101 ADDRI (13 bits)
DAL Load pro.gram DAT/u-f/ui? + (r)] p ADDR3
ADDR3, r - memory In p.396 0 in page 0 111110 (6 bits) RN
to DATA register
At P="0" H, the
condition is CPU
waiting (Soft wait
OTHER WAIT P - At P="I" H, Wait at condition P 111111 10 0000 P
INSTRUCTIONS except for clock
generator, all
function is waiting
(Hard wait mode)
Clock generator Stop clock generator
CKSTP - stop in m="0" 111111 10 1000 -
NOOP - No operation - 111111 11 - -
(Note 1) The four low order bits of the program memory's 10-bit address specified with the
DAL instruction are addressed indirectly with the contents of the general register.
The execution time for the DAL instruction is 80ps (two machine cycles).
(Note 2) The execution time for the MVGS instruction is 80ps (two machine cycles).
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TOSHIBA TC9327F
C) HO map
All of the ports within the device are expressed with a matrix of six I/O instructions (OUT 1 to 3
instructions and IN 1 to 3 instructions) and a 4-bit code number.
The allocation of these ports is shown on the following page in the form of an l/O map. The ports
used in the execution of the various l/O instructions on the horizontal axis of the I/O map are
allocated to the port code numbers indicated on the vertical axis. The G-register and data register
are also used as ports.
The OUT 1 to 3 instructions are specified as output ports and the IN 1 to 3 instructions are specified
as input ports.
(Note I) The ports indicated by the angled lines on the I/O map do not actually exist within the
device.
The contents of other ports and data memories are not affected when data is output to a
non-existent output port with the execution of the output instruction. The data loaded
from data memories when a non-existent input port has been specified with the execution
of an input instruction becomes '1'.
(Note 2) The output ports marked with an asterisk (*) on the I/O map are not used. Data output
to these ports assume the 'don't care' status.
(Note 3) The Y1 contents of the ports expressed in 4 bits correspond to the data memory data's low
order bits and the Y8 contents correspond to the high order bits.
The ports specified with the six I/O instructions and code No.C are coded in the following manner:
¢i£l L m n (21
l ?Contents of the selection port (indirectly specified data, O-F [HEX])
I/O instruction's operand CN (0-F [HEX])
The six l/O instructions are coded with the digits 1 to 3
INSTRUCTION OUT1 OUT2 OUT3 lN1 Ihl2 lN3
m 1 2 3 1 2 3
Indicates the input/output port
K : Input port (IN1 to lbl3 instructions)
L : Output port (OUT1 to OUT3 instructions)
(Example) The setting for the G-register is allocated to code T' in the OUT1 instruction. The
encoded expression at this time becomes 'il-IF'.
1997-06-23 25/80
1997-06-23 26/80
I/O map
1/0 ¢L1
OUT1 INSTRUCTION
OUTZ INSTRUCTION
OUT3 INSTRUCTION
|N1 INSTRUCTION
INZ INSTRUCTION
INS INSTRUCTION
CODE Y1 Y2 I Y4
Y1|v2|Y4IY8
Y1|Y2lv4lva
Y1IY21Y4 Y8
Y1 I Y2 Y4 [Y8
Y1IY2IY4IY8
IF offsert
+ 1 — 1
A / D control
|I0-1 data
]F control (1an
A/D cata
1/0-1' daté
AD SELol AD $EL1 |REF SELOIREF SEL1
—0| —1| —2| —3
BUSY 1 Manual | OVER
ADO I AD1 1 A02 A03
—o]—1[—2|—3
#1 | #2
Prog rammable counter selection *
A I D control
|/O-2 da‘ta
IF data
A/D data
I / 0-2 data
STA | *
—0[—1|—2|—3
10] 11 [12 [13
AD4 [ ADS | BUSY
-u|—1I-2|-3
Programmable counter
SIO control
|/0—3 da'la
IF data
PA [ PE | PC
edge | W-INV [fi-l/fi SIO-ON
-U|-1]—2|—3
fal f5 |f6|f7
”043 data
—o|—1|-2]H3
Reference part
SIO control
|/0-4 data
IF data
SlO control data
I / 0-4 data
3 [ R1 | R2
STA | 50-1/6 18/1 bit
—o[—1|—2|—3
f8 I 19 [f10lf11
BUSY ICOUNTISIO F/F
—o|—1|—21—3
IF counter control
SlO output data
|I0-5 data
IF data
510 input data
I / 0-5 data
4 0T1 [ sc ON | mm |
Spl‘rt
son | 501 | 502 | 503
—o} -1[ —2| -3
f12 | 1‘13 | f14 |f15
510 | 511 | 512 1513
—o|—1|—2§—3
IF counter control
SlO output data
I/0-6 data
IF data
SIO input data
|/0-6 data
5 STAISTP | Manual | GO |
504 I 505 506 | 507
—U}—1[—2|—3
fit? | 1‘17 | fie |f19
514 | 515 | Sl6 S|7
—0|—1[—21~3
MUTE OUT
Timer reset Test data
6 MUTE IIO |
POL | UNLOCK
2HzF/F] Timer #4 | #5
Timer 570p
2H2 F/FI ”JOHz ] 100112 F/F
D01 control
7 UNLOCK RESET OTC I 0T2 I
UNLOCK
Key scan digit
FIF |ENABLE
KR1fKR2|1|1
PWM/BUZR data
8 FWO/BMO i PW1/BM1
|Pw2/* |'Pw3/*
Key input data
K0|K1|K2|K3
PWM [BUZR data
Key scan control
PW4IBFO PWS/BF1
|PW6/ BF2|PW7 / BEN
KCO | KC1 | KCZ l KCS
Key scan data
KO |K1|K2|K3
PWM data
Key scan data selection
PW8 PW9 PW10
KSD1 | KSDZ | K504 1 KSD8
B PWM ON m
BUZR ON
Buffer
transfer/ *
|/ 0-7 data
-o; -1| -2| -3
HOLD 1 1 1
|IO-7 data
411—1145
Test data
#0 #1 | #2 |
| 108 data
DATA-reg
—o] —1[ —2| —3
d0|d1Id2|d3
l/0-8 data
—o|—1[—2]—3
SEG data selection
H0-9 data
DATA-reg
$1|52|54158
—ol—1[—2|—3
d4| d5 |d6 |d7
l/O-9 data
-o -1 —2 -3
SEG—1 data
IIO controf selection
DATA-reg
COM1 | com | COMB } coma
|I01|I/02[|/04|I/08
d8 1 d9 E10 |d11
|N2 1 1 1
SEG-Z data
[/0 control data
DATA-reg
#1 1#2|
COM1 | com | COMB | coma
logo | 104 [ 10-2 [10-3
d12 | d13 [d14 |d15
‘ Programme bJe counter
TC9 327F n 26
TOSHIBA
TC9327F
TOSHIBA TC9327F
C) Crystal resonator connection
A 75kHz crystal resonator is connected to the device's crystal resonator terminal (XIN, XOUT) as
indicated below.
The oscillation signal is supplied to the clock generator, the reference frequency divider and other
elements, and generates the various CPU timing signals and reference frequencies. The crystal
resonator circuit is powered by the voltage supplied from a built-in rated voltage circuit (VXT= 1.4V
Typ.). This enables the stable operation of the crystal resonator and reduces current consumption.
' (XOUTHXIN) (VXT)
' t9 t9 74 75 76 Q9
CL CL CX X'tal =75kHz
J J CL=15pF Typ. CX=0.47,uF Typ.
(Note) It is necessary to use a crystal resonator with a low Cl value and favorable start-up
characteristics.
C) System reset
The device's system will be reset when the Trt-ft-t terminal is subject to the 'L' level or when a
voltage of 0V-91.81/ or more is supplied to the VDD terminal (power-on reset). The program will
start from the 0 address immediately after the 100ms stand-by time has passed following system
reset.
The W terminal should be fixed at the 'H' level as the power-on reset function is used under
normal conditions.
(Note I) The LCD common output and the segment output will be fixed at the I' level during
system reset and during the subsequent stand-by period.
(Note 2) The internal ports outlined in the table below will be fixed after system reset, but all
other ports will become unstable. It is therefore advisable to initialize the ports with a
program in accordance with necessity.
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TOSHIBA TC9327F
Fixed Internal Ports
PORTS FIXED AT '0' PORTS FIXED AT '1'
SC ON, Split bit (¢L14), manual bit (¢L15) Reference port (¢L13)
IO, POL, UNLOCK bit (¢L16) MUTE bit (¢L16)
DOI control port (¢L17) IFIW (¢L14)
BUZR control ports (¢L18, ¢L19)
PWM ON, BUZR ON, PWM/BUZR, transfer bit
(¢L1B)
Test ports (¢L26, ¢L2FF) Test port (¢L1C)
CKSTP MODE bit (¢L1E)
AD control port (¢L20)
SIO control ports (¢L22, ¢L23)
Timer port (¢K26)
Key scan control ports (¢L290, ¢L292 to ¢L294)
VLCD OFF bit (¢L2FF) DISP OFF bit (¢L2FF)
IO-l to IO-6 and log IO control ports (¢L3F0 to SEG port
¢L3F5, ¢L3FD) (SEG/IO control ports: ¢L3F8 to ¢L3FA)
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TOSHIBA TC9327F
C) Back-up Mode
Three different types of back-up mode can be activated through the execution of the CKSTP
instruction and WAIT instruction.
1. Clock Stop Mode
The clock stop mode is a function that suspends system operations and maintains the internal
status immediately prior to suspension at a low level of current consumption (10pA or less at
VDD=3.0V). Crystal oscillations are suspended simultaneously and all output terminals and output
ports for LCD display purposes are automatically fixed at the 'L' level or at the OFF status. The
mains power voltage can be reduced to 1.0V with the clock stop mode.
Suspension is activated at the CKSTP instruction execution address when the CKSTP instruction is
executed. The next address is executed after approximately 100ms of stand-by time when the
clock stop mode is cancelled.
(1) Clock stop mode setting
There are two types of mode setting for the clock stop mode. The required setting is selected
with the CKSTP MODE bit. This bit is accessed with the OUT1 instruction for which [CN= EH]
has been specified in the operand.
Y1 Y2 Y4 Y8
¢L1E * * * CKSTP
I . 0 : MODE-O
CKSTP mode setting 1 : MODE-1
OD MODE-O
By setting this mode, the clock stop mode is assumed if the CKSTP instruction is executed
when the HOLD terminal is in the I' level. The same operations as the NOOP instruction
will be assumed if the CKSTP instruction is executed when the HOLD terminal is in the 'H'
level.
© MODE-1
By setting this mode, the clock stop mode is assumed when the CKSTP instruction is
executed regardless of the HOLD terminal level.
(Note) PLL will assume the off status during CKSTP instruction execution.
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TOSHIBA TC9327F
(2) Cancelling the clock stop mode
OD MODE-O
The clock stop mode is cancelled when specified in this mode by changing the 'H' level of
the HOLD terminal or the input status of I/O port 1 (P1-0 to P1-3) specified in the input
© MODE-1
The clock stop mode is cancelled when specified in this mode by changing the HOLD
terminal or the input status of I/O port 1 (P1-0 to P1-3) specified in the input port.
(3) Clock stop mode timing
C) MODE-O
CPU operations -rT-clock stop-Stand-by-i"- CPU operations
I _ (Clock stop mode cancelled)
CKSTP instruction K C: ll R,
NOOP CKSTP instruction execution NOOP operations
operations
(The clock stop mode is assumed when the CKSTP instruction is executed when
the HOLD input is in the 'L' level.)
© MODE-1
" . II
XOUT terminal llll] !Hllll II ll II
- . u u
HOLD terminal n X n
t t I I
Clock stop
CPU operations -l-o:,ck stop '' otand-by L CPU. ',
l I , operations l
CKSTP instruction C ll N ll ty
(Clock stop mode cancelled by changed input)
(The clock stop mode is assumed whenever the CKSTP instruction is executed.)
(4) Example of a circuit (example of a MODE-O circuit)
POWER VDD 72 I " POWER
Example of a battery back-up circuit Example of a condenser back-up circuit
1997-06-23 30/80
TOSHIBA TC9327F
2. Wait mode
The wait mode suspends system operations, maintains the internal status immediately prior to
suspension and reduces current consumption. There are two types of wait mode available; the
SOFT WAIT mode and the HARD WAIT mode. Operations are suspended at the address where
the WAIT instruction was executed when the wait mode is activated. The next address is
executed immediately after the wait mode is cancelled without entering a stand-by status.
(1) SOFT WAIT mode
Only the CPU operations within the device are suspended when the WAIT instruction in which
[P=0H] has been specified in the operand is executed. The crystal resonator, display circuit
and other elements will continue to operate normally at this time. The SOFT WAIT mode is
efficient in reducing current consumption during clock operations when used in programs that
include clock functions.
(Note) Current consumption will differ in accordance with the program.
(2) HARD WAIT mode
The operations of all elements, with the exception of the crystal resonator, can be suspended
by the execution of The WAIT instruction in which [P=1H] has been specified in the operand.
This enables even greater levels of current consumption reduction than the SOFT WAIT mode.
It suspends the CPU and the display circuit and all LCD display output terminals are
automatically fixed at the 'L' level. (20PA Typ. at VDD=3V)
(3) Wait mode setting
The wait status is assumed whenever the WAIT instruction is executed.
(Note) The PLL OFF status will be assumed when in the HARD WAIT mode, but the PLL OFF
status will not be assumed when in the SOFT WAIT mode. It is therefore necessary to
set the PLL OFF status in the program prior to executing the SOFT WAIT function.
(4) Wait mode cancellation conditions
The wait mode is cancelled when the following conditions are satisfied:
CD When the input status of the HOLD terminal changes.
© When the 'H' level is input for the key input terminals (K0 to K3). (However, only in the
key input mode.)
(3) When the 2H2 timer F/F is set as 'I' (only with the SOFT WAIT mode.)
(4) When the input status of the I/O port specified in the input port (P1-0 to P1-3) changes.
3. HOLD input port
Y1 Y2 Y4 Y8
fbl41B HOLD 1 1 1
The fl"t51'T5''" terminal can be used as an input port. This bit loads data input with the lN1
instruction for which [CN=BH] has been specified in the operand into the data memory.
It is necessary to access this port prior to the execution of the CKSTP instruction when the clock
stop mode has been set. It is necessary to note that there are cases when the clock stop mode
will not be activated if the CKSTP instruction is executed without this port being accessed.
1997-06-23 31/80
TOSHIBA TC9327F
C) Programmable counter
The programmable counter consists of two modulus pre-scalers, a 4-bit+13-bit programmable
counter and a port to control these elements.
The programmable counter controls the ON/OFF functions for the contents of the reference port.
1. Programmable counter control port
A port for controlling frequencies, division methods and IF correction (IF offset) when in the FM
Y1 Y2 Y4 Y8
¢L10 HF +1 -1 FM
IF offset
Division method setting
Y1 Y2 Y4 Y8
¢L11 #1 #2 * *
-"mr-" .
Programmable counter selection
Programmable counter data
(LSB) Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L12 (PA) (PB) (PC) (PD) ¢L13 P16 (MSB)
-o P0 P1 P2 P3
1 P4 P5 P6 P7
2 P8 P9 P10 P11
3 P12 P13 P14 P15
(Note) '1' is added to the ¢L11 data whenever ¢L12 is accessed.
The division method and offset are accessed with the OUT1 instruction for which [CN=0H] has
been specified in the operand.
Frequency setting is accessed with the OUT1 instruction for which [CN =1H, 2H] has been
specified in the operand, and setting is performed by writing in the PA-PD bit (¢L12). This port
is divided with the programmable counter selection port (¢L11), and a corresponding
programmable counter is set up by setting data in the selection port.
Only the MSB P16 is accessed with the OUT1 instruction for which [CN=3H] has been specified in
the operand, and setting is performed by writing in the P16 bit (¢L13). All data between P0 and
P16 are updated when P16 is set. It is therefore necessary to access P16 without fail even when
updating only certain items of data and to perform setting as the final process.
'1' is added to the programmable counter selection whenever the programmable counter data
(¢L12) is accessed. Setting can easily be carried out by setting 'o' in the programmable counter
selection port and continually accessing the programmable counter data.
1997-06-23 32/80
TOSHIBA
2. Division method setting
TC9327F
The pulse swallow method or direct division method are selected with the HF and FM ports.
The direct division method is selected when in the AM band. The following four methods are
available and should be selected in accordance with the frequency band being used.
"Ag/IE OPERATION INPUT DIVISION
FRE UENCY NUMBER
MODE HF FM DIVISION METHOD RECEIVING Rd/lil TERMINAL (NOTE)
LF 0 0 Direct division method MW/LW 0.5-12MHz AM
HF 1 0 (1/15 or 1/16) Pulse sw l--45MHz IN n
FM 0 1 swallow method FM 40--130MHz
VHF 1 1 1/2x(1/15 or 1/16) VHF 50--230MHz FMIN 2n
Pulse swallow method
(Note) 'n' represents the number of divisions programmed.
IF correction function when in the FM band
It is possible to add or subtract 'I' from the frequency without modifying the number of
divisions programmed when the pulse swallow method has been selected with the IF offset :1
port, and IF offset can be used when in the FM band.
The IF offset function will not operate when the direct division method has been selected.
+1 -l DIVISION NUMBER DIVISION NUMBER
(During VHF) (During FM and HF)
0 0 2-n n
0 1 2. (n - 1) n -1
1 0 2. (n + 1) n +1
1 1 Inhibited Inhibited
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TOSHIBA TC9327F
4. Frequency division number setting
The frequency division number for the programmable counter is set in bits PO to P16 in binary.
It Pulse swallow method (17-bits)
MSB LSB
P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
216 20
The range of frequency division number setting (pulse swallow method)
n=210H to 1FFFFH (528 to 131071)
0 Direct division method (13-bits)
MSB LSB
P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 W jfff4ihk
12 20 u J
The range of frequency division number setting
(direct division method) n=10H to 1FFFH (16 to 8191)
Don't care
(Note 1) The data in ports P0 to P3 is of no concern with the direct division
method, and port P4 becomes LSB.
(Note 2) The program value will become a two-fold frequency division number
when in the VHF mode.
5. Programmable counter circuit configuration
It Pulse swallow method circuit configuration
This circuit consists of two 11-s/hmoduius pre-scalers, the 4-bit swallow counter and a 13-bit
binary programmable counter. A 1/2 frequency divider is added to the front stage of the
pre-scaler when in the VHF mode.
Pre-set
FMIN Cro)-:
13-bit
a v .l J
"VVV-d 1
"Nr-oe,
. ir/ 1
programmable counter
swallow counter
"V9V-o l-l
P4-P16
To the phase comparator
3-o/o-IV‘
AMIN (i)-:
3-0/09
1997-06-23 34/80
TOSHIBA TC9327F
It Direct division method circuit configuration
The pre-scaler is not required if this is selected, and instead, the 13-bit programmable counter
is used.
Pre-set
AMIN CE 13-bit programmable counter
- To the phase comparator
(Note) Both FMIN and AMIN terminals have been fitted into the amplifier, and
small amplitude is possible by linking them to a condenser. The input is
pull-down for input terminals which were not selected with the division
method and when the PLL is in the off mode (set with the reference port).
C) Reference frequency divider
The reference frequency divider divides the oscillation frequencies of the external 75kHz crystal and
generates the following seven types of PLL reference frequency signals; 1kHz, 3kHz, 3.125kHz, 5kHz,
6.25kHz, 12.5kHz and 25kHz. These signals are selected with reference port data.
The selected signal is supplied as a reference frequency for the phase comparator as described
below. Also, the PLL is switched on and off with the contents of the reference port.
1. Reference port
The reference port is an internal port for selecting the seven reference frequency signals. This
port is accessed with the OUT1 instruction for which [CN=3H] has been specified in the operand
(¢L13). Operations for the programmable counter, the IF counter and the reference counter are
suspended and the PLL assumes the off mode when the contents of the reference port are all
'1'. As the frequency division setting data for the programmable counter is updated when the
reference port is set, it is necessary to set the frequency division number of the programmable
counter prior to setting the reference port.
Y1 Y2 Y4 Y8
¢L13 R0 R1 R2 R2 R1 R0 REFERENCE FREQUENCY
u-v---'
Reference frequency selection code 0 0 0 0 1kHz
0 0 1 1 3kHz
0 1 0 2 3.125kHz
O 1 1 3 5kHz
1 0 0 4 6.25kHz
1 0 1 5 12.5kHz
1 1 o 6 25kHz
1 1 1 7 PLL off mode
1997-06-23 35/80
TOSHIBA
TC9327F
C) Phase comparator and lock detection port
The phase comparator compares the difference in phasing between the reference frequency signal
supplied from the reference frequency divider and the frequency division output of the
programmable counter and outputs the result. It then controls the VCO via a low pass filter in order
to ensure that the two frequency signals and the phase difference match.
As the phase comparator outputs both the DOI and D02 tri-state buffer terminals in parallel, it is
possible to ensure the optimum filter constants for the FM/VHF and AM bands during design.
The DOI terminal can also be used as a general-purpose output with the DOI control port. In
addition to this, the DOI terminal can be set at high impedance, which enables PLL loop lock-up
types and other character improvements with the use of the DOI and D02 terminals.
The lock detection port enables the lock status of the PLL system to be detected.
1. DOI control port and the unlock detection port
Y1 Y2 Y4 Y8
¢L17 UNLOCK DO1control
RESET OTC 0T2 Hz
Y1 Y2 Y4 Y8
¢K17 UNLOCK
F/F ENABLE
Unlock enable (
Unlock detection bit (
DOI output high impedance setting , : 'oetlc'thase difference
1 : DOI high impedance
. 0 : 0T2 output 'L'
0 output data bit t : 0T2 output 'H'
(Note) Invalid when Hz is set at 'I'
0 : DOI phase difference output
0T2 output control bit {1 : 0T2 data output
(Note) Invalid when Hz is set at 'I'
data is set at 'I'
itet F/F and unlock enable are reset whenever the
1 : PLL unlock detection enabled
0 : PLL unlock detection on stand-by
1 : PLL unlock status
0 : PLL lock status
1997-06-23 36/80
TOSHIBA TC9327F
OTC, 0T2 and each Hz bit of the DOI control port use the DOI output as a general-purpose
output port and control the high impedance status without having to output the DOI output
phase difference. This can be set in the program depending on the specifications.
The UNLOCK F/F bit detects the phase difference between the programmable counter frequency
division output and the reference frequency when the phasing is misaligned by approximately
180°. The UNLOCK F/F is set when the phase difference does not match (when in the unlock
status). The UNLOCK F/F status is reset whenever the UNLOCK RESET bit is set as '1'.
It is necessary to access to UNLOCK F/F after establishing more time than is required for the
reference frequency cycle after the unlock F/F has been reset in order to detect the phase
difference with the reference frequency cycle. It is for this purpose that the enable bit has been
made available, but the unlock F/F must not be accessed until after it has been confirmed that
the unlock enable has been set at 'I'.
The unlock enable bit will be reset whenever the UNLOCK RESET bit is set at '1'.
The control of these ports and data loading are performed with the OUT1/IN1 instructions for
which [CN=7H] has been set in the operand.
(Note) The DO output will enter a high impedance status when the PLL is in the off mode.
However, the output data will be output without modification when DOI has been set as
the output port (0T2 output).
2. Phase comparator and unlock port timing
Reference frequency J-l-l-l-, l_l
Programmable counter output
Unlock F/F "
Unlock enable _, LI
I I I ' '
I I I H level
I I I I
I I I High impedance fr
DOoutput'" III. III. ................... ll llllllll
I I I I
I I I 'L level I I
I I I I I
I I I I I
Phase difference -l E l_l E I I l Cl C n (P
I I I I I
I I I I I
I I I I I
Lock detection strobe (s, b, I I I
l I l I
Unlock reset execution flt f?t ft I I ti::) I
V l I t
1997-06-23 37/80
TOSHIBA
TC9327F
3. Phase comparator and the unlock port circuit configuration
Reference frequency signal
iii) DO2
Programmable comparator
counter output
UNLOCK UNLOCK
ENABLE F/F
UNLOCK
When a filter constant has been set
for each band
DC-DC V (3V)
converter CC
33:3: "Y"
To the VCO variable 2 +., - 'l,
. " NNN
capacitor Cl 1/1}: 4.7kQ
3 F 2SC4116GR 2.2m
c! 2SK209Y
Example of an active low pass filter circuit
(for reference purposes)
Selector it-ith) D01/0T2
OTC 0T2
D02 Csb?
D01/0T2 C6is? F: (r/co])
When the LPF is shared
(Sets DOI at high impedance
and switches the filter constants)
(Note) The filter circuits illustrated in the above diagrams are for reference purposes only. It
is necessary to examine the system band configuration and characteristics and design
actual circuits in accordance with requirements.
1997-06-23 38/80
TOSHIBA TC9327F
C) IF counter
The IF counter is a 20-bit general-purpose IF counter that calculates FM and AM intermediate
frequencies (IF) during auto-tuning and can be used for detecting auto-stop signals, etc. It is also
equipped with a cycle measurement function to measure the cycle of low frequency pilot signals.
In addition to this, it is also possible to use the general-purpose IF counter as a timer function when
it is not being used for calculation purposes.
The IF counter consists of a 20-bit binary counter and a control port.
1. IF counter control port and data port
Y1 Y2 Y4 Y8
- . 20 bit/12+8 bit counter switching bit
¢L14 0T1 SC ON IF/IN1 Split l . .
0 : 20 bit counter operations
1 : Divided into a 12 bit counter and an 8 bit
counter (The signal is input from P6-2/CTRIN1
and P6-3/CTRIN2.)
IF/IN switching bit (l, : Sets f input .
0 : Sets the general-purpose input port
Cycle measurement/frequency measurement switching bit
0 : Sets cycle measurement
1 : Sets frequency measurement
'1' is set after the output port (note) has been reset, and the output data immediately
prior to the execution of clock stop is saved.
0 : 0T1 terminal 'L' level
1 : 0T1 terminal 'H' level
1997-06-23 39/80
TOSHIBA
Y1 Y2 Y4 Y8
STA/TTT" Manual GO G1
's-v-"
TC9327F
Selection of the gate time for frequency measurements
(measurement time)
G1 GO GATE TIME
0 0 1ms
0 1 4ms
1 0 16ms
1 1 64ms
Frequency measurements automatic/manual mode switching bit
0 : Automatic mode
(Measurement is performed with the above-mentioned
gate time when in the automatic mode)
1 : Manual mode
(Starts/stops measurements with the STA/ST-T bits)
Manual
1 Operated as a binary timer counter
(The timer counter is reset when '1' is set in STA l???)
- IF counter start/stop control bit
Counter stop
Counter start
(counter reset when the timer counter is set)
1997-06-23 40/80
TOSHIBA TC9327F
¢K10 Y1 Y2 Y4 Y8
BUSY Manual OVER 1
t Overflow detection (d : IF counter calculation valueS220-1
1 : f counter calculation valueiz20
(Overflow status)
Operation mode {0 : IF counter automatic mode
1 : IF counter manual mode
Operation monitor{0 : IF counter calculation ended
1 : IF counter calculation m progress
¢K11 ¢K12 ¢K13 ¢K14 ¢K15
Y1 Y2 Y4 Y8
f0 fl f2 f3 f4 f5 f6 f7 f8 f9 f10 fll f12 f13 f14 f15 f16 f17 f18 f19
20 219
75kHz 75kHz - Frequency
2 220 during
l l timer..
LSB IF counter data MSB counting
(Note) The IFIN input amplifier is disabled in the PLL off mode when the IF input
is set.
(Note) The IF counter can be operated in any mode regardless of the PLL mode
when the INI input (general input port) is set.
Signals are input at the logic level in this event.
(1) IF counter automatic mode (frequency measurement)
In order to use the IF counter automatic mode, the IF terminal for which input is required is
set in the IF input with the IF/TN'T switching bit, and the SCON bit is set at the frequency
measurements mode's 'o'.
The IF counter is operated by setting the gate time with the IF input frequency band, setting
'0' for the manual bit and setting 'I' for the STA/Trp- bit.
This inputs the clock from the IF terminal to the 20-bit binary counter during the set gate
time, and the input pulse is counted and then finished. The point for finishing IF counter
calculation is determined by referencing the BUSY bit. Also, the OVER bit is set at 'I' if the
calculation value reaches a pulse count of 220 or more.
By determining that the BUSY bit and the OVER bit are set at 'o', the frequency input to the
IF input terminal is calculated by loading the IF data in to to f19.
1997-06-23 41/80
TOSHIBA TC9327F
(2) IF counter manual mode (frequency measurement)
The manual mode is used to control the gate time with the internal time base (10Hz, etc) and
measurement the IF frequency.
This method is activated by setting the IF counter in the same way as explained for the
automatic mode and then setting the GO/GI bit data at anything other than '1'. Calculation
is then started by setting the Manual bit to 'I' and setting the STA/W bit to '1'.
Calculations are terminated by setting the STA/TTT' bit to '0', and the data is loaded in
binary.
(3) IF counter cycle mode (cycle measurement)
This mode is used to measure the low frequencies that cannot be measured with the
frequency measurement method.
Measurement is performed by entering the reference clock (75kHz) for the duration of one
cycle of the input signal into the 20-bit binary counter and measuring the cycle through the
judgment of the pulse count.
This input terminal is also used as the IF input terminal, it is possible to switch across to the
SCIN terminal by setting '1' in the SCON bit.
The Manual bit, the GO bit and the G1 bit are set at 'o' during SCIN setting.
Cycle measurement is started in the same way as the frequency measurement method, and
the calculation data is loaded after the operational status of the BUSY bit has been
confirmed.
(Note) The rectangular waveform must be input to the SClN terminal with the DC coupling at
the logic level.
(Note) Note that the BUSY bit will not become 'o' unless the clock has been input to SCIN.
(4) Timer counter mode
The IF counter may be used as a timer binary counter when it is not in use. The Manual bit,
the G0 bit and the G1 bit are set at 'I' to enable the counter to be used as a 75kHz
reference clock in binary.
This counter is reset whenever the ST/W bit is set at '1'.
(5) Counter division mode
The 20-bit binary counter can also be divided into a 12-bit and an 8-bit binary counter. This
mode is set by setting the Split bit (¢L14) and the Manual bit (¢L15) at '1'. The CTRIN1
terminal is used for input into the 12-bit binary counter, and the CTRIN2 terminal is used for
input into the 8-bit binary counter. Both of these terminals are also used as the P6-2 and P6-3
terminals, so it is necessary to establish the required setting. The data loaded into the 12-bit
counter is the bits between to and f11 (¢K11 to ¢K13) and the data loaded into the 8-bit
counter is the bits between f12 and f19 (¢K14 and ¢K15). These counters are reset when the
STA/S-T? bit for both are set at '1'.
(Note) The rectangular waveform must be input to the CTRIN1 and CTRINZ terminals with the
DC coupling at the logic level.
1997-06-23 42/80
TOSHIBA TC9327F
2. IF counter circuit configuration
CTRIN1 (P6-2) CTRINZ (P6-3)
" ar, f?,
XOUT (75kHz) 'f)afsl,1 K9 OVER
12-bit 8-bit
--er-o-
lFlN/IN1 ISCIN binary counter binary counter OVER
. - Manual
Gate Ime. - GO
control Circwt - G1
Gate clock
STA/ST-P
The IF counter consists of the input amplifier, the gate time control circuit and the 12 +8 bit
binary counter.
The IFIN input amplifier will enter the off mode when the PLL is in the off mode, but counter
operations that do not require the input amplifier may still be carried out.
(Note) The IFIN terminal is equipped with an amplifier, so small amplitude operations are
possible with the condenser coupling.
(lFIN, SCIN) cmmmmmmmmmmr -l-1-l-1-l-1-
Data is set in the STA/STO bit -4;r- -q-i-i-
I I l '
BUSY bit -I-I- -I I l L
Gateclock -rLrLrLrLrLrLrun-1KHz ammmMmmmtmmi-7skHz
Gate _'_!_ |_I
Binarycounterinput _h111mmnm_ -immmm-
Frequency measurement automatic mode Cycle measurement mode
1997-06-23 43/80
TOSHIBA TC9327F
C) LCD driver
¢L2D SI S2 S4 S8
The LCD driver uses the 1/4 duty and 1/2 bias drive method (125Hz frame frequency).
The common output outputs the VLCD, the VLCD/2 (VEE) and the GND electrical potential, and the
segment output outputs the VLCD and GND electrical potential.
A combination of four common outputs and 25 segment outputs enables a maximum of 100
segments to be illuminated.
The S22 to S25 segment output for the LCD driver are also used as the key return output for
loading key matrix data.
The LCD driver is equipped with a constant voltage circuit (VEE =1.55V) for display purposes and a
voltage doubler circuit (VLCD=3.1V) to increase this two-fold, and is a system that prevents contrast
fluctuations in the LCD display even during voltage fluctuations.
It is also possible to switch to the I/O ports in units of one bit between S17 and S25, and this
allows for programming that are perfectly matched to the system.
1. LCD driver port
Y1 Y2 Y4 Y8
Segment dalta selection
Segment-il data Segment-1 data
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L2F COM1 COM2 COM3 COM4 ¢L2E COM1 COM2 COM3 COM4
0 S17 0 SI
1| S18 1l S2
al SIS? al S3
sl S20 - sl s4 -
al S21 al S5
I I I l I I
l l l l l l
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
COM1 COM2 COM3 COM4 COM1 COM2 COM3 COM4
8 S25 F S16
I I I V Y J
Y1 Y2 Y4 Y8 [_- Segment data
F DISP VLCD {1 : illuminated
OFF OFF 0 : extinguished
1997-06-23 44/80
TOSHIBA TC9327F
Y1 Y2 Y4 Y8
¢L3E l/OI l/O2 l/O4 I/O8 (Note) The segment data controls illuminate/
I/O port control selection extinguish for the segments that
t 1 correspond with the common output
and segment output.
(Note) The DISP OFF bit is set at '1' when the
ffL3F Y1 Y2 Y4 Y8 system is reset and when the clock
8 S17 S18 S19 S20 stop mode is cancelled.
9 S21 S22 S23 524]? (Note) The contents of the VLCD OFF bit are
reset at 'o' when the system is reset.
A S25 * * *
* : don't cace
I-SEG l/O control data (1: Segment output, 0: HO port)
{1 : Segment output
0 '. I/O port
The LCD driver control port consists of the segment data selection port and the segment data
port. These ports are accessed with the OUT2 instruction for which [CN=DH-FH] has been
specified in the operand.
The segment data for the LCD driver is set with the segment data ports (¢L2E and ¢L2F). The
LCD display will be extinguished when the segment data port is set at '0' and will be illuminated
when set at '1'. Also, the segment-2 data (¢L2FF) specified with FH in the segment selection port
becomes the DISP OFF bit and the VLCD OFF bit. It is possible to extinguish all LCD displays with
the DISP OFF bit without setting the segment data.
The common output enters a non-selected wave status when this bit is set at '1' and all LCD
displays are extinguished. The contents of the segment is saved at this point, and the LCDs
return to the previous display status when the DISP OFF bit is set at 'o'.
Segment data can be re-written when the DISP OFF status is in effect. The DISP OFF bit will also
be set at '1' after resetting and after the execution of the CKSTP instruction.
SI7-S25 can be switched across to the I/O port, and control for this is performed with the SEG/
IO control ports (¢L3F8 to ¢L3FA). It becomes the segment output port when this port is set at
'1' and the I/O port when set at 'o'. It is necessary to pre-set the I/O port control selection
(¢L3E) in order to access this port.
In addition to this, it is also possible to use an external power source with the VLCD OFF bit.
This is effective when changing over to the crystal drive voltage.
This data is divided and set with the segment data selection port (¢L2D). The S22 to S25
segment output terminals are also used as a key return timing signal for loading key matrix
data. The segment output enters the GND level during key loading with this setting.
1997-06-23 45/80
TOSHIBA TC9327F
2. LCD driver circuit configuration
M N T" O
n: n: tE cc
r rN on v tf E it E
ii ii, ii ii a a 3 'cr,] 5: b) (il' (y, Cf
CP, 0 Ci? Cr, 9 Ci? 0 ----------- ea Cii?, [iii?, 0 Cii8", Citi?,
DISP Common output '
- _ _ z) Segmentdrlver/segmentdata
OFF circuit
SOOHZJ I Ill!
Key return control
:0? i"
circuit
1.5V constant Voltage
voltage circuit doubler circuit
0? OFF .' VLCD OFF signal
0.1/1F
3—0/ 0—1
500m 50(1ng
0.1,UF
0.1/JF
1997-06-23 46/80
TOSHIBA
TC9327F
COMI 5 (Example of output data)
Segment data selection (¢L2D)
5 Y1 2 Y4 Y8
0+COM3 ll 0 0 1 o 1 0
'Fif..R, =' o
Sl COM4 1 1 1 0 1
S2 COM 1 2 3 4
l 8ms l
r—n '—
DISP OFF I :
I - VLCD
COMI J-! ', H
1 Ll U - GND
li-l Cl - VLCD
COM2 ..
11 U Ll - GND
ll Cl Cl - VLCD
COM3 ':
1: Ll IL - GND
cow , Cl Cl - VLCD
ll U - GND
-l,irLrLin_rLi-Lin_rLrL- - VLCD
y, - GND
ll I [ - VLCD
S2 -,i,id LI f_rLrf_FLl
ll I - - GND
-!!"-80ps
- VLCD
S22/KR3
, Lllflj' t Lllfl - - GND
Key data loading
- VLCD
COM1-S1 -
(ON waveform) l I I - GND
- - -ULCD
- - VLCD
COM2-SI - GND
(OFF waveform) I l -
- -VLCD
The electrical potential of the LCD driver waveform outputs VLCD and GND potentials and half
of the intermediate level potential of these potentials. S22-S25 also output key return signals
during the switching. The 'L' level is entered when the segment output is 80ps during key
return data loading.
(Note) The common and segment terminals enter the 'L' level during execution of the CKSTP
instruction and during initialization.
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TOSHIBA TC9327F
C) Key input and key return timing
There are three methods available for loading keys. The correct configuration should be selected for
the system in use.
1. Key control port and key scan data port
Y1 Y2 Y4 Y8
¢L2A KSD1 KSD2 KSD4 KSD8
Key scan data selection /L29
Key scan control port
Y1 Y2 Y4 Y8
(KCO) (KC1) (Kc2) (KC3), .
o DA1 DA2 DA3 VEE -key input level control
1 don't care 1
2 KTO KT1 KT2 KT3" --l/o port-1 key return control
3 KOP K1p K2P K3p‘ Key input pull-down control
4 KOHz K1Hz K2Hz K3Hz -key input high impedance
control
5 don't care l
' F don't care
hen the key is pressed: Data='I'
Key scan data port (t . ' '
Y1 Y2 Y4 Y8 When the key IS not pressed: Data= 0
, K29 K0 K1 K2 K3
1 I KR1
al KR2
sl KR3
The key scan control port is used for setting the input level of the key input, the output format
of HO port-1 (P1-0 to P1-3) and the input format for key input.
The key data for when hardware key scans are performed is input into the key scan data port
(¢K29), and the key data is loaded into the data memory when this port is accessed.
This port is divided by the key scan data selection port (¢L2A), and this enables the ports that
correspond with the data set in this port to be accessed. '1' is added to the data in the key scan
data selection port (¢L2A) whenever the key scan control port (¢L29) and the key scan data port
(¢K29) are accessed.
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TOSHIBA TC9327F
Y1 Y2 Y4 Y8
¢L290 DA1 DA2 DA3 VEE
The bit for switching the key input level's reference power
. . (0: Reference power=V terminal), 1: Reference
Key input level setting power=VEE terminal) DD
"0" : Reference voltage VDD terminal
"I" : Reference voltage VEE terminal
KEY INPUT LEVEL V 1 When the VEE bit
(VKREF) ='1': 1.55 constant voltage (VEE)
When the VEE bit
1/9xV ='0': Mains power voltage applied (VDD)
DA3 DA2
_\_\_\_\oooo
—\—\OO—\—-OO
dC—IO—‘O—‘O
This port is for setting the key input level. The VEE bit enables the reference power to be
switched between the VEE terminal and the mains power voltage (VDD terminal). As indicated in
the table above, the level of the divided reference power with DA bit and the key input
terminal level are compared, and the result of this is output to the key scan data port and the
key input data port.
Y1 Y2 Y4 Y8
¢L292 KTO KT1 KT2 KT3 {o : I/O port
E—’ 1 : Outputs the key return signal with the software
I/O port-1
key return control
Y1 Y2 Y4 Y8
¢L30 P1-0 P1-1 P1-2 P1-3
%—, {0 : 'L' level output
I/O port-1 data _E-' 1 : 'H' level output
The following output format is assumed when '1' is set in the I/O port-1 key return control port,
and the 'H' level and 'L' level setting for this output is controlled by the I/O port-1 data.
I/O port data ---t>o-4
Output circuit when '1' is set in the KTO bit
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TOSHIBA TC9327F
The bits between KTO and KT3 correspond to the terminals between PI-O and P18. These bits
become I/O ports when set at 'o'.
It is necessary to set the bits which correspond to the ports which operate key scanning within
the I/O-1 control port to 'I' (output port, [¢L3F0]) when key scanning is operated from the HO
port-1 key return control port.
Y1 Y2 Y4 Y8
¢L293 KOP K1P K2P K3P {0 .' Key input pulI-down}
%—/ 1 : Ke in t ll-
Key input puII-down settingJ y I pu pu up
Y1 Y2 Y4 Y8
¢L294 KOHz K1Hz K2Hz K3Hz : Key input pull-down or pump -
Er—’ l (c, : Key input high impedance
Key input high impedance setting
These ports are used for setting the input format of the key input. The input format can be set
with the following conditions.
KOHz KOP INPUT FORMAT
0 0 Pull-down
0 1 VEE pull-up
1 0 VDD pull-up
1 1 High impedance
. VEE (1.55V)
Comparison voltage (VKREF) Comparison voltage (VKREF) Comparison voltage (VKREF) Comparison voltage (VKREF)
[Pull-down] [VEE puII-up] [VDD puII-up] [High impedance]
Pull-down is usually set during pull-down setting. PuII-up is only set when fluctuations exist with
the LCD segment output, otherwise high impedance is set.
The key matrix is configured with a combination of the key input terminal and the key return
output signal during pull-down and pull-up setting. This can also be used by the software as a
sequential comparison method 3-bit A/D converter during high impedance setting.
The KOP to K3P bits and KOHz to K3Hz bits correspond with the K0 to K3 terminals.
Execution of the WAIT instruction can be cancelled and CPU operations re-started by applying
the 'H' level (VDDx0.6V or more) to key input terminals set with pull-down when in the wait
mode. The CPU can only be re-started when in the 'H' level, and it should be noted that this
operation is not possible during pull-up and high impedance setting.
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TOSHIBA TC9327F
Y1 Y2 Y4 Y8
/L2D SI S2 S4 S8
Segment data selection
Segment-2 data
Y1 Y2 Y4 Y8
Hardware key
scan on
- Hardware scan enable bit
0 : Scanning with hardware inhibited
('1] : Scanning with hardware enabled. The key
return signal is output when fluctuations
occur in LCD output
The segment output is output with the timing outlined below when the hardware key scan
enable bit is set as '1'. The key return signal is not output when this is set at '0'.
VLCD (3.1V)
Segment output /2hk
[ pr GND
II I I
-t'-r-80ps
" I I v 31v
V LCD(3. )
Segment output AA''"
- Jd t GND
Becomes 'L' level during key return output
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢K27 KR1 KR2 1 1 ¢K28 K0 K1 K2 K3
c-N--"
Key scan operation monitor Key input data
KR2 KR1 Scanning position
0 0 KRO(525)
O 1 KR1 (S24)
1 0 KR2(S23)
1 1 KR3(SZZ)
It is possible to reference the key scan monitor to determine which key line is currently being
loaded when the hardware key scan is in operation.
Data loading during the hardware key scan is performed by accessing the key scan data ports
(¢L290 to ¢K293). On the other hand, each of the key input data port (¢K28) digits are accessed
during software key scans, and the result is loaded into the data memory. The input voltage
becomes 'I' when it is higher than the comparison voltage, and '0' when it is lower.
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TOSHIBA TC9327F
2. Key scan circuit configuration
P1-0~3
KTO-3 Key scan data
K3 K2 K1 K0
P1-3 41 Ci? K0
Output setting circuit
P1-1 Cfs? K1
P1-0 setting
circuit Cie? K2
S25(KRO) Cai K3
S24(KR1) LCD
segment Decoder
S23 (KR2) driver
KOP ~K3P
$22 (KR3) k0Hz- K3Hz
Selector DAI--3
VEE VEE
LCD timing Counter Hardware key scan on
A key input area of the key scan circuit consists of, an input setting circuit, a 3-bit D/A
converter, a comparator and a latch circuit for loading key data. The key return timing output
area consists of an LCD segment driver, a counter and a decoder.
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TOSHIBA TC9327F
3. Key matrix configuration
The key matrix can be configured into the following three styles:
(1) Loading key data with software
P1-0 I I
PI-? data H>o-.
Pl-l I I
P1 2 I I
P1-3 I I
Loading key data
Push key I Diode jumper I
The key matrix outlined above is configured when loading keys from programs. This method
sets the key line I/O port-1 data (¢L30) for which loading is required at the 'H' level and
determines whether the key for loading the key input port data (¢K28) into the data memory
is valid or not. The l/O port-I data for which loading is not required is set at the I' level at
this point. The key input port data becomes 'I' if the key is pressed, 'o' if the key is not
pressed, and the data is loaded into the data memory.
This method can only be used with a 4x4=16 key matrix, but as the key data is loaded at
high speed and high resistance is entered into the P1-0 to PI-? N channel FET areas, it is not
necessary to fit a diode to the I/O for preventing reverse current flows caused by the key
being pressed more than once.
The following data must be set in the relevant ports in order to use the method of loading
data with software.
Comparison voltage
DAI--DA3 VEE HARsth)RoENKEY KT3~KTO KOP~K3P KOHz~K3Hz
Without jumper 4/9 VDD o o All "1" All "0" All "0"
With jumper 3/9 VDD o o All "1" All "0" All "0"
(Note) Set the bits which corresponds with KTO to KT3 at 'o' when the I/O port-1 is to be
used for l/O output.
(Note) The key input voltage applies a low voltage only to the diode's VF (=0.6V) when a
diode jumper is configured. For this reason, the threshold value of the key input is set
at a low value. A diode to prevent reverse current flows caused by pressing the key
more than once is also required, as indicated in the diagram above. This diode is not
required in a diode jumper is not configured into the matrix.
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TOSHIBA TC9327F
By setting the mode in this manner, the execution of the WAIT instruction is cancelled when
the 'H' level (VDDXO.6V or more) is applied during the wait mode, and the CPU re-starts
operations. (The 'H' level does not affect the DA1 to DA3 bit settings at this time.)
(2) Loading key data with LCD segment output
VEE (1.55V)
I,, A + E> g
J V _ %.r
29(KRO)
v 24 KR1
LCD 285 ( )
2 S23 (KR2) To the LCD panel
26 $22 (KR3)
To the key scan data latch
Comparison voltage 35 K1
(Note) Configure of a maximum of 4x4=16 matrix is possible.
(Note) Push keys and diode jumpers cannot be combined in the same key line. Also, the diode
jumper is to be located on the key return signal output.
S25(KRO) zitz"-i'jeiHzitz-ztz-z:e
S24(KRI) zitea-ztz-E4z-E4z-a:r:
S23(KR2) ztzrE4z-E4zu4z-a:r:
S22(KR3) z; I W-Zeer/ya-a:::
ii H ii H (( l'i
Key scan data ii E n !
latch signal ll il,-.,'; ll E E 40/15 JI
Key pull-up
(80pe;)
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TOSHIBA TC9327F
The key matrix outlined in the previous diagram is configured when loading data with LCD
segment output. A diode to prevent reverse current is necessary with this key matrix, and care
must be taken over the direction of the diode and the diode jumper.
With this matrix, the VLCD (3.1V) electrical potential and the GND potential are output from
the segment terminal when fluctuations occur with the LCD output. The segment signal to be
loaded during key data loading becomes the GND potential when fluctuations occur in the
LCD output, and the key input terminal is pulled up to the VEE electrical potential. The VEE
level is input to the key input terminal when the key is not being pressed (or when no
jumper diode exists), and the voltage for one diode (=0.6V) is input from the GND potential
when the key is being pressed (or when a jumper diode does exist).
The electrical potential that has been input is compared with the D/A output level, which is
the VEE electrical potential divided into nine, and the compared signal is latched onto the key
scan data port that corresponds with the key loading segment's output line.
The key data is '1' when a key has been pressed and '0' when a key has not been pressed.
The following data must be set in the relevant ports in order to use the method of loading
data with LCD segment output.
DA1~DA3 VEE "Rsth)RoENKEY KTO--KT3 KOP~K3P KOHz~K3Hz
6/9 VEE 1 1 All "o" All "1" All "o"
The amount of time required for loading one line of key data is 2ms. Owing to this, the key
scan data (¢K29) is loaded into the data memory while referring to the key scan operation
monitor.
(Note) As the diode jumper data is stored within the latch, it is possible to make the most
effective use of data memory space by not loading the data into the data memory,
but referring to the contents of the latch when necessary.
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TOSHIBA
TC9327F
(3) Loading key data with LCD segment output and HG ports
31?; -lyxv-,
To the key
data latch
To the key
data latch
S22 (KR3)
This method utilizes a combination of loading
key data with software and loading key data
with LCD segment output. (Refer to 3-(1), (2))
The main features of this method include the
fact that high-speed key loading can be
performed with the HO ports, and the fact that
the keys can be expanded by distributing the
keys for which high-speed loading is not
necessary to the LCD segment output area.
Key loading is performed by the key input data
port (¢K28) for the HO ports and by the key
scan data port (¢K29) for the segment output.
Key input data port access is performed by
switching across to the key input comparison
voltage.
The settings for this method are as follows:
l/O port settings
KTO KT1 KT2 KT3
1 1 1 1
Key input settings
KOP K1P K2P K3P KOHz K1Hz K2Hz K3Hz
1 1 O 0 0 0 0 0
It is possible to make the settings for both the l/
o ports and the LCD segment output in single bit
units.
(Note) The execution of the WAIT instruction is cancelled when the 'H' level (VDDxO.6 or
more) is applied to the key input terminals for which pull-down has been set (the K2
and K3 terminals in the above diagram) during the wait mode, and the CPU re-starts
operations.
(Note) As the segment key data is loaded when fluctuations occur in the LCD segment, the
threshold value of the key input is different when the I/O port data is loaded
simultaneously and the segment data will be loaded erroneously.
It is therefore necessary to control the situation with the key scan operation monitor.
(Note) Set all contents of the HO port-1 control port (¢L3F0) to '1' (output setting).
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TOSHIBA TC9327F
C) Serial interface
The serial interface is a serial l/O port that synchronizes the internal and external serial clocks and
sends/receives 4-bit and 8-bit data. The data for LSls for expansion purposes, micro-computers and
other elements are sent and received by the SI, so and SCK terminals.
1. The serial interface); control port and data port
Y1 Y2 Y4 Y8 Selection of the HO port-3 and serial interface
¢L22 edge Sik-INV Si-l/tD SIO-ON f,' : I/O port-3 selection (P3-0 to P3-2)
: Serial interface function selection
TCR clock externaI/internal selection
0 : External = clock
{1 : Internal SEK- clock
Inversion of the -gtTd clock signals (only valid when the
internal clock has been selected)
0 : = clock output from the 'H' level
1 : W clock output from the 'L' level
Logical selection of serial data shift operations
0 : Shift at the St-yt rising edge
1 : Shift at the TtTk'" falling edge
Y1 Y2 Y4 Y8 Selection of 4-bit and 8-bit serial data
¢L23 STA 504/6 8/1 bit * o : 4-bit data
1 : 8-bit data
SO terminal SO output and SI input switching
O : SO output
1 : Sl input
Serial operation start and internal port reset
{0 : Don't care
1 : Resets COUNT, SIO and F/F and sets the serial
output data in the shift register. Serial operations
are started when the internal TtIIT clock is selected.
LSB Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 MSB
¢L24 soo SOI $02 $03 ¢L25 $04 $05 $06 SO7
Serial output data: The data set in these ports is output in the serial format
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢K24 SIO Sll SI2 SI3 ¢K25 SI4 SIS SI6 SI7
Serial input data: It is possible to load data input in the serial format into the
data memory
(Note) Serial input data can be accessed by directly accessing the contents of the shift
register.
(Note) The contents of the serial interface control ports (¢L22, ¢L23) will be set at '0' when
the system is reset.
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TOSHIBA TC9327F
Y1 Y2 Y4 Y8 SIO start flag
¢K23 BUSY COUNT SIO F/F 1 0 : SIO operations not performed
1 : SIC) operations performed
TtR clock count judgment bit
0 : Clock count normal (the clock count is in multiples of
1 : Clock count abnormal (the clock count is not in
multiples of four)
SIO operation monitor
0 : SIC) operations ended
1 : SIO operations in progress
Serial interface control and serial data are accessed with the OUT2 and IN2 instructions for
which [CN=2H-5H] has been specified in the operand.
The serial interface terminal is used together with the HO port-3 P3-0, P3-1 and P3-2 terminals,
and each of the I/O port-3 terminals are switched across to the SI, so and WR terminals by
setting 'I' in the SIOON bit.
(1r!rtlTClNV and ?CK-I/O bits
The Sik-lNV and St-yt-l/to bits set the input waveform for the = terminal. The following
modes are set with this bit data.
SCK terminal modes
INV “6 I/O W CLOCK WAVEFORM
0 1 Output lflflj1l
1 1 Output IIIHHI
* 0 Input -
(2) edge bit
The edge bit sets the shift logic for the serial data. This data performs the following data
shifting.
0 When edge = 'o'
STA bit set as '1' -
sc5terrninal l I I I I I I I I I I I I I I I I
I I I I I I I I I
I I I I I I I I I
so 0 eration ii)l soo SOI $02 SO? soo SOI SO2 SO?
A A A d: A
SI operation $10 X $ll X SI2 X s
X Sll X SI2 X Sl?
The so output is output with the rising edge of the WR clock when the edge bit is set at
'ty, and the SI input is input to the shift register with the same rising edge.
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TOSHIBA TC9327F
0 When edge = '1'
STA bit set as '1'
a terminal I I I I I I I I I I I I I I I I
I I I I I I I I
so operation A son X s01 i 502 i 503 a son y) SOI X SO2 ( SO? br"
I I I I I I I
A A A A A A A
Sloperation SIO X sn X Slit X SI3 SIO X sn X Slit X Sl?
The so output is output with the falling edge of the = clock when the edge bit is set
at 'I', and the SI input is input to the shift register with the same falling edge.
(3) 8/T bit
The 8/1 bit selects the length of the serial data. The length of the serial data is set at 4 bits
when this bit is '0', and at 8 bits when this bit is 'I'. The SCK clock outputs four clocks when
4 bits are selected for the internal clock, and eight clocks when 8 bits are selected.
0 When the 8/TI bit is 'o' (however, edge='0' and TtR-lNU='0')
sc-kterminal I I I I I I I I
STA bit set as '1'
so operation iiiid2 f SOI if 502 X 503 f"
Sloperation SIO X t, X S|2 X l,
It When the 8/T bit is '1' (however, edge='0' and =-INV='0')
SF< terminal
Irs" bit set as '1'
so operation ks soo f SOI X SO2 f 503 i; 504 X 505 ii; 506 ii) 507 W
SI operation SIO HX sn xt Sli? xt. SI3 xt SI4 xt SIS xt SI6 xt.
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TOSHIBA TC9327F
(4) SO-I /5 bit
The 504/5 bit sets the serial H5 for the SO terminal.
The so terminal outputs serial data when the SO-I/tj" bit is set at '0', and the SO terminal is
used for serial data input when this bit is set at '1'. The control of this bit enables T-BUS and
other serial bus-type LSIs for performing data l/O with single terminals to be easily
controlled.
sc-kterminal {Illllll l Illililf
l l l l l Floating
so operation X so X SI X S2 , S3 so X SI X S2 X S3
u-v---'
L, set as 'O' 504/6 set as 'I' Data input by the LSI being controlled
(Note) It is necessary to pull up the SO terminal in the case of the above as a certain
timing exists for floating.
This method sets the data in the serial output data port and performs SIC) operations during
sending, and performs SIO operations after the input setting of the SO terminal and loads
the contents of the serial input data port into the data memory during receiving. The SI
terminal can also be controlled as an I/O port (P3-0) when the serial interface has been
selected. The I/O output (P3-0) can be used as the strobe pulse terminal for T-BUS and other
elements.
(Note) The I/O control pores P3-0 bit that corresponds with the I/O port-3 must be set at '0'
during SI terminal serial data input.
(5) Serial interface operation monitor
The operational status of the serial interface is determined by referencing the BUSY, COUNT
and SIO F/F bits.
As the BUSY bit becomes '1' during SIO operations, control data switching and serial data
access is performed when the BUSY bit is 'o'.
The COUNT bit determines if data sending/receiving has been performed in units of 4 bits or
not. This bit outputs 'o' when shift operations are performed in multiples of four, and 'I'
when not performed in multiples of four.
'I' is set in the SIO F/F bit when the ?Cl? terminal commences clock operations.
Both the COUNT bit and SIO F/F bit are reset to 'o' when 'I' is set in the STA bit. These two
bits are mostly used when the TTCR- terminal sets external clocks. Normal operations are
determined to exist when the external clock has been input and serial data has been sent or
received.
(6) STA bit
The serial output data is set in the shift register whenever the STA bit is set at 'I' during the
TtR internal clock setting, the clock is output from the fZR terminal and shift operations are
commenced. The COUNT bit and the SIG F/F bit are simultaneously reset at 'o'.
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TOSHIBA TC9327F
2. Serial interface configuration
SIO F/F COUNT
I I I S_CI<-INv:)D_b "ter'
STA-- Control circuit
48 sc5 (P3-2)
Cle-edge . m SO (P34)
teg" SI (P3-0)
Shift register
Shift Tregister
-l - - _
4 if? 8/4 bit C.'
lsoolsm lsoz (sos I':,:,,,,,",'',,)",,,,,,,,'-, H iriir''2"i'r,iE
IIO port-3 data IIO port-3 IIO control
Sl4 to Sl7
SI0 to Sl3 Serial output data
Serial input data
The serial interface consists of a control circuit, a shift register and an I/O port.
(Note) The SI terminal can be used as the I/O port-3 (P3-0) without modification.
(Note) The data set in the serial output data area and the contents of the serial input data do
not match.
(Note) The SI terminal set up for SI input, the WR terminal set up for TtR input and the SO
terminal set up for input will all follow the Schmidt input method.
3. Serial interface timing
The frequency of the clock output by the SCK terminal when the internal clock is set within the
Sik clock is 37.5kHz (duty 50%).
The following is an example of the timing for the serial interface:
_.I 26.tips F-
SCKterminal l I‘II ld, IBI IAI l I I I
so terminal a soo X SOI X 502 X SO?
SI terminal . a x b x c x
_ g.().__><__
Serial input
data port X
(¢K24) Y x: Not fixed
I t I I
Set as '1' E E Set as 'I'
STA bit -d: ; I A:ty
BUSY bit I
COUNT bit I
SIO F/F I I I
(sci6--1, sciNV=0, edge=0, so//t5=0, 8/7Ibit=0)
Example of serial interface timing
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TOSHIBA TC9327F
C) D/A conversion (pulse-width modulation: PWM) output
The pulse-wide modulation output (PWM) can easily acquire D/A conversion output by the
attachment of a low-pass filter. The PWM output is 12-bit resolution and is equipped with
one-channel output.
PWM control port and data port
Y1 Y2 Y4 Y8 9S L19 Y1 Y2 Y4 Y8 fb L1 A Y1 Y2 Y4 Y8
PWO PW1 PW2 PW3 PW4 PW5 PW6 PW7 PW8 PW9 PW10 PW11
12 2 /
LSB PWM data MSB
Y1 Y2 Y4 Y8
PWM FM Buffer Buffer transfer bit
ON /BUZR transfer
to the PWM data
1 : Transfers the PWM data
I : The PWM output does not change despite amended
PWM data and BUZR data selection
0 : BUZR data selection
1 : PWM data selection
(Note) The internal port for setting the PWM data and
BUZR data is the same. The PWM data or BUZR
data is selected with this bit and the data port is
accessed.
I/O port-4 P4-0 and PWM output selection
{0 : I/O port-4 (P4-0) selection
1 : PWM output selection
The pth/M output is used together with the P4-0 I/O port. P4-0 switches across to the W
output when '1' is set in the pth/M ON bit.
PWM data setting is carried out after the PWM /m bit is set at '1' and the buffer transfer
bit is set at 'ty. The PWM data is transferred to the PWM data latch when the buffer transfer
bit is set at 'I' after PWM data setting. A maximum of 109ms is required after the buffer
transfer bit has been set at 'I'. Owing to this, care must be taken as the ptMM output will
not be changed if this bit is set at 'o' before the data can be sent to the PWM data latch.
PWO is LSB and PW11 is MSB in the PWM data, and the eight high-order bits of data (PW4
to PW11) control the pulse output pulse width and the four Iow-order bits of data (PWO to
PW3) control the position to which the pulse added to one cycle of PWM output is to be
output.
The setting for this data is performed with the OUT1 instruction for which [CN=8H-BH] has
been specified in the operand.
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TOSHIBA TC9327F
2. PWM output circuit configuration
37skHz-/ 12-bit binary counter _ --
PW11 l
PW8 Additional
generation
PW7 PWM circuit
PWM data port to data
PW4 latch - ALL "o"
PW3 i) arator F/F C1 R2
to Clrcwt S R1 Si I
PWO ---- _ 5 tio) PWM Impe D/A
' Matched signal _ output
Latch signal -7icy-,
PWM / BUZR "
Buffer transfer
The PWM output circuit consists of a 12-bit binary counter, a PWM latch, comparator circuit and
other elements.
3. PWM output waveform
TS=6.83ms(TM/16)
I T Pulse width--(n+1)xto n: Data values between PW4 and PW11 (0 to 255)
I I t :
to: 26.7,us
I to-- 2I .7 s Ito
*Pulsewidth nxtol * I I ll
I -d,i-- I I Cir- I I I I
pvr-nrn l l Tri FI ri, Fl Fl: :
TS(15): TS(0) i TS(1) : .Tsa) : ITS(3) i TS(4) i TS(5) l :Tsmzb ll TS(13) l TS(14) l TS(15): TS(0) l
, I . . I .. ' ' I l
" TM=109.2ms(4096/37.5kHz) -.
Example of PWM output timing (Pulse added to TS (4) and TS (12): PW1 bit='1')
PW DATA AREA IN WHICH THE ADDITIQNAL PULSE IS OUTPUT
BITS (C) represents the position to which pulses have been added)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PWO C)
PW1 O C)
PW2 C) C) C) C)
PW3 O C) C) O C) C) C) C)
(Note) The above-mentioned numerals are the i values of TS (i)
Additional pulses are added to the positions marked above with circles
when the PW data bit is set at 'I'.
One cycle of the PWM output waveform is TM=212/37.5kHz= 109.2ms, and a pulse with a
resolution of 12 bits is output. The eight high-order bits between PW4 and PW11 of the PWM
data control the pulse width of the pulse output for the TS (TS=TM/16=6.83ms) cycle. The
Iow-level pulse width for the TS cycle becomes nxto (to=1/37.5kHz) when the value of PW4 to
PW11 is n (n=0 to 255).
The four low-order bits between PWO to PW3 control the position for the output of the to
width's added pulse within the 16 TS (i) areas (i =0 to 15) within the TM cycle. The low-level
pulse width becomes (n +1)xto in the areas to which the additional pulses are output. An
additional pulse is output to the m location within the 16 TS (i) areas when the data for the
Iow-order bit is m (m =0 to 15). The area to which this additional pulse is added is shown in the
above table. (However, the additional pulse will not be output to the TS(0) area.)
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TOSHIBA
C) Buzzer output (BUZR)
TC9327F
The buzzer output can be used to output tones and alarm tones to confirm key operations and the
tuning scan mode. Buzzer types can be selected from a combination of four output modes and
eight different frequencies.
1. Buzzer control port and data port
Y1 Y2 Y4 Y8
BUZR PWM
/ ON /BUZR
Y1 Y2 Y4 Y8
¢L18 BMO BM1
Buzzer output mode data
Y1 Y2 Y4 Y8
¢L19 BFO BF1 BF2 BEN
Buzzer frequency selection data
PWM data and BUZR data selection
d)sTo be set at 'o' prior to setting the BUZR data.
IIO port-3 P3-3 and BUZR output selection
(d : I/O port-3 (P3-3) selection
1 : BUZR output selection
BM1 BMO BUZZER OUTPUT MODE
0 0 Continual output (Mode A)
0 1 Staggered output (Mode B)
1 0 10Hz intermittent output (Mode C)
10Hz intermittent output with 1H2
intervals (Mode D)
- Buzzer output enable bit
0 : Buzzer output fixed at '0'
1 : Buzzer output enabled
BF2 BF1 BFO BUZZER(EEE?UENCY DUTY
0 0 0 0.625 1/2
0 o 1 0.75 1/2
0 1 0 1 2/3
0 1 1 1.25 1/2
1 0 0 1.5 1/2
1 0 1 2.08 2/3
1 1 0 2.5 1/2
1 1 1 3 2/3
Buzzer output is used together with the P3-3 I/O port. 'I' is set in the BUZR ON bit to set buzzer
output. This switches P3-3 across to BUZR output.
Buzzer data setting (output mode, frequency selection and output enabling) is performed after the
PWM/BUZR bit has been set at 'o'.
(Note) The contents of the BMO, BM1, BFO to BF2 and BEN bits are reset at '0' when the system is
reset.
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TOSHIBA TC9327F
2. Buzzer circuit configuration
10Hz 1Hz
Buzzer output control Cai?, BUZR
Buzzer frequency C) Multiplexer
PWM/BUZR
Latch signal V y j
Buzzer data port
3. Buzzer output waveform
ModeA _lllllllllllllllllllllllllllllllllllllllllllllllllllllllNlllllllllllllllllllllll .....
I 50ms I
s'"-'', Period of buzzer frequency output
ModeB I ill “I
I 50ms I
, I Period of I
Mode C " l” non-output ml'm'm'l'l'm l'lrl'Gl'lrl'fll ......
ies0t-'mso,uf'0.0-r'.1s.,i Output status with mode C
I Period of I Period of I
', non-output ' output I
ModeD llllllllllllll mrrrrrrrrrrr llllllllllllll ......
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TOSHIBA TC9327F
C) A/D converter
The A/D converter is used for measuring the strength of electric fields and the voltage of batteries
with 3-channel 6-bit resolution.
1. A/D converter control port and data port
Y1 Y2 Y4 Y8
¢L20 AD AD REF REF
SELO SEL1 SELO SEL1 SEL1SELO DC-REF VOLTAGE
V v Mu I J 0 Applied from the DC-REF terminal
1 VDD (mains power applied voltage)
0 VEE (1.55V constant voltage)
1 Inhibited
- DC-REF selection
—‘—‘OO
AD input selection
SEL1 SELO A/D INPUT
0 0 ADIN1
0 1 ADINZ
1 0 ADIN3
1 1 Inhibited
Y1 Y2 Y4 Y8
¢L21 STA
I A/D converter start bit.
A/D conversion is performed whenever this
bit is set at '1'.
¢K20 Y1 Y2 Y4 Y8 ¢K21 Y1 Y2 Y4 Y8
ADO AD1 AD2 AD3 AD4 ADS BUSY 1
I I . .
LSB A/D conversion data MSB A/D operation monitor
0 : A/D conversion ended
1 : A/D conversion in progress
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TOSHIBA TC9327F
The A/D converter has 6-bit resolution. It is possible to select between external voltage (DC-REF
terminal), mains power voltage (VDD) and 1.55V constant voltage (VEE) for the standard voltage
of A/D conversion. Also, the A/D conversion input follows the external input terminal 3-channel
(terminals ADIN1 to ADIN3) multiplex method.
Under normal circumstances, the standard voltage is set at the external voltage or mains power
voltage, A/D conversion performed on the external input level, and the strength of the
electrical field and volume level measured.
The A/D converter can also carry out measurements on batteries and mains power applied
voltage. The battery signal is output when the battery or mains power applied voltage becomes
low, and control moves across to the back-up mode.
The A/D converter performs A/D conversion whenever the STA bit is set at '1', and this is
ended after seven machine cycles (280ps). A/D conversion completion is determined by
referencing the BUSY bit, and the A/D conversion data is loaded into the data memory after
conversion has finished.
The control for this is access by the OUT2 and lN2 instructions for which [CN=0H, 1H) has been
specified in the operand.
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TOSHIBA TC9327F
2. A/D converter circuit configuration
AD SELO 1
' ' AD
Comparator @ IN1
Sample
+ hold V
- REF Amplifier "', Q ADINZ
SELO-N
ADO A/D, l crvi" ADIN3
A/D d t ort converSIon
a a p Atlgs data latch @
DC-REF
- Control circuit 1.55V constant
R . . Ciii VEE
t I Decoder voltage circuit
STA BUSY
6-bit D IA converter
The A/D converter consists of a 6-bit D/A converter, a comparator, an A/D conversion latch, a
control circuit, an A/D data port, a 1.55V constant voltage circuit (mains power for the LCD
driver) and other elements.
The A/D converter sequentially latches the data A/D converted with the 6-bit sequential
comparison method onto the A/D conversion data latch.
(Note) The DC-REF terminal is built into the amplifier and is a high impedance input.
(Note) Correct data cannot be acquired even when the A/D conversion data is referenced during
A/D conversion. Referencing must be performed after checking with the A/D operation
monitor and confirming that conversion has finished.
(Note) '0' (input setting) must be set in the bit which corresponds with the I/O port-2 control
port (¢L3F1) for the terminals which use A/D input and DC-REF.
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TOSHIBA TC9327F
0 I/O ports
There are 36 I/O ports available between I/O port-1 and HG port-9 which are used to input and
output control signals. Of these 36 HO ports, I/O port-2 is used together with the A/D converter
input, I/O port-3 in used together with the serial interface and buzzer output, I/O port-4 is used
together with the PWM output, I/O port-6 is used together with the counter input, and HG ports
7, 8 and P9-0 are used together with the LCD driver output.
I/O ports 7, 8 and P9-0 are usually used as the LCD driver output.
1. I/O port control and HG port data
Y1 Y2 Y4 Y8
¢L3E l/O1l/O2l/O4l/O8
I/O port control selection
Y1 Y2 Y4 Y8
¢L3F -0 -1-2 -3,, ,
o I/O-1 -
1 I/O-2 "s,
2 1/0-3 ",
"s, -0 -l -2 -3 HO control data
5 l/O-6 rl/O port input/output setting
's, fl : I/O port input
_ 1 : I/O port output
-o -1 -2 -3
B I/O-7
C I/O-8
(Y1) (Y2) (Y4) (Y8)
D I/O-9
-0 -1-2 -3-l/O port number J
¢KL30 I/O-1
¢KL31 l/O-2
¢KL32 l/O-3
0 : I/O terminal 'L' level
fbKL35 l/O-6 FI/O port data{1 : I/O terminal 'H' level
¢KL3B I/O-7
¢KL3C l/O-8
¢KL3D I/O-9 y
¢K3E Ihl2 1 1 1
(Note) The contents of the I/O control data between I/O-1 and KO-ii and the contents of P9-1
to 3 in l/O-9 are set at 'o' (the input port) when the system is reset.
(Note) I/O-1, I/O-2 through to I/O-9 correspond to each of the P1-O to 3, P2-0 to 3 through to
P9-0 to 3 terminals.
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TOSHIBA TC9327F
The input/output for the I/O ports is set with the contents of the HO control data port. 'o' is
set in the I/O control data port bit which corresponds to the relevant port when setting the
input port, and 'I' is set when setting the output port.
The l/O control data port is divided by the HO control selection (¢L3E). The data which
corresponds with the port which is to be set in the I/O control selection is set and the HO
control data port is accessed. 1 is added to the I/O control selection data whenever the I/O
control data port is accessed.
The output status of the HO port is controlled by executing the OUT3 instruction which
corresponds to each I/O port during output port setting. The contents of the data currently
output can also be loaded into the data memory by executing the IN3 instruction.
The data input in the I/O port is loaded into the data memory by executing the lhl3 instruction
which corresponds to each l/O port during input port setting. The contents of the output latch
will have absolutely no effect on the input data at this point.
Input for I/O ports 2 to 5 and 7 to 9 and terminals P6-0, P6-1 and lN2 use the NOR input
structure. The NOR input gate signal (inp-utinst-ructit%) is set at on by executing the lhl3
instruction which corresponds to each l/O port, and the input data is read into the memory. This
enables abnormal mains current consumption to be constrained even when the input electrical
potential reaches the intermediate potential. As the configuration prevents the generation of
abnormal electrical current when these I/O ports are used with N-ch open drain output, low-
potential pull-up is possible with the VDD potential. l/O ports-l, P6-2 and P6-3 are always
impedance input, so the previously-mentioned functions do not apply.
l/O ports 7, 8 and P9-O are used together with the LCD driver output. As these terminals use the
VLCD terminal (step-up voltage) for output power, the 'H' level outputs VLCD potential. Care
must be taken here as the 'H' level has no load capabilities (a load resistance of IMfl or more is
recommended.) Also, the input power uses the VDD terminal power, so other l/O ports can be
used in the same way during input setting.
l/O ports 2 to 4 and 6 are used together with the A/D converter and BUZR output. These ports
are set in the HO port when the system is reset. The l/O port is also set as an input port after
the system has been reset, and the combined LCD driver and HG port terminals are set in the
LCD driver output.
The execution of the WAIT instruction and CKSTP instruction is cancelled and CPU operations are
re-started when the status of the HO port input specified in the input port changes with NO
port-1. Also, the MUTE port and MUTE bit are forcibly set to '1' during changes in the input
status when the MUTE pores l/O bit is set at '1'.
(Note) I/O port input/output setting and the I/O port data will be set at 'don't care' during
LCD driver setting with the combined LCD driver and I/O port terminals.
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TOSHIBA TC9327F
C) Register port
The G-register and data register outlined in the explanation on the CPU are also used as a single
internal port.
1. G-register (¢L1F)
This register addresses the data memory's row addresses (DR=4H to FH) during execution of the
MVGD instruction and MVGS instruction. This register is accessed with the OUT1 instruction for
which [CN=FH] has been specified in the operand.
(Note) The contents of this register are only valid when the MVGD instruction and MVGS
instruction are executed and are ineffective when any other instruction is executed.
Y1 Y2 Y4 Y8
¢L1F #o #1 #2 #3 #3 #2 #1 #0 DR
Data memo)yrt,wLdr-esiecification 0 1 0 0 4H
0 1 o 1 5H
0 1 1 0 6H
, S I i i
1 1 1 0 EH
1 1 1 1 FH
(Note) All of the data memory row addresses can be specified indirectly by
setting data OH to FH in the G-register. (DR=0H to FH)
2. Data registers (¢K1C to ¢K1F)
16-bit registers which load the program memory data when the DAL instruction is executed.
The contents of this register are loaded into the data memory in 4-bit units with the execution
of the lNI instruction for which [CN=CH to FH] has been specified in the operand.
This register can be used for loading LCD segment decoding operations, radio band edge data
and the data related to binary to BCD conversion.
Y8 Y4 Y2 Y1 -- -
d d d d d d d d d d d d d d d d
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fblf1F ¢K1E ¢K1D fbKIC
MSB Program memory 16-bit data LSB
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TOSHIBA TC9327F
C) Timer and CPU stop functions
The timer is equipped with 1OOHz, 10Hz and 2H2 F/F bits and is used for counting clock operations
and the tuning scan mode, etc.
The CPU stop function suspends CPU operations with the voltage detection circuit when the applied
VDD voltage falls to 1.55V or below in order to prevent CPU malfunctions.
1. Timer port and STOP F/F bits
. Set at '1' when VDD
Reset port MI I falls to 1.55v or below
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
F/F Timer F/F 10Hz 100Hz F/F
I I i l i I
u-v---'
The 2H2 F/F, the STOP F/F, the 10Hz and the 100Hz are reset whenever 'I' is set.
The timer port and STOP F/F bits are accessed with the OUT2 and IN2 instructions for which
[CN=6H] has been specified in the operand.
2. Timer port timing
The 2Hz timer F/F is set with the 2H2 (500ms) signal and is reset by setting '1' in the reset
port's 2H2 F/F. This bit is usually used as a clock counter.
The 2Hz timer F/F can only be reset with the reset port's 2Hz F/F, and incorrect counts will be
output and correct times not acquired if not reset within a 500ms cycle.
2Hz timer F/F output t<500ms
2Hz F/F reset execution
2Hz clock
The 10H2 and 100Hz timers are output to 10Hz and 100Hz bits with respective cycles of 100ms
and 10ms and a pulse of duty 50%. Counters at 1kHz or below will be reset whenever the reset
pores timer bit is set at '1'.
10Hz 50ms I I I
100Hz 5ms I I I
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TOSHIBA TC9327F
3. CPU stop function and STOP F/F bit
The STOP F/F bit is set at '1' and CPU operations suspended if the applied VDD voltage falls
below 1.55V in order to prevent CPU malfunctions. The CPU program counter and the execution
of instructions are suspended when a voltage of 1.55V or below is applied to the VDD terminal.
CPU operations are re-started when a voltage of 1.55V or higher is applied to the VDD terminal.
Abnormalities will occur with clocks during this period of non-operations. In this event, the
situation will be determined by the contents of the STOP F/F, and initialization and clock
correction will be performed if necessary.
The STOP F/F bit will be reset to '0' whenever the reset port's 2H2 F/F is set at '1'.
2Hz F/F I
reset execution V I "
STOP F/F I
(Note) The contents of the timer port and STOP F/F will be reset at 'o' when the
system is reset and when the CKSTP instruction is executed.
(Note) The CKSTOP mode cannot be executed during clock stop mode setting if the
voltage applied to the VDD is 1.55V or below, so care must be taken over the
mains power voltage timing when setting the radio off and similar operations.
(Note) The CPU stop function will be inhibited when all of the internal test port
(¢L1C) bits between #0 and #3 are set at '1'.
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TOSHIBA TC9327F
C) MUTE output
This is a dedicated 1-bit CMOS output port for muting control purposes.
1. MUTE port
Y1 Y2 Y4 Y8
¢L16 MUTE I/O POL UNLOCK
L Phase difference output selection for phase comparator
0 : Phase difference not output
1 : Phase difference output
MUTE output polarity control
0 : Positive logic: MUTE bit output without modification
1 : Negative logic: MUTE bit inversed and output
(Note) Phase difference output is controlled
simultaneously
Control selection by changes in the I/O port-1 input status
0 : MUTE output not amended when changes in NO
( port-1 input status exist
1 : MUTE bit set at 'I' when changes in l/O port-1
input status exist
MUTE output setting
{0 : MUTE output set at I' level during positive logic
and 'H' level during negative logic
1 : MUTE output set at 'H' level during positive logic
and 'L' level during negative logic
This port is accessed with the OUT1 instruction for which [CN=6H] has been specified in the
operand. MUTE output is used for muting control. A function to set the MUTE bit at '1' during
band switching with I/O port-1 input is also available.
This function prevents noise from being generated during linear circuit switching when band
switching is performed with the HO port-1 input for slide switches. Control for this function is
performed with the contents of the I/O bit.
The POL bit sets the logic for MUTE output.
MUTE output can also control muting with the use of the phase difference output. The PLL
element is output as a pulse when the lock status is not in effect (in the unlock status). A low-
pass filter is attached to the MUTE output in this event, and the output is used for MUTE
output. This can be selected with the UNLOCK bit.
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TOSHIBA TC9327F
2. MUTE output configuration and timing
'H' level
High impedance
POL bit DO output I I I " , . . Lk ........ l
II II, I
T L' level
MUTE bit JD "di MUTE Phase difference J-Lr'rl-rlu"'''-e'rl-
UNLOCK bit I-rr':-':-
l/O bit 3%
UNLOCK bit I I
MUTE bit I l l
Phase comparator’s I I I
I/O port-l input phase difference MUTE output -1 -1 H h
change signal
_ Phase difference input
(Note) When the POL bit='0'.
(Note) A low-pass filter must be attached to the MUTE output when the phase
comparator's phase difference output is used.
C) Test port
An internal port for testing device functions. Access is performed with the OUT1 instruction for
which [CN=CH] has been specified in the operand, and the OUT2 instruction for which [CN=6H]
has been specified in the operand. 'o' is usually set with the program.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L1C #0 #1 #2 #3 ¢L26 #4 #5 ¢L2FF #6
Test port Test port Test port
Bit #6 of the test port can suspend the LCD driver output internal frame signal. Suspension of the
frame signal outputs all segment output as segment data inversed output. Segment output will
usually enter the I' level when all segment data bits between COM1 and COM4 are set to '1', and
usually enters the 'H' level when all bits are set to '0'. This can be used as a simple output port in
systems which do not use LCD output. External mains power is to be set with the VLCD OFF bit
and a connection established between the VDD terminal and VLCD terminal in this case.
The CPU stop function is inhibited when all test port bits between #0 and #3 are set at '1' and
enabled when set at '0'. The CPU stop function must be inhibited when external mains power
voltage detection is to be performed.
(Note) The contents of bits #4 to #6 are reset to '0' and bits #0 to #3 are set to '1' when the
system is reset.
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TOSHIBA TC9327F
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD - 0.3--4.0 V
Input Voltage VIN -0.r-VDD+0.3 V
Power Dissipation PD 100 mW
Operating Temperature Topr -10--60 "C
Storage Temperature Tstg - 55--125 "C
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Ta =25°C, VDD=3.0V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
Range Of Operating
V - * 1. ' .
Supply Voltage DD ( ) 8 3 6 V
Range Of Memory V Crystal oscillation stopped 1 0 -- 3 6
Retention Voltage HD (CKSTP instruction executed) (*) . .
Under ordinary operation
No output load VDD=3.0V - 7.0 12
I FMIN =230MHz input A
DD1 - Under ordinary operation m
No output load VDD=3.0V - 6.0 10
FMIN = 130MHz input
Operating Current Under CPU operation only
I - . V = . V - 1
DD2 (PLL off, display turned on) DD 3 0 50 00
Soft Wait mode
IDD3 - (Crystal oscillator, display circuit - 30 60 A
operating, CPU stopped, PLL off) p
Hard Wait mode
IDD4 - (crystal oscillator operating only) - 20 40
Memory Retention I Crystal oscillation stopped 0 1 10
Current HD - (CKSTP instruction executed) - .
Crystal Oscillation *
- - 7 -
Frequency fXT ( ) 5 kHz
Crystal oscillation t Cr stal oscillation f =75kHz 1 o s
Start-up Time ST y XT-- .
VOLTAGE DOUBLER CIRCUIT
Voltage Doubler
Reference Voltage VEE - GND reference (VEE) 1.35 1.55 1.75 V
Constant Voltage
Temperature DV - GND reference (VEE) - -5 - mV/°C
Characteristics
Voltage Doubler
Boosting Voltage VLCD - GND reference (VLCD) 2.7 3.1 3.5 V
For conditions marked by an asterisk (*), guaranteed when VDD-- 1.8 to 3.6V, Ta = - 10 to 60°C
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TOSHIBA TC9327F
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
OPERATING FREQUENCY RANGES FOR PROGRAMMABLE COUNTER AND LF COUNTER
Sine wave input when ViN=0.3Vp-p (*)
FMIN (VHF Mode) fVHF - Sine wave input when 1/iN=0.21/p-p, 50 - 230
VDD =1.8--3.0V, Ta = -10--60oc
FMIN (FM Mode) fFM - Sine wave input when V|N=0.2p-p (*) 40 -- 130 MHz
AMIN (HF Mode) fHF - Sine wave input when 1/iN=0.2p-p (*) 1 -- 45
AMIN (LF Mode) fu: - Sine wave input when V|N=0.2p_p (*) 0.5 -- 12
IFIN hr: - Sine wave input when VIN =0.2p-p (*) 0.35 -- 12
FMlN input ( ) 0.3 -0.8
. (VHF mode) VDD--1.8--3.0V, VDD
Input Amplitude VIN - Ta= - 10 to 60°C 0.2 -0.8 Vp-p
FMIN(FM mode), AMIN, IFIN input (*) 0.2 -- 1’33
LCD COMMON OUTPUT/SEGMENT OUTPUT, GENERAL-PURPOSE I/O PORTS
(COM 1 to COM4, S1 to S16, S17/P7-0 to S25/P9-0, P9-1 to 3, IN2)
Output "H" Level IOH'I - VLCD=3VI VOH =2.7V -0.4 -0.8 - mA
Current "L" Level 'OL1 - VLCD=3V, V0L=0.3V 0.4 0.8 - mA
Output Voltage 1/2 v35 - No load 1.35 1.55 1.75 v
VIH=VDD, VIL=0V +
Input Leak Current 'LI (when using I/O port, IN port) .10 #A
" " . VDD ~
Input H Level VIH1 - (when usmg I/O port, IN port) x0.6 VDD V
Voltage "L" Level 1/IL1 - (when using I/O port, IN port) 0 - Re,
I/O PORT (P1-0 to P1-3)
Output "H" Level 10m - VOH=2.7V -0.4 -0.8 - mA
Current "L" Level IOU - V0L=0.3V 0.4 0.8 - mA
VIH =3.0V, 1hL=0V +
Input Leak Current 'LI (when using I/O port) -+1.0 PA
Input "H" Level VIH2 - (When using l/O port) 2.4 -- 3.0 V
Voltage "L" Level 1/IL2 - (When using I/O port) 0 -- 0.6
. VOL=3.OV
N ch Load Resistance RON - (When connected to load resistance) 50 100 200 kn
For conditions marked by an asterisk (*), guaranteed when VDD-- 1.8 to 3.6V, Ta = - 10 to 60°C
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TOSHIBA TC9327F
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
HOLD INPUT PORT
Input Leak Current ILI - V|H=3.0V, lhL=0V - - i 1.0 PA
Input "H" Level 1/IH3 - - 2.4 - 3.0 V
Voltage "L" Level l/ILS - - 0 ' 1.2
A/D CONVERTER (ADIN1 to ADIN3, DC-REF)
Analog Input
Voltage Range VAD - ADIN1 ADIN3 0 VDD V
Analog Reference VDD
V - D-REFV =2.~.V 1. - V
Voltage Range REF C ' DD 0 3.6 0 x0.9
Resolution VRES - - - 6 - bit
Conversion Total - - VDD=2.0--3.6V - 11.0 14.0 LSB
V = . V V = V
Analog Input Leak 'LI - (AglNiEADIILI: 'IU, - - 11.0 PA
KEY INPUT PORT (K0 to K3)
Key Input Voltage
V - - 0 - V V
Range KI DD
A/D Conversion .
Resolution VRES - - - 3 - bit
A/D Conversion VDD=1.8--2.0V - - i1.5 LSB
Total Error - VDD=2.0--3.6V - - 10.5
Mb /P-ch Input RIN1 - - 50 100 200 kn
Resistance
Input "H" Level VIH4 - When releasing WAIT instruction 1.8 ' 3.0 V
Voltage "L" Level VIL4 - When releasing WAIT instruction 0 -- 0.3 V
. . . ff V = . V
Input Leak Current ILI - afiunpl‘t resistance IS o ' IH 3 O ' - - 11.0 PA
DO1/OT2, D02 OUTPUT, MUTE, 0T1 OUTPUT
Output "H" Level IOH1 - VOH =2.7V -0.4 -0.8 - mA
Current "L" Level 'OL1 - V0L=0.3V 0.4 0.8 -
Output Off Leak
- = . = - - i1 A
Current ITL VTLH 3 ov, VTLL 0V(DOI, DO2) 00 n
For conditions marked by an asterisk (*), guaranteed when VDD=1.8 to 3.6V, Ta = - 10 to 60°C
1997-06-23 78/80
TOSHIBA TC9327F
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
GENERAL-PURPOSE I/O PORT (P2-0 to P6-3)
Output "H" Level IOH1 - V0H=2.7V -0.4 -0.8 - mA
Current "L" Level 'OL1 - VOL=0.3V 0.4 0.8 -
Input Leak Current ILI - VIH =3.0V, lhL=0V - - i 1.0 #A
Input "H" Level 1/IH2 - - 2.4 ' 3.0 V
Voltage "L" Level Vle - - 0 - 0.6
IN1/SCIN, RESET INPUT PORT
Input Leak Current 'LI - .VIH =3.OV, 1hL=01/ (excluding SCIN - - -+1.0 PA
input)
Input "H" Level VIH2 - - 2.4 -- 3.0 V
Voltage "L" Level VIL2 - - 0 - 0.6
OTHERS
Input Pull-down
Resistance RIN2 - (TEST) 15 30 60 k0
XIN Amp. Feedback
Resistance RfXT - (XIN XOUT) - 20 - Mn
XOUT Output
Resistance ROUT (XOUT) 4 k0
Input Amp. Feedback RfIN1 - (FMIN, AMIN) 150 300 600 k0
Resistance RfIN2 - (IFIN / SC|N) 500 1000 2000
Voltage Drop
Detection Voltage VSTP - (VDD) 1.35 1.55 1.75 V
Voltage Drop
Detection Ds - (VDD) - -3 - mV/°C
Temperature Property
For conditions marked by an asterisk (*), guaranteed when VDD-- 1.8 to 3.6V, Ta = - 10 to 60°C
1997-06-23 79/80
TOSHIBA TC9327F
OUTLINE DRAWING
LQFP80-P-1212-0.50A
1 4.0i0.2
12.0i0.2
1 .25TYP
14.0:02
0.1 P-.-..
" 1 3.0:t0.2 $5.?
Weight : 0.45g (Typ.)
1997-06-23 80/80
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