TC9318FB Fast Delivery |IC PHOENIX CO.,LIMITED

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TC9318FB
SINGLE CHIP DTS MICROCONTROLLER (DTS-21)
TOSHIBA TC9318FA/FB
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC931l 8FA, TC931 8FB
SINGLE CHIP DTS MICROCONTROLLER (DTS-21)
The TC9318FA and TC9318FB are a 4bit CMOS TC9318FA
microcontroller for signal chip digital tuning systems. It is
capable of functioning at a low voltage of 3V and
features a built-in prescaler of operating 230MHz, PLL
and LCD drivers.
The CPU has 4bit parallel addition and subtraction
instructions (e.g., Al, SI), logic operation instructions (e.g.,
OR, AND), composite judging and compare instructions
(e.g., TM, SL), and time-base functions.
The package is an pin 64, 0.5/0.65-mm-pitch quad flat
pack package. In addition to various input/output ports LQFP64-P-1010-0.50
and a dedicated key-input port, which are controlled by TC9318FB
powerful input/output instructions (IN 1, 2, OUT 1, 2),
there are many dedicated LCD pins, a buzzer port, a 6bit
A/D converter, an IF counter, and other pins.
Low-voltage and Iow-current consumption make this
microcontroller suitable for portable DTS equipment.
FEATURES
0 4bit microcontroller for digital tuning systems.
0 Operating voltage VDD=1.8~3.6V, with low current QFP64-P-1212-th65
consumption because of CMOS circuitry (with only CPU Weight .
operating, when VDD=3V, lDD=80/rA Max.) lf#,ttyily2tf.lii'so , 8.31:3 Egg;
0 Built-in prescaler (1 /2 fixed divider +2 modulus prescaler : fmax2 230MHz)
0 Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3V booster circuit for the display.
It Data memory (RAM) and ports are easily backed up.
0 Program memory (ROM): 16bitx4096 steps
0 Data memory (RAM) : 4bitx256 words
It 62-instruction set (all one-word instructions)
0 Instruction execution time : 40ps (with 75kHz crystal) (MVGS, DAL instructions : 80ps)
0 Many addition and subtraction instructions (12 types addition, 12 types subtraction)
It Powerful composite judging instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN)
0 Data can be transmitted between addresses on the same row. (MVSR instruction)
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TOSHIBA TC9318FA/FB
0 Register indirect transfer available (MVGD, MVGS instruction).
0 16 powerful general registers (located in RAM)
0 Stack levels : 2
o JUMP or CAL instruction can be used anywhere in the 4096 steps of program memory (ROM) as
there are no pages or fields.
0 16bit of any address in the 1024 steps in program memory (ROM) can be referenced (DAL
instruction).
o Features independent frequency input pins (FMIN and AMIN) and two (DOI and D02) phase
comparison outputs for FM/VHF and AM.
It Seven reference frequencies can be selected by program.
It Powerful input/output instructions (IN 1, 2, OUT 1, 2)
0 Dedicated input ports (ktr-k3) for key input. 26 LCD drive pins (69 segments maximum) available.
0 17 I/O ports .' 10 with input/output programmable in 1bit units, and 7 output-only port. The 2
IFIN, and DO1 pins can be switched by instruction to IN (input-only) or OT (output-only).
0 Three back-up modes available by instruction : only CPU operation, crystal oscillation only, clock
It Features a built-in 2Hz timer HF and a built-in 10/100Hz interval pulse output (internal port for
time base).
0 Allows PLL lock status detection.
It 8 of the LCD segment outputs (Slir-S23) can also operate as key return timing outputs (KR0-KR7).
The I/O ports are not dedicated key return timing outputs but can have other uses as well.
0 Built-in 20bit, general-purpose f counter can detect stations during auto-tuning by counting the
intermediate frequencies of each band.
0 Built-in 8bit buzzer output circuit can produce 254 different tone signals.
0 Features a built-in 2-channel, 6bit A/D converter.
It To prevent CPU malfunctions, a built-in supply voltage drop detection circuit shuts down the CPU
when voltage falls below 1.5V.
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TOSHIBA TC9318FA/FB
PIN CONNECTION
Output A/D Converter
| P3-1(BUZR)—
| P2-3(DC—REF)
I P2-2(AD|N2)
I P2—1(AD|N1)
b-,L-"
| P3-O
| P2-0
| P1-3
| P1-2
| P‘I-1
| P1—0
Radio ON/OFF o-- HOLD I/O Port Key Return T1
Timing
IF Signal -H-lFIN/lhl Output Port= T0
Phase - DO1/OT K3
Comparison
Output -- DO2 Keylnput K2
_- GND K1
Local ---o- FMIN K0
Oscillator
Signal _ AMIN $23/KR0
Battery 0*: VDD (TOP VIEW) S22/KR1
75kH RESET $21/KR2
Z Key Return
"gi-'' OUT Timing S20/KR3
it-u-ear- NN Output Port S19/KR4
it-n- VXT S13/KR5
Q-o- VLCD S17/KR6
C1 S15/KR7
l'_ C2 515
ir-o- VEE LCD Driver (3x23=69max. SEGMENT) S14
iii'g?lrJrJ'?cfiy?l/'/2/g'tg'fj-'i--.C).t-'
VT V3 V3 Mt
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TOSHIBA
BLOCK DIAGRAM
FIN/IIN
IFIN/IN
500 Z 10Hz
CPU Timing Gene. 2Hz F/F
Reference Divider MPX / La.
1kHZ PLL OFF
4bit Swallow
1/15, 16 Counter/La.
20bit IF Counter
DATA BUS
CODE BUS
COLUMN
(16 x 4096 Step)
Instruction
Prog. Counter
Stack Reg. (2 Level)
VL VEE
500H COM
500HZ KEY SCAN
TIMING GENE.
Segment Driver/La. EY Data La
S15/KR
$17/KR
S18/KR5
Szg/KR
TC9318FA/FB
UNLOCK F/F
Phase Com.
SIG OT La.
MUTE Cont.
12bit Programmable
Counter/La.
8bit BUZR
(4 x 256 word)
R/W Buf
6bit AID
STOP RES
Doubler
Circuit
Lu Pus-
LIJ UU
DO1/OT
P3-1 IBUZR
P2-3 /DC-REF
P2-2 /ADIN2
P2-1 /AD|N1
2001 -06-1 9
TOSHIBA
EXPLANATION OF FUNCTION
TC9318FA/FB
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
LCD common
output
Output common signals to the LCD
panel. Through a matrix with pins
Sr-sp, a maximum of 69 segments can
be displayed.
Three levels, l/LCD, VEE, and GND, are
output at 83Hz every 2ms.
VEE is output after SYSTEM RESET and
CLOCK STOP are released, and a common
signal is output after the DISP OFF bit is
set to "o".
sr-SIS
LCD segment
output
S15/KR7
$23 / KRO
LCD segment
output/ Key
return timing
output
Segment signal output pins for the LCD
panel. Together with COM1, COM2, and
COM3, a matrix is formed that can
display a maximum of 69 segments.
The signals for the key matrix and the
segment signals from pins S15/KR7~523/
KRO are output on a time division basis.
4x8=32 key matrix can be created in
conjunction with key input ports K0--K3.
Key input ports
4bit input ports for key matrix input.
Combined in a matrix with key return
timing outputs of the LCD segment pins,
data from a maximum of 4x8=32 keys
can be input and pins are pulled up. On
the key seteutining output pins, data
from 4x6=24 keys can be input and
pins are pulled down. The WAIT mode is
released when high level is applied to
key input ports set to pull-down.
Ttr-Ts
Key return
timing output
These ports output the timing signal for
key matrix. To form the key matrix, load
resistance has been built-in the N-channel
side. When the key matrix combined
with push-key, that does not need a key
matrix diode.
I/O port1
The input and output of these 4bit I/O
ports can be programmed in 1bit units.
By altering the input to I/O ports set to
input, the CLOCK STOP and WAIT modes
can be released, and the MUTE bit of
the MUTE pin can be set to "I''.
''-] i
2001 -06-1 9
TOSHIBA
TC9318FA/FB
PIN No. SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
P2-1 /
41 ~44 P2-2/
DC-REF
I/O port2
/AD analog
voltage input
/AD analog
voltage input
/Reference
voltage input
4bit I/O ports.
Input and output may be programmed in
1bit units.
Pins P2-1 through P2-2 can also be used
for analog input to the built-in 6bit, 2-
channel A/D converter.
Conversion time of the built-in A/D
converter using the successive comparison
method is 280ps. The necessary pin can
be programmed to AD analog input in
1bit units, and P2-3 can be set to the
reference voltage input. Internal power
supply (VDD) or constant voltage (VEE)
can be used as the reference voltage. In
addition, constant voltage (VEE) can be
input to the AD analog input so battery
voltage, etc., can be easily detected. The
reference voltage input, for which a
built-in operational amp is used, has high
impedance.
The A/D converter, and their control are
all executed by program.
- To A/D converter
(P2-0 pin is excluded)
45--46 P3-1 /
l/O port3
/Buzzer output
2bit l/O ports, whose input/output can
be programmed in 1bit units.
The P3-1 pin also functions as the output
for the built-in buzzer circuit. The buzzer
sound can be output in 254 different
tones between 18.75kHz and 147Hz, and
at a duty of 50%.
The buzzer output, and all associated
controls can be programmed.
47 MUTE
Mutiny output
1bit output port. Normally, this port is
used for muting control signal output.
This pin can set the internal MUTE bit to
"I" according to a change in the input
of I/O port 1. MUTE bit output logic can
be changed ; PLL phase difference can
also be output using this pin.
48 TEST
TEST mode
control input
Input pin used for controlling TEST
mode. High level indicates TEST mode,
while low level indicates normal
operation. The pin is normally used at
low level or no-connection (NC). (A pull-
down resistor is built-in).
2001 -06-1 9
TOSHIBA
TC9318FA/FB
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
HOLD mode
control input
Input pin for request/release HOLD
Normally, this pin is used to input radio
mode selection signals or battery
detection signals.
HOLD mode includes CLOCK STOP mode
(stops crystal oscillation) and WAIT mode
(halts CPU). Setting is implemented with
the CKSTP instruction or the WAIT
instruction. When the CKSTP instruction is
executed, request/release of the HOLD
mode depends on the internal MODE bit.
If the MODE bit is "0" (MODE-O),
executing the CKSTP instruction while the
HOLD pin is at low level stops the clock
generator and the CPU and changes to
memory back-up mode. If the MODE bit
is "1" (MODE-1), executing the CKSTP
instruction enters memory back-up mode
regardless of the level of the HOLD pin.
Memory back-up is released when the
HOLD pin goes high in MODE-O, or when
the level of the HOLD pin level in
MODE-1.
When memory back-up mode is entered
by executing a WAIT instruction, any
change in the HOLD pin input releases
the mode.
In memory back-up mode, current
consumption is low (below 10PA), and all
the output pins (e.g., display output,
output ports) are automatically set to
low level.
IFlN/IN
IF signal input/
Input port
IF counter's IF signal input pin for
counting the IF signals of the FM and
AM bands and detecting the automatic
stop position.
The input frequency is between
o.35~12MHz (0.2up-p (Min)). A built-in
input amp and C coupling allow
operation at Iow-level input.
The IF counter is a 20bit counter with
optional gate times of 1, 4, 16, and
64ms. 20 bits of data can be readily
stored in memory.
This input pin can be programmed for
use as an input port (IN port). CMOS
input is used when the pin is set as an
IN port.
2001 -06-1 9
TOSHIBA
TC9318FA/FB
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
DO1/OT
comparison
output
/Output port
comparison
output
PLL's phase comparison tri-state output
When the programmable counter's
prescaler output is higher than the
reference frequency, output is at high
level. When output is lower than the
reference frequency, output is at low
level. When output equals the reference
frequency, high impedance output is
obtained.
Because DOI and D02 are output in
parallel, optimal filter constants can be
designed for the FM/VHF and AM bands.
Pin DO1 can be programmed to high
impedance or programmed as an output
port (OT). Thus, the pins can be used to
improve Iock-up time or used as output
ports.
Power-supply
Pins to which power is applied.
Normally, VDD--1.8--3.6V (3.0V Typ.) is
applied.
In back-up mode (when CKSTP
instructions are being executed), voltage
can be lowered to 1.0V. If voltage falls
below 1.5V while the CPU is operating,
the CPU stops to prevent malfunction
(STOP mode). When the voltage rises
above 1.5V, the CPU restarts.
STOP mode can be detected by checking
the STOP F/F bit. If necessary, execute
initialization or adjust clock by program.
When detecting or preventing CPU
malfunctions using an external circuit,
STOP mode can be invalidated and
rendered non-operative by program. In
that case, all four bits of the internal
TEST port should be set to "I".
If more than 1.8V is applied when the
pin voltage is 0, the device's system is
reset and the program starts from
address "o". (Power on reset)
(Note) To operate the power on reset,
the power supply should start up
in 10~100ms.
2001 -06-1 9
TOSHIBA
TC9318FA/FB
PIN No. SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
54 FMIN
programmable
counter input
Programmable counter input pin for FM,
VHF band.
The 1/2 +pulse swallow system (VHF
mode) and the pulse swallow system (FM
mode) are selectable freely by program.
At the VHF mode, local oscillation output
(VCO output) of 50~230MH2 (0.2kap
(Min)) is input and FM mode,
40~130MH2 (0.2Vp-p (Min)) is input.
A built-in input amp and C coupling
allow operation at low-level input.
(Note) When in the PLL OFF mode or
when set to AMIN input, the
input is pulled down.
55 AMIN
AM local
oscillator signal
Programmable counter input pin for AM
The pulse swallow system (HF mode) and
direct dividing system (LF mode) are
freely selectable by program. At the HF
mode, local oscillation output (VCO
output) of 1--45MHz (thill/p-p (Min)) is
input and LF mode, 0.5--12MHz (0.2Up-p
(Min)) is input.
Built-in input amp operates with low-
level input using a C coupling.
(Note) When in PLL OFF mode or when
set to FMIN input, the input is
pulled down.
57 RESET
Reset input
Input pin for system reset signals.
FSET takes place while at low level , at
high level, the program starts from
address "0".
Normally, if more than 1.8V is supplied
to VDD when the voltage is 0, the
system is reset (Power on reset).
Accordingly, this pin should be set to
high level during operation.
58 XOUT
59 XIN
60 VXT
Crystal
oscillator pins
Crystal oscillator pins.
A reference 75kHz crystal oscillator is
connected to the XIN and XOUT pins.
The oscillator stops oscillating during
CKSTP instruction execution.
The VXT pin is the power supply for the
crystal oscillator. A stabilizing capacitor
(0.47/1F Typ.) is connected.
2001 -06-1 9
TOSHIBA TC9318FA/FB
PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
Voltage doubler boosting pin for driving
the LCD.
61 VLCD A capacitor (0.1PF Typ.) is connected to
boost the voltage.
The VLCD pin outputs voltage (3.0V),
which has been doubled from the
constant voltage (VEE : 1.5V) using the
Voltage . v
62 C1 doubler capacitors cen.n.ected between C1 and C2. , LCD
boosting pin That potential IS supplied to the LCD
drivers. If the internal VLCD OFF bit is set
to "I" by program, an external power
supply can be input through the VLCD
pin to drive the LCD.
63 C2 At this time, the VLCD/2 potential,
whose VLCD voltage is divided using
registers, is output from the C2 pin.
1.5V constant voltage supply pin for
Constant ffsvti2ilitzh1"cl),acito, (0.1/1F Typ.) is
64 VEE veltage supply connected. This is a reference voltage for -
pin the A/D converter, key input, and the
LCD common output's bias potential.
(Note 1) When the device is reset (voltage higher than 1.8V, or when "kTffi?T--low-9high)
I/O ports are set to input, the pins for I/O ports and additional functions (e.g.,
A/D converter) are set to l/O port input pins, while the lFlN/IN pins become IF
input pins.
(Note 2) When in PLL OFF mode (when the three bits in the internal reference ports all
show "1"), the IFIN and FMIN, AMIN pins are pulled down, and DOI and D02 are
at high impedance.
(Note 3) When in CLOCK STOP mode (during execution of CKSTP instruction), the output
ports and the LCD output pins are all at low level, while the constant voltage
circuit (VEE), the voltage doubler circuit (l/LCD), and the power supply for the
crystal oscillator (VXT) are all off.
(Note 4) When the device is being reset, the contents of the output ports and internal
ports are undefined and initialization by program is necessary.
2001 -06-1 9
TOSHIBA TC9318FA/FB
EXPLANATION OF OPERATION
CD CPU
CPU is composed of program counter, stack register, ALU, program memory, data memory, G-
register, carry F/F and judging circuit.
Program counter (PC)
Program Counter is a block to designate the address of program memory (ROM), and is
composed of 12 bits binary up counter. This is cleared by system reset, and the program starts
from zero address.
Usually, it's increment is made one by one everytime the one instruction is executed, but when
JUMP instruction or CAL instruction is executed, the address designated at operand part of that
instruction is loaded.
Further, when the instruction (AIS, SLTI, TMT, RNS instructions, etc.) having skip function is
executed, two increments of program counter is made if the result is the condition to be
skipped, and the succeeding instruction is skipped.
MSB LSB
PC PC1 1 PC10 PC9 PC8 PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO
. Stack register (STACK)
This is a register composed of 2x12 bits during the execution of subroutine call instruction, the
value obtained by adding +1 to the content of program counter, namely return address, is
housed. The content of stack register is loaded on the program counter by the execution of
return instruction. (RN, RNS instructions)
This stack level is 2 level, and nesting is 2 level.
ALU has binary 4 bits parallel addition and subtraction, logical operation, comparison and plural
bit judge functions.
This CPU has no accumulator, and all operations directly treat the contents of data memory.
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TOSHIBA TC9318FA/FB
4. Program memory (ROM)
Program memory is composed of 16bitx4096 steps and is the address of 000H--FFTH.
Program memory has no concept of page or field, so JUMP instruction and CAL instruction can
be freely used among 4096 steps.
Further, it is possible to use optional address of program memory as data area, and its content,
16 bits, can be loaded to the data register by executing DAL instruction.
(Note 1) Provide the data area at the address outside the program loop in the program
memory.
(Note 2) In DAL instruction, the address of program memory can be designated as the data
area becomes 1024 steps of 000H--3FFH.
FFFH 000H
ROM 16bitx4096 steps
4096 steps
5. Data memory (RAM)
Data memory is composed of 4bitx256 words and used for storing data.
This 256 words are expressed with row address (4 bits) and column address (4 bits).
192 words (row address=4H-FH) among the data memory are indirect addressing by G-register.
For this reason, when carrying out data processing within this territory, it is necessary to
designate row address by G-register beforehand Area of 00H~0FH address in data memory is
called general register, and can be used only by designating column address (4 bits). These 16
general registers can be used for operation and transfer between data memories. Further, it can
also be used as ordinary data memory.
(Note) The column address (4 bits) to designate general register becomes register number of
the general register.
(Note) It is also possible to indirectly designate all of row address (=0H--FH) by G-register.
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TOSHIBA TC9318FA/FB
Column Address : Dc
0123456789ABCDEF
(*):_’
g l 0 General register
i,,' l 1 (One of 00H--OFH address)
13; l 2
Indirectly designate 8
row address (4H-FH) 9
by G-register.
(*) Indirect designation A
of row address (OH-FH) B
is also possible
RAM (4bitx256 words)
6. G-register (G-REG.)
G-register is a 4 bits register for addressing row address (DR=4H--FH) of 192 words in data
memory.
Content of this register is effective during executing MVGD instruction, MVGS instruction, and is
not related with the execution of other instructions.
This register is treated as one of the port, and its content is set by the execution of OUT1
instruction among input and output instructions.
(refer to register port item 1)
7. Data register (DATA REG.)
This is a register composed of 1x16 bits. In this register, 16 bits data of optional address among
the program memory in 000H~3FFH is loaded during executing of DAL instruction. This register
is treated as one of the port, and when IN1 instruction among input and output instruction is
executed, it's content is read in the data memory in 4 bits unit.
(refer to register port item 2)
8. Carry F/F (CF/F)
This is set when carry or borrow is produced as a result of executing operational instruction, and
is reset when it is not produced. Content of carry F/F changes only when addition and
subtraction instruction is executed, and does not change during the execution of other
instructions.
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TOSHIBA
TC9318FA/FB
9. Judging circuit (J)
When a instruction with skip function is executed, this circuit judges it's skip condition. When
skip condition is satisfied, this circuit makes two increments of program counter, and skips the
succeeding instruction.
It is provided with 29 kinds of instructions having abundant skip function.
(refer to Item 11, explanation list of function and operation of instructions, .2( marked
instruction)
10.List of instruction set
60 kinds of instruction set are included, all of which consisting of one word instruction.
These instructions are expressed with 6 bits instruction code.
Higher Rank 00 01 IO 11
Lower 2 bits
Rank 4 bits 0 1 2 3
0000 0 Al M, I AD r, M TMTR r, M SLTI M, I
0001 1 AIS M, I ADS r, M TMFR r, M SGEI M, I
0010 2 AIN M, I ADN r, M SEQ r, M SEQI M, I
0011 3 AIC M, I AC r, M SNE r, M SNEI M, I
0100 4 AICS M, I ACS r, M LD r, M TMTN M, N
0101 5 AICN M, I ACN r, M ST M, r TMT M, N
0110 6 ORIM M, I ORR r, M MVGD r, M TMFN M, N
0111 7 ANIM M, I ANDR r, M MVGS M, r TMF M, N
1000 8 SI M, I su r, M IN1 M, c
1001 9 SIS M, I sus r, M IN2 M, c
1010 A SIN M, I SUN r, M CALL ADDR1 -
1011 B SIB M, I SB r, M OUT1 c, M
1100 c SIBS M, I SBS r, M OUT2 c, M
1101 D SIBN M,I SBN r, M -
1110 E XORI M, I XORR r, M JUMP ADDR1 DAL ADDR2, r
RN, RNS, WAIT
1111 F MVIM M, I MVSR M1, M2 CKSTP, NOOP
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TOSHIBA
TC9318FA/FB
11.Explanation list of function and operation of instructions (Explanation of symbols)
lN1--lhl2
OUT1--OUT2
: Data memory address
Normally, one of 00H--3FH address of data memory.
: General register
One of 00H~0FH address of data memory.
: Program counter (12bit)
: Stack register (12bit)
: G-register (4bit)
: Data register (16bit)
: Immediate data (4bit)
: Bit position (4bit)
: All "0"
: Code No. of port (4bit)
.' Code No. of port (4bit)
: General register No. (4bit)
: Program memory address in page 0 or 1 (12bit)
: Higher rank 6bit of program memory address in page 0
: Carry
: Borrow
: Port treated during the execution of lhl1-lN2 instruction
: Port treated during the execution of OUT1--OUT2 instruction
: Register or data memory content
: Content of port indicated by code No. C (4bit)
: Content of data memory indicated by the content of register or data memory
.' Content of program memory (16bit)
.' Instruction code (6bit)
: Instruction having skip function
: Data memory column address (4bit)
: Data memory row address (2bit)
: Wait condition
15 2001-06-19
TOSHIBA TC9318FA/FB
. 9 MACHINE LANGUAGE (16bit)
r- F- EXPLANATION OF EXPLANATION OF
21:” MNEMONIC E; FUNCTION OPERATION IC A B c
if, E (6bit) (2bit) (4bit) (4bit)
Al M, Add immediate data Me-(M) +1 000000 DR Dc I
to memory
Add immediate data
AIS M, .2(. to memory, then skip M<._(.M) M 000001 DR Dc I
. Skip if carry
if carry
Add immediate data
AIN M, X to memory, then skip 'le-tm N 000010 DR DC I
. Skip if not carry
if not carry
AIC M, Add immediate data Me-ON/l) +l+ca 000011 DR DC I
to memory with carry
Add immediate data
o AICS M, .2(. to memory with carry, [rt-ry) +I+ca 000100 DR Dc I
- . . Skip if carry
r- then skip if carry
Add immediate data
ttd AICN M, Fd. to memory with carry, 'le-tm +l+ca 000101 DR Dc I
F- . . Skip if not carry
W then skip if not carry
E Add memory to
a AD r, M general register re-fr) + (M) 010000 DR Dc RN
- Add memory to
l ADS r, M .2(. general register, then rfr.(r). + (M) 010001 DR DC RN
CI . . Skip if carry
0 skip if carry
< Add memory to
ADN r, M Fd. general register, then rf.-.ir). + (M) 010010 DR Dc RN
. . Skip if not carry
skip if not carry
Add memory to
AC r, M general register with re-ir) + (M) +ca 010011 DR Dc RN
Add memory to
ty. general register with re-ir) + (M) +ca
ACS r, M X carry, then skip if Skip if carry 010100 DR DC RN
Add memory to
.w. general register with re-ir) + (M) +ca
ACN r, M X carry, then skip if not Skip if not carry 010101 DR DC RN
16 2001-06-19
TOSHIBA
TC9318FA/FB
. 9 MACHINE LANGUAGE (16bit)
r- F- EXPLANATION OF EXPLANATION OF
2 n: MONIC E g FUNCTION OPERATION IC A B c
if, E (6bit) (2bit) (4bit) (4bit)
Subtract immediate
SI M, I data from memory Me-(M) -l 001000 DR DC I
Subtract immediate
SIS M, I X data from memory, yt-ly). -l 001001 DR Dc I
. . Skip if borrow
then skip if borrow
Subtract immediate
tw". data from memory, Me-iM) -l
SIN M, I yd. then skip if not Skip if not borrow 001010 DR DC I
borrow
Subtract immediate
SIB M, I data from memory Me-(M) -l-b 001011 DR DC I
a with borrow
9 Subtract immediate
I- .w. data from memory Ms-iM) -l-b
g SIBS M, I yd. with borrow, then Skip if borrow 001100 DR DC I
ff skip if borrow
'dl Subtract immediate
- .w. data from memory Mt-iM) -l-b
a SIBN M, I X with borrow, then Skip if not borrow 001101 DR DC I
0 skip if not borrow
1: Subtract memory from -
'd su r, M general register re-ir) (M) 011000 DR Dc RN
ttd Subtract memory from
m SUS r, M .yd. general register, then rfr.(r). (M) 011001 DR Dc RN
:3 . . Skip if borrow
V, skip if borrow
Subtract memory from
SUN r, M .2(. general register, then rfr.(r). (M) 011010 DR Dc RN
. . Skip if not borrow
skip if not borrow
Subtract memory from
SB r, M general register with re-ir) - (M) -b 011011 DR DC RN
borrow
Subtract memory from
.w. general register with re-ir) - (M) -b
SBS r, M X borrow, then skip if Skip if borrow 011100 DR DC RN
borrow
Subtract memory from
Fd. general register with re-ir) - (M) -b
SBN r, M borrow, then skip if Skip if not borrow 011101 DR DC RN
not borrow
17 2001-06-19
TOSHIBA
TC9318FA/FB
. 9 MACHINE LANGUAGE (16bit)
'- F- EXPLANATION OF EXPLANATION OF
Ile MNEMONIC E 'sl FUNCTION OPERATION IC A B c
if, E (6bit) (2bit) (4bit) (4bit)
. Skip if memory is less . .
SLTI M, I X than immediate data Skip if(M) a . . .
0 Skip if memory IS
F- SGEI M, I X greater than or equal Skip if(M) 2| 110001 DR Dc I
g to immediate data
0: Skip if memory is
F- . . . . .
m SEQI M, I yd. equal to immediate Skip if(M) =l 110010 DR Dc I
E data
a Skip if memory is not
a SNEI M, I X equal to immediate Skip if(M) #l 110011 DR Dc I
- data
a: . .
< Skip if general
E SEQ r, M X register is equal to Skip if(r) = (M) 100010 DR Dc RN
8 memory
Skip if general
SNE r, M yd. register is not equal Skip if(r) = (M) 100011 DR DC RN
to memory
Load memory to
g LD r, M general register re-(M) 100100 DR Dc RN
F- ST M, r Store general register Me-ir) 100101 DR DC RN
u to memory
a Move memory to
t MVSR M1, M2 memory in the same (DR, DC1)e-(DR, DC2) 011111 DR DCI DC2
a: MVIM M, I Move immediate data Me-l 001111 DR DC I
'd to memory
2 Move memory to
< destination memory
E MVGD r, M referring to G-register [(G),(r)le-(M) 100110 DR DC RN
and general register
Move source memory
referring to G-register
MVGS M, r and general register Ms-fits),))] 100111 DR DC RN
to memory
18 2001-06-19
TOSHIBA
TC9318FA/FB
. 9 MACHINE LANGUAGE (16bit)
r- 1- EXPLANATION OF EXPLANATION OF
2 ar' MNEMONIC E see' FUNCTION OPERATION IC A B c
if, E (6bit) (2bit) (4bit) (4bit)
Input lN1 port data
'iei5 INI M, C to memory Me-FI]: 111000 DR Dc CN
o - Output contents of
mg OUT1 c, M memory to mm port [OUT11ce-(M) 111011 DR DC CN
215 In ut lN2 ort data
Cr, IN2 M, C p p Me-oat:: 111001 DR DC CN
SE to memory
CL Output contents of
- OUT2 c, M memory to OUT2 port [OUT21ce-(M) 111100 DR DC CN
Logical OR of general
ORR r, M register and memory r_-(r)V(h/l) 010110 DR DC RN
Logical AND of
a ANDR r, M general register and re-(r)/N(hh) 010111 DR Dc RN
9 memory
"Z Lo . I OR f
<0 glca o memory
3.: ORIM M, I and immediate data Me-(M)VI 000110 DR DC I
tLU) Logical AND of
n: ANIM M, I memory and Mt- (M)N 000111 DR Dc I
tl; immediate data
SE Logical exclusive OR
g XORIM M, I of memory and Mt- (M) Ol 001110 DR DC I
.1 immediate data
Logical exclusive OR
XORR r, M of general register re-ir) C) (M) 011110 DR DC RN
and memory
a Test general register
C) tw". bits by memory bits, Skip if r[N(M)]
F- TMTR r, M X then skip if all bits =all "1" 100000 DR DC RN
g specified are true
ff Test general register
m tw". bits by memory bits, Skip if r[N(M)]
E TMFR r, M X then skip if all bits =all "0" 100001 DR DC RN
LLI specified are false
g Test memory bits,
P, TMT M, N .)k. then skip if all bits Skip if M (N) =all "I" 110101 DR Dc N
I- specified are true
- Test memory bits,
on TMF M, N X then skip if all bits Skip if M (N) =all "o" 110111 DR DC N
specified are false
19 2001-06-19
TOSHIBA
TC9318FA/FB
. 9 MACHINE LANGUAGE (16bit)
r- l- EXPLANATION OF EXPLANATION OF
. MNEM NI
Ile 0 C E E FUNCTION OPERATION IC A B c
if, E (6bit) (2bit) (4bit) (4bit)
Test memory bits . .
Lu 2 I
39 TMTN M, N .yd. then not skip if all Skip if M(“Pnot all "I" 110100 DR Dc N
D t bits specified are true -
-, D .
tE Test memory bits, . .
le, TMFN M, N >:< then not skip if all Skip if M (“Pnot all "o" 110110 DR DC N
m E bits specified are false -
. STACK-(PC) +1 and .
:3 CALL ADDR1 Call subroutine PCe-ADDRI 1010 ADDR1(12blt)
tt RN Rem?" to mam PG-(STACK) 111111 00 - -
OD routine
2215 Return to main
3% RNS .2(. routine and skip PCe-(STACK)and skip 111111 01 - -
- unconditionally
tL Jump to the address
E F- .
32 JUMP ADDR1 specified PG-ADDR, 1011 ADDR1 (12bit)
Load program DATAe-[ADDR + (r)]
DAL ADDR2, r memory in page 0 to in a e 0 2 P 111110 RN
g DATA register p g
F- At P="0" H, the
g condition is CPU
E waiting (Soft wait
m mode) . . .
E WAIT P At P="1" H, except Wait at condition P 111111 10 0000
m for clock generator,
w all function is waiting
t (Hard wait mode)
Stop clock generator
111111 1 1 -
CKSTP Clock generator stop at MODE condition 0 000
NOOP No operation - 111111 11 - -
(Note 1) Among 10 bits of the program memory address assigned by DAL instruction, the
lower rank of 4 bits become indirect addressing based on the content of general
register.
DAL instruction executing time is 80ps (2 machine cycles).
(Note 2) MVGS instruction executing time is 80ps (2 machine cycles).
2001 -06-1 9
TOSHIBA TC9318FA/FB
C) HO map
All ports in the device are expressed by matrix of four input and output instruction (OUT1--2
instructions, 1N1--2 instructions) and 4 bits of code No.C. Assignment of these ports is indicated
previously as I/O map. In the HO map, port names treated in the execution of each input and
output instruction are assigned horizontally, while code No. of port are assigned vertically. G-
register and data register are also treated as port.
The OUT1--2 instructions are assigned to output port, and Ihl1--2 instructions are assigned to input
(Note 1) The port indicated with oblique line on I/O map is a port not existing in the device. In
the execution of output instruction, when data is output to the non-existing output port,
no effect is given to the content of other port or data memory. When non-existing input
port is designated during the execution of input instruction, the content read into the
data memory becomes "I".
(Note 2) Among the output ports on l/O map, .24 marked port is unused port. The data output
here becomes "don't care".
(Note 3) Regarding the content of port expressed in 4 bits, Y1 corresponds to the least significant
of the data of data memory, and Y8 to the most significant bit.
Each port assigned by four input and output instruction and code No. C is coded as
follows :
¢i£/_len
?Contents of het selected port
(Indirectly specified data, 0~F[HEX])
4 kinds of input and output instruction are described in No. I--2
Inputand putput OUT1 OUT2 IN1 IN2
Instruction
m 1 2 1 2
Expresses input/output port (K : input port, L : output port)
K : input port (|N1~|N2 instructions)
L : output port (OUT1--OUT2 instructions)
(Example) The G-register is set by OUT1 instruction wite code 'T".
Therefore, the notation is "¢L1F".
21 2001-06-19
TC9318FA/FB
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2001 -06-1 9
TOSHIBA TC9318FA/FB
C) Connecting crystal oscillator
The following diagram shows the connection of the 75kHz crystal oscillator to the device's crystal
oscillator pins (XIN, XOUT).
The oscillation signal is supplied to the clock generator, reference frequency divider, and other sub-
systems to generate the various CPU timing signals, reference frequency, and other signals. The
power supply for the crystal oscillator circuit is the voltage (VXT= 1.4V Typ.) supplied by the built-in
constant voltage circuit. This stabilizes the crystal oscillation and reduces the current consumption.
' (XOUTHXIN) (er)
' Q9 ty) 58 59 so '
CL CL CX X'tal = 75kHz
J J CL=15pF Typ. CX--th47PF Typ.
(Note) Use a crystal oscillator with a low CI value and with good startup characteristics.
C) System reset
The system is reset when a low level is applied to the Rt-st-T pin, or when the voltage supplied to
the VDD pin goes from 0V to 1.8V or more (a power on reset). Following a system reset, the
program starts from address 0 after a standby period of 100ms.
As the power on reset function is typically used, fix the 'k"""ir"frt't"' pin to the high level.
(Note 1) During a system reset and during the standby period following the reset, the LCD
common and segment outputs are fixed at the low level.
(Note 2) After a system reset, the internal ports shown in the following table are fixed at the
specified levels. The states of the other ports after a reset are undefined. Therefore,
initialize the ports in the program when necessary.
Fixed internal ports
PORTS SET TO "0" PORTS SET TO "1"
MANUAL bit (¢L17) REFERENCE PORT (¢L15)
IO, POL, UNLOCK bit (¢L18) MUTE bit (¢L18)
DOI CONTROL PORT (¢L19) IF/m bit (¢L16)
BUZR ON bit (¢L1E) DISP OFF bit (¢L2FF)
TEST PORT (¢L1A, ¢L1D)
CKSTP MODE bit (¢L1E)
AD CONTROL PORT (¢L20, ¢L21)
TIMER PORT (¢K1A)
KEY RETURN SELECT bit (¢L2FF)
IO-r-IO-? IO CONTROL PORT (¢L25~¢L27)
23 2001-06-19
TOSHIBA TC9318FA/FB
0 Backup modes
To enter the three backup modes, execute the CKSTP or WAIT instruction.
1. Clock stop mode
Clock stop mode halts the system and maintains the internal state of the system immediately
prior to halting. During a halt, the system is maintained with low current consumption (IOpA or
below, at VDD=3.0V). In clock stop mode, the crystal oscillator halts and the output ports and
LCD display output pins are all automatically set to the low level or the off state. The supply
voltage can be reduced to 1.0V.
When the CKSTP instruction is executed, execution halts at the address of the CKSTP instruction.
Therefore, execution starts again from the next instruction when clock stop mode is released
(after a standby period of around 100ms).
(1) Setting clock stop mode
Clock stop mode can be set to one of two modes. The CKSTP bit determines which of the
two modes is set. Use the OUT2 instruction with the operand [CN=7H] to access this bit.
Y1 Y2 Y4 Y8
¢L27 CKSTP
t 0 : MODE-O
CKSTP Mode Settings
1 : MODE-1
C) MODE-O
In mode 0, executing the CKSTP instruction when the HOLD pin is low enters clock
stop mode. Executing the CKSTP instruction when the HOLD pin is high is equivalent
to executing a NOOP instruction.
© MODE-1
In mode 1, executing the CKSTP instruction enters clock stop mode regardless of the
level of the HOLD pin.
(Note) The PLL turns off during execution of the CKSTP instruction.
(2) Releasing clock stop mode
co MODE-O
In mode 0, clock stop mode is released when the HOLD pin goes to high, or by a
change in the input state of any l/O port 1 pin (P1-O~P1-3) set as an input port.
© MODE-1
In mode 1, clock stop mode is released by a change in the input state of the HOLD
pin or in the input state of any I/O port 1 pin (PI-tr-PI-S) set as an input port.
24 2001-06-19
TOSHIBA TC9318FA/FB
(3) Clock stop mode timing
co MODE-O
HOLD Pin ' ll /
CPU Operation -,'-T- I Clock Stop c'-, Standby l CPU Operation
(Clock stop mode release)
CKSTP Instruction K R, ll k
NOOP Operation CKSTP Instruction Execution NOOP Operation
(Executing the CKSTP instruction while the HOLD pin input is low sets the device
to clock stop mode.)
© MODE-1
HOLD Pin " , n
XOUT Pin lllllllllllllll] ll _i-ii7Frrn,pt,,l,lFm,,cTock
l I CPU Clock Stop
CPU Operation - Clock Stop - Standby -T"- -
I ' Operation
A " n A
It, (Clock stop mode released by input change)
CKSTP Instruction
(Executing the CKSTP instruction always sets the device to clock stop mode.)
(4) Circuit example (MODE-O)
L< POWER
_ POWER
Example of backup circuit using battery Example of backup circuit using capacitor
25 2001-06-19
TOSHIBA TC9318FA/FB
2. Wait mode
Wait mode halts the system and maintains, with reduced current consumption, the internal state
of the system immediately prior to halting. Two wait modes are available : "soft wait" and
"hard wait". When the WAIT instruction is executed, execution halts at the address of the WAIT
instruction. Therefore, when wait mode is released, execution starts again from the next
instruction without delaying for the standby time.
(1) Soft wait mode
Executing the WAIT instruction with the operand [P=0H] stops only the CPU inside the
device. In this mode, the crystal oscillator, display circuit, and other circuitry continue to
operate normally. Using soft wait mode in the program for clock functions reduces the
current consumed during clock operation.
(Note) The current consumption depends on the program.
(2) Hard wait mode
Executing the WAIT instruction with the operand [P= 1H] stops all operation other than
the crystal oscillator. This reduces current consumption still further than soft wait mode. In
this state, the CPU and display circuits are halted, and the LCD display output pins are all
automatically fixed at the low level. (15PA Typ. at VDD=3V)
(3) Setting wait mode
Executing the WAIT instruction always sets wait mode.
(Note) In hard wait mode, the PLL turns off, while in soft wait mode, the PLL does not
turn off. Accordingly, before setting a soft wait, turn the PLL off by software.
(4) Wait mode release conditions
Wait mode is released by the following conditions.
At a change in the input state of the HOLD pin
When a high level is input to a key input pin (K0--K3)
(Note : Depends on the key input mode)
When the 2Hz timer flip-flop is set to 1". (In soft wait mode only)
At a change in the input state of an I/O-1 port (P1-0~P1-3) set as an input port
3. HOLD input port
Y1 Y2 Y4 Y8
ffK1i1 HOLD
The HO-LD pin can be used as an input port. Executing the IN1 instruction with the operand
[CN =BH] reads the data input from this bit to data memory.
When setting clock stop mode, always access this port prior to executing the CKSTP instruction.
Note that if the CKSTP instruction is executed without first accessing this port, the device may
not enter clock stop mode.
26 2001-06-19
TOSHIBA TC9318FA/FB
C) Programmable counter
The programmable counter block consists of a 2-modulus prescaler, 4bit and 13bit programmable
counters, and the ports used to control the block.
The programmable counters can be turned on and off by the contents of the reference ports.
1. Programmable counter control ports
These ports control the divisor, division method, and the IF correction (IF offset) for the FM
Y1 Y2 Y4 Y8
¢L10 HF +1 -1 FM
l u-v--' i
T Offset
Division Method Setting
Programmable Counter Data
(LSB) Y1 Y2 Y4 Y8
P0 P1 P2 P3
ffl-12 P4 P5 P6 P7
¢L13 P8 P9 P10 P11
¢L14 P12 P13 P14 P15
fbL15 REFERENCE SELECT P16 (MSB)
Access the division method and the IF offset using the OUT1 instruction with the operand
[CN=0H]. Access the divisor settings using the OUT1 instruction with the operands [CN=1H~5H].
Set the divisor by writing to bits P0~P16. When the programmable counter data (P16) is set, all
the data from P0 to P16 are updated. Therefore, always access P16 to set the data, even when
changing only a portion of the data.
And the reference frequency is set at the same time.
27 2001-06-19
TOSHIBA
2. Setting division method
The HF and FM bits select the pulse swallow or direct division method.
As the following table shows, there are four methods. Select the appropriate method in
accordance with the frequency band used.
TC9318FA/FB
MODE HF FM DIVISION METHOD REEESWSKE $110 FRE§JE§€V§§NGE "Ir)? Dl)d'feo)"
LF 0 0 Direct division method MW/LW 0.5-12MHz AM
HF 1 0 (1/15 or1/16) sw 1.0-45MHz IN n
FM 0 1 Pulse swallow method FM 40~130MH2
VHF 1 1 1/2x(1/150r1/16) VHF 50~230MH2 FMIN 2n
Pulse swallow method
(Note) n indicates the programmed divisor.
3. IF correction function for FM band
When the pulse swallow method is selected, the A|Fi1 ports allow the actual divisor to be
varied by Il without changing the programmed divisor. This can be used for IF offset in FM.
When the direct division method is selected, the IF offset function does not operate.
dlF-rl dlF-1 34:13:) (Ae'ngHF)
0 0 Tn n
0 1 2. (n - 1) n -1
1 0 2. (n + 1) n +1
1 1 Prohibited Prohibited
2001 -06-1 9
TOSHIBA TC9318FA/FB
4. Setting divisor
Set the divisor of the programmable counter as a binary value in bits P0~P16.
0 Pulse swallow method (17 bits)
MSB LSB
P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Divisor setting range (pulse swallow method) n=210H-1FFFFH (528-131071)
It Direct division method (13 bits)
MSB LSB
P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 sr" /P//%
212 20 u Y J
Divisor setting range (direct division method) n=10H--1FFFH (16--8191) don't care
(Note1) In case of direct dividing mode, Psr-P3(iL11)data be comes unrelated and P4
port becomes LSB.
(Note2) In VHF mode, the divisor is double the programmed divisor.
5. Programmable counter circuit structure
It Pulse swallow method circuit structure
The programmable counter circuit is made up of a 1/15 or 1/16 2-modulus prescaler, a 4bit
swallow counter, and a 13bit binary programmable counter. In FMH mode, a 1/2 divider is
inserted before the prescaler.
' ('ijj',3, J
" 16 Swallow Counter
"Nr-oz,
i/i Preset
FMIN o-sri-Ci-, C', 15 16
I; 13bit To Phase Comparator
Programmable Counter
P4--P16
AMIN 65
29 2001-06-19
TOSHIBA TC9318FA/FB
It Direct division method circuit structure
This circuit bypasses the prescaler and uses the 13bit programmable counter.
Preset
AIVIIN CsisD 13bit Proarammable Counter
- To Phase Comparator
(Note) The FMIN and AMIN pins incorporate amps. Connecting a capacitor permits low-
amplitude operation. The input pins not selected by the division method are
pulled down. In PLL off mode (set by the reference port), the inputs are also
pulled down.
O Reference frequency divider
The reference frequency divider divides the frequency of the external 75kHz crystal oscillator to
generate seven PLL reference frequency signals : 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 12.5kHz, and
25kHz. The frequency signal is selected by the reference port data.
The selected signal is supplied as the reference frequency for the phase comparator, which is
described next. The PLL is turned on or off by the reference port setting.
1. Reference select port
The reference port is an internal port used to select the reference frequency signal (from the
seven frequencies). Use the OUT1 instruction with the operand [CN=5H] (¢L15) to access this
port. When the contents of the reference port are all "I", the programmable counter, IF
counter, and reference counter are halted, and the PLL is turned off.
when The reference port are set, the frequency division data of the programmable counter are
updated. Therefore, in case of setting reference port, it is neccesary to set the frequency division
data of the programmable counter.
Y1 Y2 Y4 Y8
¢L15 R0 R1 R2
a_l R2 R1 R0 FRREEFSEENEEK
Reference Frequency Select Code 0 0 0 0 1kHz
I 0 0 1 1 3kHz
0 1 0 2 3.125kHz
0 1 1 3 SkHz
1 0 0 4 6.25kHz
1 0 1 5 12.5kHz
1 1 0 6 25kHz
1 1 1 7 PLLOFF MODE
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TOSHIBA
TC9318FA/FB
C) Phase comparator, Clock detection port
The phase comparator compares the reference frequency signal supplied by the reference frequency
divider with the divided signal output by the programmable counter, and outputs the phase
difference. The output of the phase comparator is used to control the VCO via the low pass filter
so as to eliminate the frequency and phase difference between the two signals.
Data are output from the phase comparator to the tristate buffered DOI and D02 pins in parallel.
This enables the optimal filter constants to be designed for both FM and AM bands.
Also, the DO1 pin can be set for general-purpose output by the DOI control port. The DO1 pin can
also be set to high impedance. By using the DOI and D02 pins, PLL loop characteristics, such as the
lockup time, can be improved.
The lock detection port can be used to detect the PLL lock state.
1. D02 control port, Unlock detection port
Y1 Y2 Y4 Y8
UNLOCK D02 Control
RESET OTC OT Hz
0 : DO1 phase difference output
- Set DO1 output to high impedance
1 : DO1 high impedance
0 : OT output low
- OT output data bit .
1 : OT output high
(Note) Invalid when Hz set to 1
0 : DO1 phase difference output
- OT output control bit
1 : OT data output
(Note) Invalid when Hz set to 1
Setting "1" resets the unlock flip-flop bit and unlock enable bit.
Y1 Y2 Y4 Y8
¢K17 UNLOCK
F/F ENABLE
1 : PLL unlock detect enabled
- Unlock enable bit
0 : PLL unlock detect wait state
1 .' PLL unlocked
Unlock detect bit
0 : PLL locked
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TOSHIBA TC9318FA/FB
The OTC, OT, and Hz control bits of the DOI control port set the DOI output pin as a general-
purpose output port, and control whether DOI goes to high impedance instead of outputting
the phase difference. Set these bits to the required values by program.
When the phase is approximately 180°, the unlock flip-flop bit detects the phase difference
between the divided output of the programmable counter and the reference frequency. If the
phase difference does not match, that is, if the PLL is unlocked, the unlock flip-flop is set. Also,
setting the unlock reset bit to "1" resets the unlock flip-flop.
To detect the phase difference during the reference voltage period, reset the unlock flip-flop,
then access the unlock flip-flop after waiting for a time longer than the reference frequency
period. An enable bit is supplied for this purpose. After confirming that the unlock enable bit is
set to "I", access the unlock flip-flop.
Setting the unlock reset bit to "1" resets the unlock enable bit.
Use the OUT1 and lN1 instructions with the operand [CN=7H or 9H] to control these ports, and
to load data.
(Note) When the PLL is off, the DO output is set to high impedance. However, when DOI is
set as an output port (OT output), the data are output from the port without change.
2. Phase comparator, Unlock port timing
Reference Frequency u
l High Impedance
" L" Level
Program mable
Counter Output
DO Output ' . I
-i-tu-t-,
Phase Difference l
Unlock Detect Strobe th, th,
Unlock Reset Execution y.'"
Unlock Flip-Flop
Unlock Enable
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TOSHIBA TC9318FA/FB
3. Phase comparator, Unlock port circuit structure
Reference Frequency Signal VDD -
Programmable COMPARATOR D DO2
Counter Output
e 'sp-Iso) DOI /OT
UNLOCK UNLOCK
ENABLE F/F
OTC 0T2
UNLOCK Hz
RESET --
D02 Cii"
DOI /OT 9 Ds:
When setting different filter When using the same
constants for each band low pass filter for both bands
(Set DOI to high impedance to
switch the filter constant)
DC-DC Vcc (3V)
CONVERTER
gt o ".Y"
To VCO . B- " - AAgk
Varactor diode ct . 1ptF 4.7km 2.2kQ
2SC4116GR
2SK209Y
0.01#F
(Note) The filter circuit shown in the above figure is an example for reference, and the
actual circuit should be investigated and designed conforming to the system band
construction and the required characteristics.
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TOSHIBA TC9318FA/FB
O IF counter
This is a 20bit general-purpose intermediate frequency (IF) counter used for such purposes as
counting the FM or AM intermediate frequency during auto-tuning or detecting the auto-stop
signal.
The IF counter block consists of a 20bit binary counter and a control port.
1. IF counter control port, Data port
Y1 Y2 Y4 Y8
fbL16 IF/IN
IF/IN switching bit
( 1 set to IF input
0 : set as generaI-purpose input port
Y1 Y2 Y4 Y8
- Fre uenc measurin ate time selection (measurin time)
¢L17 STA/STP MANUAL GO G1 q y g g g
-Br" G1 GO GATE TIME
0 0 1ms
0 1 4ms
1 0 16ms
1 1 64ms
- Frequency measuring auto/manual mode switching bit
0 .' Auto mode
(Auto mode uses the above gate times for measuring)
1 : Manual mode
(The STA/ST-P bit is used to start and stop measuring)
IF counter start/stop control bit
( 0 .' Stops counter
1 : Starts counter (Setting the timer/counter resets the counter)
34 2001-06-19
TOSHIBA TC9318FA/FB
Y1 Y2 Y4 Y8
0 : IF counter values220-1
K10 f Overflow detection (
ff BUSY MANUAL OVER 1 1 : IF counter value >22°(overflow state)
; Operating mode t : IF counter auto mode
1 : IF counter manual mode
0 : IF counter count-up complete
Operation monitor (
1 : IF counter count-up in progress
¢K11 ¢K12 ¢K13 ¢K14 ¢K15
Y1 Y2 Y4 Y8
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19
20 219
LSB IF Counter Data MSB
(Note) When the PLL is off, the IF counter is disabled.
IF counter auto mode (Frequency measuring)
To use IF counter auto mode, use the IF/W switching bit to set the IF pin to IF input.
Set the gate time based on the IF input frequency band. Set the MANUAL bit to "0" and
the STA/W bit to "1" to start the IF counter.
As a result, the clock for the 20bit binary counter is input from the IF pin for the specified
gate time. The IF counter counts the number of input pulses. To determine when the IF
counter has finished counting, check the BUSY bit. When the count equals or exceeds 220
input pulses, the OVER bit is set to "1".
To measure the frequency input to the IF input pin, load the F0~F19 IF data when the
BUSY and OVER bits are both "o".
IF counter manual mode (Frequency measuring)
Use manual mode to measure the frequency using the IF frequency by controlling the gate
time using an internal time base (eg, 10H2).
Perform the same IF counter input settings as for auto mode, and set the GO and G1 bits
to other than "I". Set the MANUAL bit to "1" and the STA/ST_P bit to "1" to start the
count. Setting the STA/rrp bit to "0" terminates the count and loads the data in binary
format.
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TOSHIBA TC9318FA/FB
2. IF ounter circuit structure
FO-F19 OVER
20bit Binary Counter H OVER I
' - MANUAL
Gate Time _ GO
Control Circuit - G1
Gate Clock "
1kHz STA/ste
The IF counter block consists of an input amp, a gate timer control circuit, and a 20bit binary
counter.
When the PLL is turned off, the IF counter is off. However, the block can still operate when set
as a timer/counter.
(Note) The IFIN pins incorporate amps. Connecting the pins via a capacitor permits Iow-
amplitude operation.
(IFIN) cm1mmmmmmmm1E
Set Data in STA/sms Bit --9-
BUSY Bit -I-t-
GateClock -rLrLrLrLrLrLrLr1-1kHz
Gate -l l-
BinaryCounterlnput -lmmmmmi-
Frequency measuring auto mode
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TOSHIBA TC9318FA/FB
C) LCD driver
The LCD driver has a 1/3 duty and 1/2 bias drive (frame frequency is 83Hz).
The common outputs are at three voltages : l/LCD, VLCD/2VEE, and GND. The segment outputs are
at two voltages : VLCD and GND.
The combination of three common outputs and 23 segment outputs enables the LCD driver to drive
a maximum of 69 segments.
LCD driver segment output pins S16--S23 are also used for the key return timing signals for loading
key matrix data.
The LCD driver incorporates a constant voltage circuit (VEE= 1.5V) and voltage double boosting
circuit (VLCD=3-0V) for the display. This maintains an even LCD contrast regardless of fluctuations
in the supply voltage.
1. LCD driver port
Y1 Y2 Y4 Y8
¢L2D S1 S2 S4 S8
Segment Data Select
Segment Data 2 Segment Data 1
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L2F COM1 COM2 COM3 * ffL2E COM1 COM2 COM3 *
- 0 SI? 0 SI
1 I S18 1 I S2
al s19 al s3
al S20 al S4
ol $21 4' S5
sl $22 ' , I
6' S23 l l I
l : l COM1 COM2 COM? *
KEY F SIE
F DISP RETURN TEST *
OFF SELECT DATA "-e-o
' : don't care Segment Data 1 : Light on
0 : Light off
(Note1) The segment data control whether or not the segments corresponding to the
common and segment outputs are lit.
(Note2) The DISP OFF bit is set to "1" at a system reset and at release of clock stop
37 2001-06-19
TOSHIBA TC9318FA/FB
The LCD driver control ports consist of a segment data selection port and segment data ports.
Use the OUT2 instruction with the operand [CN=DH--FHI to access these ports.
Set the LCD driver segment data using the segment data ports (¢L2E, ¢L2F). Set the segment
data port to "o" to turn the LCD display off and set "I" to turn the LCD display on. When FH is
specified for the segment data select port, the DISP OFF and KEY RETURN SELECT bits are
selected as segment-it data port (¢L2FF). The DISP OFF bit can turn the whole LCD display off
without setting segment data.
Setting this bit to "1" outputs the de-selected waveform from the common outputs and turns
off the entire LCD display. The segment contents are preserved. Setting the DISP OFF bit back to
"0" displays the previous LCD screen.
Segment data can be rewritten during DISP OFF. After a reset, and after CKSTP execution, the
DISP OFF bit is set to "I".
The KEY RETURN SELECT bit allows an external power supply to be used. This is useful for
changing the LCD drive voltage.
The data are set according to the segment data select port (¢L2D). Segment output pins
S16--S23 are also used for the key return timing signals for loading key matrix data. At the
timing for loading the key matrix data, the segment output is set to the GND level.
2. LCD driver circuit structure
ts, LO LO Q
a: D! n: m n: tE
.- fN m tf tf E if. tf tf
a. Ps 00 cr, N m
g g i? T" N m T" G _- .- N N
U U U m m m vs vs m vs vs
OFF -lcommon Output Circuitm Segment Driver/Segment Data
500Hz ________
Key Return Control Circuit
3V Constant Voltage Circuit
1.5V ESE {ESE
[El 5% IE] 8
OFF VLCD OFF Signal
KVEE c2 CI VLCD
2 Gi 63 62 61 2
tviii'" tvii:'
.- 0.1IuF _-
o; 0-;
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TC9318FA/FB
TOSHIBA
3. LCD driver timing chart
The following chart shows the timing for the COM1-COM3 output waveforms and the eight
types of segment output waveform.
1/2 VEE
--------- VLCD
3%. A J 1.
C y .r y
m 2W 4 A
5 OarV
D C V v
10: A 4
-------- VLCD
----- GND
oNlloNllffffff)
"i'jjj'jcCglCijiicj'caloN
o_Nllr,ifjfj3lo_N
Eii3io7llo7]
Segment Output
(S1~523)
2001 -06-1 9
TOSHIBA TC9318FA/FB
4. Example of timing chart for LCD driver output data and loading key data
The following chart shows the output waveform timing and key return data loading timing
when the common and segment outputs are allocated as shown.
S2 Display Data (Output data example)
ts- C) Segment data select (¢L2D)
S3 SI COM1 95ng
3 L Y1 Y2 Y4 Y8
0 0 1 * S1
(50013 1il1-co,v,2Ct' Ill 'S2
=evil, c: o 2 1 0 * S?
COM3 COM
I ms I
DISP OFF I I
,.'-l i-l -ULCD
COM1 ' I
Cl Cl - GND
Cl [_I - VLCD
Cl Cl - GND
i, m I'-'l - VLCD
|_l Cl - GND
- VLCD
- VLCD
- - GND
- VLCD
-' - GND
5 - - VLCD
S16/KR7 l 5
- - _ - - - GND
Key Data Loading
-I - VLCD
COM1-SZ I,
(ON Waveform) - GND
_I _I - - -VLCD
COM2-53 - VLCD
WWW -GND
- -VLCD
The voltages output in the LCD driver waveform are l/LCD, GND, and an intermediate voltage
halfway between the two. Pins S16--S23 output the key return signals at the timing for
switching between these levels. During key return data loading, the segment outputs are at the
VLCD level for 80ps.
(Note) At CKSTP instruction execution or at a system reset, the common and segment pins go
to the low level.
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TOSHIBA TC9318FA/FB
0 Key input, Key scan timing
The following are the two basic methods of loading key data.
Select the appropriate method for the system.
1. Key Control Port, Key Scan Data Port
Y1 Y2 Y4 Y8
SEG-2 DATA
KEY TEST 0 : Output the Key Return Signal by software
DISP OFF RETURN * ' .
SELECT DATA 1 : Output the Key Return Signal by changing the LCD
I output
Key Return Select Bit
In case of setting data
timing as shown below.
l" to the key Return Select bit, the segment output is the output
Segment output A truiru V VLCD(3V)
-e 80/s l--
VLCD(3V)
Segment output
When the key Return output, the level is "L".
In case of setting "0" to the bit, The key Return signal don't outputted.
Key Scan Digit Port Key Scan Input Data Port
Y1 Y2 Y3 Y4 Y1 Y2 Y3 Y4
KEY SCAN DIGIT K28 KEY SCAN INPUT DATA-O
' KS0 I KS1 I KS2 1 Ksoo I KS01 I KSO2 I K503
¢K29 KEY SCAN INPUT DATA-1
KS10 I KS11 I KS12 I K513
¢K2A KEYSCANINPUT DATA-2
KS20 I KS21 I KS22 I K523
fbK2B KEY SCAN INPUT DATA-3
K530 I K531 I KS32 I K533
fbk2C KEYSCANINPUTDATA-4
K540 I K541 I K542 I K543
¢K2D KEY SCAN INPUT DATA-5
KS50 I KS51 I KS52 I K553
¢K2E KEY SCAN INPUT DATA-6
KS60 I KS61 I KS62 I KS63
¢K2F KEY SCAN INPUT DATA-O?
KS70 I KS71 I KS72 I KS73
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TOSHIBA
TC9318FA/FB
The key Return Select bit is the bit of setting the loading key method.
The data is loading by the digit timing of the key Return Signals from the key scan digit
The key data by key scan is input to the key scan input data port. By accessing this port, the
key data is loading to the data memory.
2. Key Scan Circuit structure
KEY SCAN INPUT DATA
K3 K2 K1 K0
T3 m KR1
's Ci?, K0
T2 E L-
E Cais? K1
E Ciii' K2
S23(KRO) >4
$22 (KR1)
DECOD ER
$21 (KR2) -
LCD SEGMENT DR IVER
$17 (KRG)
$16 (KR7) 19
K0 K1 K2 K3
Timing COUNTER
The key input block of the key scan circuit consist of key input circuit, latch circuit for
loading key data.
The key return timing output block consist of LCD segment driver, decoder and counter block.
2001 -06-1 9
TOSHIBA TC9318FA/FB
3. Key matrix structure
The key matrix can have one of the following two structures.
(1) Key data loading by software
- T0 J I
T5 H>v- I-I
fh Ah fh
' V \l
C) C C) O c, T4 I I
" r r\ CN fh
)( )( ' v.' v.r
K0 - 27 A:\KCJ C C) C) C) i-l-
i f i 1 T5
Key Data A A A n m A
Loading V V U V V U
Push Key Diode Jumper I
When loading key data by software, use a key matrix with the above structure. For this
method, set to high the key timing output port data (¢L28, ¢L29) for the key line to be
loaded. Then to determine which keys are pressed, load the key input port (¢K26) data to
memory. At this timing, set the other key timing output ports to low. If the corresponding
key is pressed, the key input port data are "1" ; if not pressed, "o". This structure allows up
to 24 (4xS)) keys to be used. The key data can be loaded at high speed. Also, as the
structure has a high resistance in the N channel FETs of pins T0--T5, there is no need to use
a diode to prevent reverse current flow caused by, for example, multiple keys being pressed.
When loading key data by software, set to "o" to the key return select bit.
(Note) In case of structuring a diode jumper, the key input voltage is input/ow voltage of
VF (20.6V) voltage of diode. It's necessary the diode for diode jumper malfunction
prevention to structure of double push of a key.
The diode is unnecessary when there is no diode jumper necessity. Therefore, key
input thre-shold level is set up low.
In the mode structure, when executing a wait instruction (in WAIT mode), applying a high
level to a key input pin releases WAIT mode and restarts the CPU.
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TOSHIBA TC9318FA/FB
(2) Key data loading by LCD segment output (hardware scan)
To Key Scan IKB A
i 30 %
Data Latch
f\ (”x f\ .
29 o .') 0 c, C)
K1 rx h fh r\ fh
28 \J J _ ' \J dy
27 t-2sl2sl2s LALA
26(KRO) 5
$22 KRI th.
25 ( I
S21 KR2 D
24 ( ) u
4; QMHKRS)
19 S16(KR7)
(Note) A key matrix to 4x8=32 can be created.
(Note) The same key line cannot contain both push keys and diode jumpers or alternate
switches. Place diode jumpers or alternate switches on the key return signal output
2ms 80/15
" n ' VLCD
S30(KRO) W """"N,.; 2% cztiitEiiiiC:
I I tt I I tt
_ VLCD
S29 (KR1) N
_ l . GND
' ' _ l VLCD
may) AV w W
" u GND
Key Data Latch
Key Scan Data -ll I l 40“} /\/ n n I I
U-ol /
Loading Timing
Key Input Pulled Up Key Loading Signal
(80 ta)
When loading key data by LCD segment output, use a key matrix with the above
structure. In this structure, it's necessary for a diode to prevent reverse current flow and
be careful the direction of diode and diode jumper.
The VLCD and GND potential are outputted from a segment pin at the timing of changing
LCD output.
When loading key data, loading of segment signal becomes to the GND potential and key
input pin is pulled up to the VDD potential at changing LCD output.
44 2001-06-19
TOSHIBA TC9318FA/FB
At this timing, if key is not pressed (or without diode jumper), key input pin is inputted
VDD potential , if key is pressed (or with diode jumper), key input pin is inputted one
diode potential (=0.6V) from GND potential.
Therefore, key input threshold level is set up high.
Inputted key data is load key scan data port corresponding to segment output line of
loading the key. If a key is pressed, the key data is "I'' ; if not pressed, "o".
The key data loading time for each one line is 2ms. Referring the key scan action monitor,
key scan data (¢K26) is loaded to the data memory.
C) Key Return Timing Output Port (Tir-TS)
Ttr-rs are exclusive output port of 6 bits with N-channel load resostors. Normally, Ttr-rs is used as
output of key return timing Signal for Key matrix.
This output port is made access by OUT2 instruction designated the operand part [CN=8 or 9]
(¢L28 or ¢L29).
(Note) During the clock stop mode (excusing CKSTP instruction), To--" and 0T0, 0T1 output is
fixed at "L" level automatically, but the content of port is held on the previous data.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L46 T0 T1 T2 T3 fbL47 T4 T5
C) Buzzer output (BUZR)
The buzzer output is used for such purposes as audible alarms or to issue confirmation beeps for
key-presses or tuning scan mode. The buzzer frequency can be set as desired. 50% duty waveform
is output.
BUZR data port
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 - Controls the BUZR output frequency and BUZR output on/off.
¢L1B BO B1 B2 B3 ¢L1C B4 B5 B6 B7
\20 a) Selectofl/Oport-3(P3-1)andBUZRoutput.
LSB BUZR Data MSB {0 : I/O port-3 (P3-I)selection
I— 1 : BUZR output selection
Y1 Y2 Y4 Y8
¢L1E ON
The BUZR output can also be used as the P3-1 I/O port. To switch the P3-1 output to BUZR
output, set "I" to BUZR ON bit.
It is necessary to set of the BUZR data before setting the BUZRON bit to "I".
Setting the data to BUZR data port (¢LIC), the BUZR data is transferred to the BUZR data Latch,
and then changed BUZR frequency.
The BUZR output has a frequency of 75kHz divided by 2xn (n =BO--B7). The BO~B7 setting
range and frequency range is 2SnS255. This can be expressed as a formula as follows.
75kHz 75kHz
- =18.75kHzsfBuzRs - =
2x2 2X255 147Hz
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TOSHIBA TC9318FA/FB
Set BO~B7 to 1 or 0 to use the pin for 0T1 output. The output states are as follows.
B7 B6 B5 B4 B3 B2 Bl BO 0T1 OUTPUT
0 0 0 0 0 0 0 0 Low level output
0 0 0 0 O 0 0 1 High level output
To set the above data, use the OUT1 instruction with the operand [CN=BH~EH].
(Note) After a system reset, the BUZR data port is reset to "o".
2. BUZR circuit structure
Counter
75kHz Programmable Counter fdg" 0T1 /BUZR
BUZR Data Latch
BUZR Data Port
The buzzer circuit consists of an 8bit programmable counter, a 1/2 counter, a buzzer latch, and
a buzzer data port.
3. BUZR output timing (BUZR ON bit is "1")
BUZROutput ILI‘LrLI |_l Le-l |_l
BUZR Data Port W Data All "0"
(75L1C) u
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TOSHIBA TC9318FA/FB
C) A / D converter
The 2 channel/6bit resolution A/D converter is used for such purposes as measuring field intensity
and battery voltage.
1. A/D converter control port, Dare port
Y1 Y2 Y4 Y8
AD AD REF REF
¢L20 SELO SEL1 SELO SEL1
u Y J u I J _ DC-REF Select
SEL1 SELO DC-REF VOLTAGE
0 0 Supply from DC-REF pin
0 1 VDD (Power Supply Voltage)
1 0 VEE (1.5V constant voltage)
1 1 Prohibited
AD Input Select
SEL1 SELO A/D INPUT
0 0 ADIN1
0 1 ADINZ
1 O VEE (1.5V constant voltage)
1 1 Prohibited
Y1 Y2 Y4 Y8
w STA "J,?'' "),11 2°;
A/D Input and I/O port Select
I {0:I/O Port
: A/D Input
DC-REF Input and I/O port Select
{0 : I/O Port
1 : DC-REF
A/D Converter Start bit
Setting "I" Starts A/D Comparison
ff K20 Y1 Y2 Y4 Y8 ¢K21 Y1 Y2 Y4 Y8
ADO AD1 AD2 AD3 AD4 ADS BUSY 1
l I . .
LSB A/D comparison data MSB A/D Operating monitor
{0 : finished A/D comparison
1 : operating A/D comparison
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TOSHIBA
TC9318FA/FB
The A/D converter is a 6bit resolution. The reference voltage of A/D conversion can select the
external voltage (DC-REF terminal), supply voltage and 1.5V constant voltage (VEE). The A/D
conversion input is a multiplex method of 2-channel external input terminal (ADIN1, ADINZ
terminal) and also switchable to 1.5V constant voltage (VEE) as well.
Normally field strength and volume level are measured by selecting external voltage or supply
voltage as reference voltage and A/D converting the external input level.
The A/D converter can also measure battery and supply voltages. It outputs a battery singal or
performes control for backup mode when battery voltage or supply voltage drop.
The A/D converter does A/D conversion whenever setting "1" to STA bit and the conversion
will complete after 7 machine cycles (280ps). Whether A/D conversion is completed can be
judged by referring to BUSY bit. After A/D conversion is completed, the data will be loaded
into data memory.
These controls are accessed when OUT2/IN2 instruction designated [CN=0H, 1H] in the operand
is executed.
2. A/D converter circuit configuration
A/D data ADO
AD SELO 'N 42 ADIN1
Sample SELI \/° ' tlt
VDD oq
REF Amplifier 49 ADlNit
SELO 'N
-(44) DC-REF
Com parator
l conversion
data latch
Control
Circuit
STA BUSY
- Decoder
R consta nt sy VEE
voltage
circuit
6bit D/A converter
The A/D converter consists of : 6bit D/A converter, comparator, A/D conversion latch, control
circuit, A/D data port and 1.5V constant voltage circuit (supply for LCD driver).
The A/D converter will latch the data to A/D conversion data latch sequentially by means of
the 6bit sequential comparison method.
(Note)
(Note)
The DC-REF terminal is built-in an amplifier and is high impedance input.
During A/D conversion, a proper data is not obtainable even if referring to the A/
D conversion data. Therefore, make sure to confirm that the conversion has finished
by referring to the A/D operation monitor.
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TOSHIBA TC9318FA/FB
C) Input and output port
HO Port P1-0~P1-3 (¢KL22), P2-0--P2-3 (¢KL23), P3-0~P3-1(¢KL24)
l/O port (P1-0~P1-3, P2-0--P2-3) are 4 bits and (P3-0--P3-1) are 2 bits CMOS type, and is capable
of making input and output setting with each bit.
Input and output setting of I/O port is made by the content of I/O control internal port.
Setting to input port can be made by setting "o" to the bit of I/O control port corresponding
to I/O port, while setting to output port can be made by setting "I" in the same.
In case of input port setting, the present data input I/O port is read into the data memory by
the execution of lN2 instruction designated the operand part [CN=2--4] (¢K22, ¢K23, ¢K24).
In case of output port setting, output condition of HO port is controlled execution of OUT2
instruction designated the operand part [CN=2--4] (¢K22, ¢K23, ¢K24).
I/O port 2~3 are also used for A/D converter and BUZR output.
After system reset, these ports are set to l/O port.
(Note 1) HO control port is made access by OUT2 instruction designated the operand part
[CN = 5--71.
(Note 2) During the clock stop mode (executing CKSTP instruction), output condition of HO
port set at output mode is all fixed at "L" level automatically, but each output latch
holds on the data just before the clock stop mode.
(Note 3) At the time of changing input condition of P1-0~P1-3 port set at input mode, it
cancels the execution of WAIT and CKSTP instructions and makes the operation
restart. In case of setting "1" to l/O bit of MUTE control port, MUTE port is made
to set to "I" compulsorily by the same condition.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢KL22 PI-O Pl-l PI-? PI-? ffL25 PI-O PI-I PI-? PI-?
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢KL23 P2-0 P2-1 P2-2 P2-3 ¢L26 P2-0 P2-1 P2-2 P2-3
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢KL24 P3-0 P3-1 * * ¢L27 P3-0 P3-1 1 1
+1 a—’
NO PORT Set up input and output of I/O PORT
49 2001-06-19
TOSHIBA TC9318FA/FB
C) Register port
The G-register (mentioned in the CPU description) and the data register are treated as internal
ports.
1. G-register (95 L1F)
This register sets the row address (DR=4H--FH) in data memory for the MVGD and MVGS
instructions. To access this register, execute the OUT1 instruction with the operand [CN =FH].
(Note) The register value is only used when the MVGD or MVGS instructions are executed.
The register is ignored for other instructions.
Y1 Y2 Y4 Y8
¢L1F #0 #1 f2 #3 #0 #1 #2 #3 DR
Specifies data memory 0 0 1 0 4H
row address 1 0 1 0 5H
0 1 1 0 6H
, S i S S
0 1 1 1 EH
1 1 1 1 FH
(Note) Setting data OH-FH in the G register allows all the data memory row addresses to
be specified indirectly. (DR--0H-FH)
2. Data register (¢K1C~¢K1F)
This is a 16bit register to load the program memory data when the DAL instruction is executed.
The contents of the register are read to data memory in units of 4 bits by the lbl1 instruction
with the operands [CN=CH~FH].
This register can be used for such purposes as LCD segment decoding, radio band edge data, or
for coefficient data for binary-to-BCD conversion.
Y8 Y4 Y2 Y1
d d d d d d d d d d d d d d d d
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
¢K1F ¢K1E ¢K1D ¢K1C
MSB Program Memory 16bit Data LSB
50 2001-06-19
TOSHIBA TC9318FA/FB
C) Timer and CPU stop function
The timer has 100Hz, 10Hz and 2H2 flip-flop bits. These are used for counting operations, such as
for a clock or tuning scan mode.
The CPU stop function uses a voltage detector circuit to shut down the CPU when the VDD voltage
applied to the CPU falls below 1.5V. This prevents CPU malfunction.
1. Timer port, STOP flip-flop bit
Set to "l"
Reset Port Timer Port {when VDD falls below 1.5V.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
2Hz 2Hz STOP
L1A _ K1A
' HF Timer ff F/F 10Hz 100Hz F/F
I i l l
l l - i
u----"
Setting "1" resets the 2H2 F/F, the STOP HF, and the 10Hz and 100Hz bits.
To access the timer port and the STOP flip-flop bit, execute the OUT1/IN1 instruction with the
operand [CN =AH].
2. Timer port timing
The 2Hz timer flip-flop is set by the 2H2 (500ms) signal, and reset by setting the RESET port 2H2
flip-flop to "I". This bit can normally be used for the clock count.
The 2Hz timer flip-flop is only reset by the 2Hz flip-flop in the RESET port. Therefore, if the flip-
flop is not reset within 500ms, the next count is missed and the correct time is not obtained.
2Hz Timer
Flip-Flop Output
2Fiz Flip-Flop
Reset Execution
t<500ms
2H2 Clock
' 500ms l
The 10Hz and 100Hz timers are output to the 10Hz and 100Hz bits with a cycle of 100ms and
10ms, respectively, and a pulse duty of 50%. Whenever the RESET port timer bit is set to "I",
counters below 1kHz are reset.
10Hz 50ms I I I
100Hz 5ms I I I
51 2001-06-19
TOSHIBA TC9318FA/FB
3. CPU stop function, STOP flip-flop bit
The STOP flip-flop bit is set to "I'' when the VDD voltage applied to the CPU falls below 1.5V.
This prevents CPU malfunction by shutting down the CPU. When a voltage of 1.5V or less is
applied to the VDD pin, the program counter stops and instruction execution ceases in the CPU.
When a voltage higher than 1.5V is again applied to the VDD pin, The CPU starts up again. As
the CPU was shut down, the clock and other timings are no longer valid. Use the STOP flip-flop
to test whether the CPU stop function operated. Perform initialization or clock correction if
required.
The STOP flip-flop bit is reset to "o" whenever the RESET port 2H2 flip-flop is set to "I".
2Hz Flip-Flop CPU in CPU Stopped', CPU in
Reset Execution Operation l Operation
" l \“l
STOP F/F I
(Note) After a system reset or execution of the CKSTP instruction, the timer port and the
STOP flip-flop are reset to "o".
(Note) If the VDD voltage falls below 1.5V when clock-stop mode is set, the CKSTP
instruction cannot be executed. Be careful with the supply voltage timing, for
example, when the radio is off.
(Note) The key scan input data immediately after restarting the CPU are undefined.
(Note) If the interal Test port from #0 to #3 bit (¢L1D) is set to "I", the CPU stop
function is inhibited.
52 2001-06-19
TOSHIBA TC9318FA/FB
C) MUTE output
This is a 1bit CMOS-format output-only port for muting control.
1. MUTE port
Y1 Y2 Y4 Y8
¢L18 MUTE IIO POL UNLOCK
- Phase comparator phase difference output select
{0 : Does not output phase difference
1 : Outputs phase difference
- MUTE output polarity control
{0 : Positive logic ... Outputs MUTE bit
1 .' Negative logic ... Inverts MUTE bit output
(Note) The phase difference output is also controlled at the same time
- Selection of control operation when input state of IIO port 1 changes
{0 , Even if I/O port 1 input state changes, do not change MUTE output
1 : Change in IIO port 1 input state sets MUTE bit to "l"
MUTE output setting
0 .' MUTE output is low when positive logic is set, and high when negative
( logic is set
1 : MUTE output is high when positive logic is set, and low when negative
logic is set
Access the MUTE port by executing the OUT1 instruction with the operand [CN=8H]. The MUTE
output is used for muting control. At such times as switching bands using the I/O port 1 input, the
MUTE bit can be set to "I".
When using the HO port 1 input to switch bands (using a slide switch, for example), this function
prevents linear circuit switching noise. This control is based on I/O bit values.
The POL bit sets the MUTE output logic.
The mute output can also control muting using the phase difference output. A pulse is output to
indicate when the PLL is not locked. By connecting an external low-pass filter to the MUTE output,
the output can be used as a MUTE signal. Use the UNLOCK bit to perform selection.
53 2001-06-19
TOSHIBA TC9318FA/FB
2. MUTE output structure and timing
High Level
High Impedence
. . . . 2 ....... . . .
POL Bit DO Output ]_I l-l Lk l
. Low Level I
MUTE bit Phase Difference -l-Lr'irl-lnuo'"''-"'''e'rl-
c; @ MUTE I
UNLOCK Bit -l-'7',r'i,-',i-
l/OBit é
UNLOCK l
Bit -1 I
Phase Comparator MUTE Bit l I I I
I/O Port 1 Phase Difference -1 _| H h
Input Change Signal MUTE Output
s'-- Phase Difference Input
(Note) When POL bit=0
(Note) When using the phase difference output by the phase comparator, externally
connect a Iow-pass filter to the MUTE output.
0 Test ports
These are internal ports for testing the device's functions. Access the ports by executing the OUT1
instruction with the operand [CN=AH] or [CN=DH], or the OUT2 instruction with the operands
[CN =FFH]. The ports are normally set to "o" by software.
If the data "1" is set to Test port bit from #0 to #3, the CPU stop function is inhibited and the
data "o" is set, the CPU function is operating.
In case of using supply voltage detection externally, set CPU stop function as inhibition.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L1D #0 fl #2 #3 ¢L1A #4 f5 ¢L2FF #6
c-v-" W W“
Test Port Test Port Test Port
(Note) The ports are reset to "o" after a system reset.
54 2001-06-19
TOSHIBA TC9318FA/FB
MAXIMUM RATINGS (Ta=25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.3-4.0 V
Input Voltage VIN -0.3--VDD+0.3 V
Power Dissipation PD 100 mW
Operating Temperature Topr -10--60 °C
Storage Temperature Tstg - 55--125 ''C
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Ta =25°C, VDD=3.0V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Range Of Operating *
Supply Voltage VDD - 1.8 3.0 3.6 V
Range Of Memory V Crystal ocillation stopped * 1 0 '"- 3 6
Retention Voltage HD (CKSTP instruction executed) . .
Under ordinary
operation and PLL on
operation, no output VDD=3.0V - 7.0 12
I FMIN =230MHz input A
DDI - Under ordinary m
operation and PLL on
operation, no output VDD=3.0V - 6.0 10
. FMIN = 130MHz input
Operating Current Under CPU operation
IDD2 - (PLL off, display VDD=3.0V - 40 80
turned on)
Soft Wait mode
IDD? - (Crystal oscllator, display circuit - 25 50 pA
operating, CPU stopped, PLL off)
I Hard Wait mode 15 30
DD4 (Crystal oscillator operating only)
Memory Retention I Crystal oscillation stopped 0 1 10
Current HD (CKSTP instruction executed) .
Crystal Oscillation *
Frequency fXT - - 75 - kHz
Crystal Oscillation . .
Startup Time tST - Crystal oscillation fXT=75kHz - - 1.0 s
For conditions marked by an asterisk (*), guaranteed when VDD=1.8-3.6V, Ta = -1ir-6iy'C.
2001 -06-1 9
TOSHIBA TC9318FA/FB
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Voltage doubler circuit
Voltage Doubler
Reference Voltage VEE - GND reference (VEE) 1.3 1.5 1.7 V
Constant Voltage
Temperature DV - GND reference (VEE) - -5 - mV/°C
Characteristics
Voltage Doubler
Boosting Voltage VLCD - GND reference (VLCD) 2.6 3.0 3.4 V
Operating frequency ranges for programmable counter and IF counter
FMIN (VHF Mode) fVHF - Sine wave input when V|N=0.2Vp_p 50 -- 230
FMIN (FM Mode) fFM - Sine wave input when V|N=0.2Vp_p 40 -- 130
AMIN (HF Mode) fHL - Sine wave input when V|N=0.2Vp-p 1 -_- 45 MHz
AMIN (LF Mode) fLF - Sine wave input when V|N=0.2Vp_p 0.5 -- 12
IFIN hr: - Sine wave input when VIN =0.2Vp-p 0.35 .- 12
Input Amplitude VIN - FMIN, AMIN, IFIN input 0.2 '.%.. 1’33 Vp-p
LCD common output/segment output (COM1--COM3, S1~523)
Output "H" Level IOH1 - VLCD = 3V, VOH = 2.7V - 0.5 - 1.0 - A
Current "L'' Level IOU - VLCD=3V, V0L=0.3V 0.5 1.0 - m
Output Voltage 1/2 v35 - No load 1.3 1.5 1.7 v
HOLD input port
Input Leak Current Ity - VIH =3.0V, lhL=0V - $1.0 pA
Input "H" Level VIH1 - - 2.4 -- 3.0 V
Voltage "L" Level VIL1 - - 0 -- 1.2
A/D converter (A/D|N1, A/DIN2, DC-REF)
Analog Input Voltage
V - AD AD -- V V
Range AD lhl1, lN2 0 DD
Analog Reference VDD
Voltage Range VREF - DC-REF, VDD=2.0 3.6V 1.0 x0.9 v
Resolution VRES - - - 6.0 - bit
Conversion Total - - VDD=2.0--3.6V - 11.0 14.0 LSB
V|H=3.0V, lhL=0V +
Analog Input Leak Ity (ADINL ADIN2, DC-REF) _1.0 pA
For conditions marked by an asterisk (*), guaranteed when VDD=1.8-3.6V, Ta = -1ir-6iy'C.
2001 -06-1 9
TOSHIBA TC9318FA/FB
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
KEY input port (Ko-Ka)
N-ch/P-ch Input
. R - - 7 1 k0
Resistance IN1 5 50 300
Input "H" Level 1/IH2 - When input with pull-down resistance 1.8 -- 3.0 V
Voltage "L" Level VIL2 - When input with pull-down resistance 0 ~ 0.3
Input "H" Level VIH3 - When input with puII-up resistance 2.7 -- 3.0 V
Voltage "L" Level VIL3 - When input with pull-up resistance 0 -- 1.2
When input resistance off,
- - - +
Input Leak Current Ity VIH =3.0V, VIL=0V - 1.0 pA
Timing output port (TO-TS)
Output "H" Level IOH1 - VOH = 2.7V - 0.5 - 1.0 - mA
Current "L" Level IOL1 - VOL=0.3V, Use LCD key-return mode 0.5 1.0 -
N-ch Load Resistance RON - No used LCD key-return mode 75 150 300 k0
DO1/OT, D02 output ; MUTE output
Output "H" Level IOH1 - VOH = 2.7V - 0.5 - 1.0 - mA
Current "L" Level IOL1 - V0L=0.3V 0.5 1.0 -
Output Off Leak
- = = - - +
Current ITL VTLH 3.0V, VTLL 0V (DOI, D02) -100 nA
General-purpose I/O ports (Pl-ir-Pa-l)
Output "H" Level IOH1 - VOH = 2.7V - 0.5 -1.0 - A
Current "L" Level IOU - VOL=0.3V 0.5 1.0 - m
Input Leak Current Ity - V|H=3.0V, VIL=0V - $1.0 PA
Input "H" Level VIH4 - - 2.4 -- 3.0 V
Voltage "L" Level VIL4 - - 0 -- 0.6
IN, RESET input port
Input Leak Current ILI - VIH =3.0V, VIL=OV - $1.0 pA
Input "H" Level VIH4 - - 2.4 -- 3.0 V
Voltage "L" Level VIL4 - - 0 -- 0.6
57 2001-06-19
TOSHIBA TC9318FA/FB
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Others
Input Pull-Down
Resistance RINZ - (TEST) 25 50 100 k0
XIN Amp Feedback
Resistance RfXT - (XIN XOUT) - 20 - Mn
XOUT Output
R - X - - k0
Resistance OUT ( OUT) 3
Input Amp Feedback RfIN1 - (FM|N,AM|N) 150 300 600 k0
Resistance RfIN2 - (IFIN) 500 1000 2000
Voltage Used To
Detect Supply Voltage VSTp - (VDD) 1.3 1.5 1.6 V
Supply Voltage Drop
Detection Temperature Ds - (VDD) - -2 - mV/°C
Characteristics
58 2001-06-19
m Two- room
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25 ammo ” £925
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mzo_mzm_>:n_ mwm_H_\TOSHIBA TC9318FA/FB
PACKAGE DIMENSIONS
QFP64-P-1212-0.65 Unit : mm
14.0:t0.2
12.0i0.2
Cl: fififlfififlfWifW%Wi
',c'i'.-v- 49
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HHHTEEHHHHHHH -
1.125TYP_ A o.3:o.1 F5lj:jtatsn
0.5:t0.2
Weight : 0.45g (Typ.)
60 2001-06-19
TOSHIBA TC9318FA/FB
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
61 2001-06-19
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www.loq.com
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Partno	Mfg	Dc	Qty	Available	Descript
TC9318FB	TOS	N/a	308	avai	SINGLE CHIP DTS MICROCONTROLLER (DTS-21)