TC9317F Fast Delivery |IC PHOENIX CO.,LIMITED

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TC9317F
DTS MICROCONTROLLER (DTS-21)
TOSHIBA TC9317F
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC93117F
DTS MICROCONTROLLER (DTS-21)
The TC9317F is a 4bit CMOS microcontroller for digital
tuning systems. It is capable of functioning at a low
voltage of 3V and features a built-in PLL and LCD drivers.
The CPU has 4bit parallel addition and subtraction
instructions (e.g., AI, SI), logic operation instructions (e.g.,
OR, AND), composite judging and compare instructions
(e.g., TM, SL), and time-base functions.
The package is an pin 80, 0.5-mm-pitch quad flat pack
package. In addition to various input/output ports and a
dedicated key-input port, which are controlled by
powerful input/output instructions (IN 1~3, OUT 1~3),
there are many dedicated LCD pins, a PWM output port, LQFP80-P-1212-0.50A
a buzzer port, a 6bit A/D converter, a serial interface, an Weight : 0.45g (Typ.)
f counter, and other pins. A digital tuning system (DTS)
is formed in conjunction with prescalers TD6134AF,
TD7101F, or TD7103F.
Low-voltage and Iow-current consumption make this
microcontroller suitable for portable DTS equipment.
FEATURES
0 4bit microcontroller for digital tuning systems.
It Operating voltage 1/DD=1.8--3.6V, with low current consumption because of CMOS circuitry
(with only CPU operating, when VDD=3V, IDD=100/1A max.)
Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3V booster circuit for the display.
Data memory (RAM) and ports are easily backed up.
Program memory (ROM): 16bitx4096 steps
Data memory (RAM) : 4bitx256 words
62-instruction set (all one-word instructions)
Instruction execution time : 40ps (with 75kHz crystal) (MVGS, DAL instructions : 80ps)
Many addition and subtraction instructions (12 types addition, 12 types subtraction)
Powerful composite judging instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN)
O O O O O O O O 0
Data can be transmitted between addresses on the same row.
1 2001-06-19
TOSHIBA TC9317F
0 Register indirect transfer available (MVGD, MVGS).
o 16 powerful general registers (located in RAM)
0 Stack levels : 2
o JUMP or CAL instruction can be used anywhere in the 4096 steps of program memory (ROM) as
there are no pages or fields.
0 16bit of any address in the 1024 steps in program memory (ROM) can be referenced (DAL
instruction).
o Features independent frequency input pins (FMIN and AMIN) and two (DOI and D02) phase
comparison outputs for FM and AM.
o In FM or TV mode, a swallow counter is formed with prescalers TD6134AF, TD7101F or TD7103F,
and signals of up to 250MHz can be received.
It Seven reference frequencies can be selected by program.
It Powerful input/output instructions (IN 1~3, OUT 1~3)
0 Dedicated input ports (ktr-k3) for key input. 33 LCD drive pins (90 segments maximum) available.
0 25 I/O ports: 24 with input/output programmable in 1bit units, and one output-only port. The
three IFIN1, IFINZI and DOI pins can be switched by instruction to lbll (input-only) or OT (output-
only). All LCD output pins can be switched in 1bit units to l/O ports. (The S30 pin switches to an
IN port).
0 Three back-up modes available by instruction .' only CPU operation, crystal oscillation only, clock
It Features a built-in 2Hz timer F/F and a built-in 10/100Hz interval pulse output (internal port for
time base).
It Allows PLL lock status detection.
0 12 of the LCD segment outputs (S19--S30) can also operate as key return timing outputs
(KRO--KR11). The l/O ports are not dedicated key return timing outputs but can have other uses as
0 Built-in 20bit, general-purpose IF counter can detect stations during auto-tuning by counting the
intermediate frequencies of each band.
0 Built-in 8bit buzzer output circuit can produce 254 different tone signals.
It Built-in 12bit PWM circuit can be used as a simple D/A converter.
0 Features a built-in 2-channel, 6bit A/D converter.
It To prevent CPU malfunctions, a built-in supply voltage drop detection circuit shuts down the CPU
when voltage falls below 1.5V.
2 2001-06-19
TOSHIBA TC9317F
PIN CONNECTION (TOP VIEW)
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TEST P1-O(KR12)
lFIN(lN1/SCIN) K3 :2;
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output Key inputs g'
- D02 K1 'E
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'- GND 529(P14-3/KR1) 5;
Prescaled output
signal
AM local oscillator--- AMIN
signal
Battery OT VDD
---o- FMIN SVFP-80PIN $28(P14-2/KR2)
(0.5mm Pitch) S2 ( )
7 P14-1/KR3
526(P14-0/KR4)
$25 (P13-3 IKR5)
3-": XOUT S24(P13-2/KR6)
it-n-es-s XIN S23(P13-1/KR7)
it-n- VXT S22 (P13-0/KR8)
t-o- VLCD S21 (P12-3/KR9)
c- C1 S20 (P12-2/KR10)
L c2 CD 519(P12-1/KR11)
Q-n- VEE LCD drivers (3 x 30 = 90Max. segments) S18 (P12-0)
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3 2001-06-19
TOSHIBA TC9317F
BLOCK DIAGRAM
10Hz OCK Detector DOI/OT
CPU Tlming Gene. 2H1 F/F DO2
”gas EF
XIN o Reference Divider MPX/La. Phase Com.
VXT SIG La. MUTE
1kHz PLL OFF
PSC MUTE Cont,
FM 4bit Swallow 12bt Programmable
IN FM Counter / La. Counter , La. i/O-l
IN 1kHz FM
IFIN/lm /SCIN 20bit IF Counter
DATA BUS
CODE BUS .
RAM Bbit BUZR
(a x256 word)
f?, P3-3/BUZR
3 ROM 4 pa-ZIW
1 MW Buf P3 1 ISO
' (16X4096 Step) P3-0/SI
8bit Shift
Instruction
12bit PWM
PZ-3/PWM
Frog, Counter P2-2/DC-REF
92-1 /AthN2
P2-0/AD|N1
12 Sblt A
Stack Reg. (ZLevel) VEE
V E Power
LCD/IO Cort/La. 3bit AID ON
VLCD VL KEY KEY RESET VDD
LCD _ GND
COM Segment Driver/La, Dec. KEY Cont. V . . Doubler
Circuit
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4 2001-06-19
TOSHIBA
TC9317F
PIN FUNCTION
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
COM1 /P7-0
COM2/P7-1
COM3 / P7-2
LCD common
output / input-
output ports
Output common signals to the LCD
panel. Through a matrix with pins
S1~S30, a maximum of 90 segments can
be displayed.
Three levels, l/LCD, VEE, and GND, are
output at 83Hz every st.
VEE is output after SYSTEM RESET and
CLOCK STOP are released, and a
common signal is output after the DISP
OFF bit is set to "O".
These pins can also be programmed as
I/O ports.
S1/P7-3
S18/P12-0
LCD segment
output / input-
output ports
$19/P12-1
S30/lN2/
LCD segment
output / input-
output ports (IN
port)/ Key return
timing output
Segment signal output pins for the LCD
panel. Together with COM1, COM2, and
COM3, a matrix is formed that can
display a maximum of 90 segments.
These pins can also be programmed as
I/O ports. (Port S30, however, can only
be programmed as an input pin).
The signals for the key matrix and the
segment signals from pins S19/
KR11--S30/KR0 are output on a time
division basis. 4x12=48 key matrix can
be created in conjunction with key input
ports K0--K3.
Key input ports
4bit input ports for key matrix input.
When the key return timing outputs
(KRO--KR11) of the LCD segment pins are
combined in a matrix with the key
return timing outputs (KR12--KR15) I/O
port 1 (P1-0~P1-3) pins, data from a
maximum of 4x16=64 keys can be
input. An A/D comparator with a
programmable 3bit threshold level is
used as the input circuit.
Input is selectable between pull-down,
pull-up, or high impedance, making it
possible to construct different types of
key matrices. These key input ports may
also be used as a sequential compare
method 4-channel, 3bit A/D converter.
The WAIT mode is released when high
level is applied to key input ports set to
pull-down.
RIN1 Com parator
Refe rence
voltage
2001 -06-1 9
TOSHIBA
TC9317F
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
P1-0/KR12
P1-3/KR15
Input/output
port 1/Key
return timing
output port
The input and output of these 4bit l/O
ports can be programmed in 1bit units.
Can be programmed to output key
matrix timing signals. To form the key
matrix, load resistance has been built
into both the N-channel and P-channel
sides. A key matrix combined with the
LCD segment output can be formed, as
well as a push-key matrix that does not
need a key matrix diode.
By altering the input to I/O ports set to
input, the CLOCK STOP and WAIT modes
can be released, and the MUTE bit of
the MUTE pin can be set to "I".
DC-REF
P2-3 / PWM
l/O port 2/A/D
analog voltage
/A/D analog
voltage input
/Reference
voltage input
/PWM output
4bit l/O ports.
Input and output may be programmed
in 1bit units.
Pins P2-0 through P2-2 can also be used
for analog input to the built-in 6bit, 2-
channel A/D converter.
Conversion time of the built-in A/D
converter using the successive
comparison method is 280ps. The
necessary pin can be programmed to A/
D analog input in 1bit units, and P2-2
can be set to the reference voltage
input. Internal power supply (VDD) or
constant voltage (VEE) can be used as
the reference voltage. In addition,
constant voltage (VEE) can be input to
the A/D analog input so battery
voltage, etc., can be easily detected. The
reference voltage input, for which a
built-in operational amp is used, has
high impedance.
Pin P2-3 can also take over the output
of the built-in 12bit PWM. The PWM
output is a continuous 73.26Hz pulse,
whose duty is converted in 256 steps
(8bit). In addition, a further 4bit are
output every 16 PWM pulse cycles
(218.5ms).
The A/D converter, PWM output, and
their control are all executed by
program.
to A/D converter
(P2-3 pin is excluded)
2001 -06-1 9
TOSHIBA
TC9317F
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
P3-0/SI
P3-1/SO
P3-2 /Ttfit"
P3-3/BUZR
l/O port3
/Serial data
/Serial data
output
/Serial clock
input-output
/Buzzer output
4bit I/O ports, whose input/output can
be programmed in 1bit units.
Pins P3-0 through P3-2 also function as
input/output pins for the serial interface
circuit (SIO).
The SIO serially inputs 4bit or 8bit data
from the SI pin at the 'fRTit- pin's clock
edge, and serially outputs data from the
SO pin. For the serial operation clock
(TCR) there is an internal/external
option, and a rising/falling shift option.
Moreover, because the SO pin can be
switched to serial input (SI), LSI control
and communication between controllers
is simple. All SIO input pins use built-in
Schmitt circuits.
The P3-3 pin also functions as the
output for the built-in buzzer circuit.
The buzzer sound can be output in 254
different tones between 18.75kHz and
147Hz, and at a duty of 50%.
The SIO, the buzzer output, and all
associated controls can be programmed.
l/O port4
HO port6
The input and output of these 16bit I/O
ports can be programmed in 1bit units.
Muting output
1bit output port. Normally, this port is
used for muting control signal output.
This pin can set the internal MUTE bit to
"1" according to a change in the input
of I/O port 1. MUTE bit output logic
can be changed; PPL phase difference
can also be output using this pin.
TEST mode
control input
Input pin used for controlling TEST
mode. High level indicates TEST mode,
while low level indicates normal
operation. The pin is normally used at
low level or no-connection (NC). (A pull-
down resistor is built in).
2001 -06-1 9
TOSHIBA
TC9317F
PIN No. SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
64 IFIN/IN1/
IF signal input/
Input port
/Frequency
measuring input
IF counter's f signal input pin for
counting the IF signals of the FM and
AM bands and detecting the automatic
stop position.
The input frequency is between
0.35--12MHz (0.2Vp-p-min). A built-in
input amp and C coupling allow
operation at Iow-level input.
The IF counter is a 20bit counter with
optional gate times of 1, 4, 16, and
64ms. 20 bits of data can be readily
stored in memory.
The IF counter can also be used as a
timer when not being used as an IF
counter.
This input pin can be programmed for
use as an input port (IN port). It can
also be used to measure the frequency
with the IF counter (SCIN). CMOS input
is used when the pin is set as an IN
Note: When the pin is set for SCIN, use
DC coupling and input a square
65 DO1/OT
66 D02
comparison
output
/Output port
comparison
output
PLL's phase comparison tri-state output
When the programmable counter's
prescaler output is higher than the
reference frequency, output is at high
level. When output is lower than the
reference frequency, output is at low
level. When output equals the reference
frequency, high impedance output is
obtained.
Because DOI and D02 are output in
parallel, optimal filter constants can be
designed for the FM/ VHF and AM
bands.
Pin DOI can be programmed to high
impedance or programmed as an output
port (OT). Thus, the pins can be used to
improve Iock-up time or used as output
ports.
2001 -06-1 9
TOSHIBA
TC9317F
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
HOLD mode
control input
Input pin for request/release HOLD
Normally, this pin is used to input radio
mode selection signals or battery
detection signals.
HOLD mode includes CLOCK STOP mode
(stops crystal oscillation) and WAIT mode
(halts CPU). Setting is implemented with
the CKSTP instruction or the WAIT
instruction. When the CKSTP instruction
is executed, request/release of the HOLD
mode depends on the internal MODE
bit. If the MODE bit is "0" (MODE-O),
executing the CKSTP instruction while
the HOLD pin is at low level stops the
clock generator and the CPU and
changes to memory back-up mode. If the
MODE bit is "1" (MODE-1), executing
the CKSTP instruction enters memory
back-up mode regardless of the level of
the HOLD pin. Memory back-up is
released when the HOLD pin goes high
in MODE-O, or when the level of the
'Fit5Li5 pin level in MODE-1.
When memory back-up mode is entered
by executing a WAIT instruction, any
change in the HtiLD pin input releases
the mode.
In memory back-up mode, current
consumption is low (below IPA), and all
the output pins (e.g., display output,
output ports) are automatically set to
low level.
Prescaler control
output
Output pin that controls the switching
of two modulus prescaler ratios between
1/15 and 1/16.
When the programmable counter is used
in pulse swallow frequency division
mode, this output pin controls the
external prescaler ratio.
High:1/16, Low:1/15
2001 -06-1 9
TOSHIBA
TC9317F
PIN No.
SYM BOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
Power-supply
Pins to which power is applied.
Normally, VDD=1.8--3.6V (3.0V typ.) is
applied.
In back-up mode (when CKSTP
instructions are being executed), voltage
can be lowered to 1.0V. If voltage falls
below 1.5V while the CPU is operating,
the CPU stops to prevent malfunction
(STOP mode). When the voltage rises
above 1.5V, the CPU restarts.
STOP mode can be detected by checking
the STOP F/F bit. If necessary, execute
initialization or adjust clock by program.
When detecting or preventing CPU
malfunctions using an external circuit,
STOP mode can be invalidated and
rendered non-operative by program. In
that case, all four bits of the internal
TEST port should be set to "1".
If more than 1.8V is applied when the
pin voltage is 0, the device's system is
reset and the program starts from
address "O". (Power on reset)
Note: To operate the power on reset,
the power supply should start up
in 10--100ms.
programmable
counter input
Programmable counter input pin for the
16bit pulse swallow frequency division
method.
This pin inputs the external prescaler
output signals.
A built-in input amp and C coupling
allow operation at Iow-level input.
Note: When in the PLL OFF mode or
when set to AMIN input, the input
is pulled down.
2001 -06-1 9
TOSHIBA
TC9317F
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
AM local
oscillator signal
Programmable counter input pin when
using the 12bit direct dividing method.
Normally, the pin inputs AM band local
oscillation signals.
Built-in input amp operates with low-
level input using a C coupling.
Note: When in PLL OFF mode or when
set to FMIN input, the input is
pulled down.
Reset input
Input pin for system reset signals.
Reset takes place while at low level; at
high level, the program starts from
address "O".
Normally, if more than 1.8V is supplied
to VDD when the voltage is 0, the
system is reset (Power on reset).
Accordingly, this pin should be set to
high level during operation.
Crystal oscillator
Crystal oscillator pins
A reference 75kHz crystal oscillator is
connected to the XIN and XOUT pins.
The oscillator stops oscillating during
CKSTP instruction execution.
The VXT pin is the power supply for the
crystal oscillator. A stabilizing capacitor
(0.1/st typ.) is connected.
Voltage doubler
boosting pin
Voltage doubler boosting pin for driving
the LCD.
A capacitor (0.1-3.3pF typ.) is connected
to boost the voltage.
The VLCD pin outputs voltage (3.0V),
which has been doubled from the
constant voltage (VEE: 1.5V) using the
capacitors connected between C1 and
C2. That potential is supplied to the LCD
drivers. If the internal VLCD OFF bit is
set to "1" by program, an external
power supply can be input through the
VLCD pin to drive the LCD.
At this time, the VLCD/2 potential,
whose VLCD voltage is divided using
registers, is output from the C2 pin.
f VLCD
2001 -06-1 9
TOSHIBA TC9317F
PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
1.5V constant voltage supply pin for
driving the LCD.
Constant voltage A stabilizing capacitor (0.47pF typ.) is
80 VEE supply pin connected. This is a reference voltage for -
the A/D converter, key input, and the
LCD common output's bias potential.
(Note) 1. When the device is reset (voltage higher than 1.8V, or when RESET=Iow -9 high)
I/O ports are set to input, the pins for LCD output and I/O ports are set to LCD
output, the pins for I/O ports and additional functions (e.g., SIO, A/D converter)
are set to l/O port input pins, while the lFlN/IN1/SCIN pins become IF input pins.
. When in PLL OFF mode (when the four bits in the internal reference ports all
show "1"), the lFlN/SCIN and FMIN/AMIN pins are pulled down, and DOI and
D02 are at high impedance.
. When in CLOCK STOP mode (during execution of CKSTP instruction), the output
ports and the LCD output pins are all at low level, while the constant voltage
circuit (VEE), the voltage doubler circuit (N/LCD), and the power supply for the
crystal oscillator (VXT) are all off.
When the device is being reset, the contents of the output ports and internal
ports are undefined and initialization by program is necessary.
. If the pins for LCD output and HG ports are set to I/O ports, because the VLCD
potential is used as the power supply for their input and output, attention must
be paid to the input potential when the ports are set to input, and to the high-
level output current when set to output.
12 2001-06-19
TOSHIBA TC9317F
DESCRIPTION or OPERATION
(D CPU
The CPU consists of: program counter, stack register, ALU, program memory, data memory, G-
register, data register, carry F/F and judge circuit.
Program counter (PC)
This counter consists of a 12bit binary up-counter and is for addressing program memory (ROM).
It is cleared by system reset and a program starts from address 0.
Normally, when one instruction is executed, it is incremented by one.
However, when JUMP or CAL instruction is executed, the address designated in the operand of
the instruction will be loaded.
When an instruction having the skip function (AIS, SLTI, TMT, RNS instruction, etc.) is executed
and, if the result is a condition to be skipped it is incremented by two and skips next
instruction.
MSB LSB
PCI 1 PCI 0 PC9 PC8 PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO
. Stack register (STACK)
It is a register consisting of 2x12 bits.
When subroutine call instruction is executed, a value of the contents of program counter+ l,
that is, return address is stored in this register.
The contents of this register is loaded into program counter when return instruction (RN, RNS
instruction) is executed.
This stack level is 2 levels and the nesting also is 2 levels.
It has the following functions: binary 4bit parallel add-subtraction, logical operation, comparison,
multiple bit judge.
The contents of data memory are directly treated in every operation because this CPU has no
accumulator.
13 2001-06-19
TOSHIBA TC9317F
4. Program memory (ROM)
It consists of 16 bitsx4096 steps and stores programs. The usable address range is 4096 steps
from address 000H to FFFH.
There is no concept of page and field in program memory, JUMP and CAL instructions are freely
usable in 4096 steps. Any address in program memory can be used as data area. When DAL
instruction is executed, the contents of 16 bits are loaded into data register.
(Note) Set the data area in program memory to an address outside the program loop.
(Note) When DAL instruction is executed, the address of program memory designat able as
data area is within 1024 steps from OOOH to 3FFH.
FFFH OOOH
ROM 16bitx4096 steps
409 6 ste ps
5. Data memory (RAM)
It consists of 4bitx256 words and is used for data storage. These 256 words are expressed by
the row address (4 bits) and column address (4 bits). 192-words in data memory (row
address=4H--FH address) are indirectly addressed by G-register. For this reason, when processing
data within this area, it is necessary to process after the row address is designated by G-register
in advance.
The address 00H~0FH in data memory is called general register. This is also usable for
designating only the column address (4 bits). These 16 general registers are used for operation
and transfer with the data memory and are also usable as ordinary data memories.
(Note) The column address (4 bits) designating general register become the register number
of general register.
(Note) It is possible to designate all row addresses (0H--FH address) indirectly by G-register.
14 2001-06-19
TOSHIBA TC9317F
COLUMN ADDRESS : DC
0123456789ABCDEF
(*) l 0 General register
g: l 1 (One of the 00H~0FH address)
tf] I 2
tlt5 5
To designate row 9
addresses (4H-FH)
indirectly by G-register A
address = OH-FH -
designating row )
s ' I s . I .
indirect y IS possib e RAM (4bitx256 words)
. G-Register (G-REG)
It is a 4bit register for addressing row addresses (DR=4H--FH address) of 192 words of data
memory. The contents of this register are valid when MVGD/MVGS instruction is executed and
have nothing to do when other instructions are executed. This register is used as one port and
the contents are set when OUT1 instruction of HO instructions is executed. (Refer to Register
Port, item 1.)
. Data register (DATA REG)
It is a register consisting of 1x 16bit. When DAL instruction is executed, the 16bit data of any
address between 000H--3FFH in program memory is loaded. This register is treated as one of
port and when INI instruction of I/O instructions is executed, it's contents are loaded into data
memory by 4 bits unit. (Refer to register port, item2.)
. Carry F/F (CF/F)
This is set if carry or borrow is generated as a result of execution of the calculation instruction
and reset if neither is generated.
The contents of carry F/F changes only when addition/subtraction instruction is executed and
remain unchanged when other instructions are executed.
15 2001-06-19
TOSHIBA TC9317F
9. Judge circuit (J)
When an instruction with the skip function is executed, it judges the skip condition. When the
skip condition is satisfied, the program counter is incremented by two and the subsequent
instruction is skipped.
There are 29 instructions having the skip function. (Refer to item 11, Instruction Function, Table
of Operational Instruction marked "*".)
10.Table of instruction set
Total 62 kinds of instruction sets are available, and instructions are all one word.
These instructions are expressed in a 6bit instruction code.
HIGH ORDER 00 01 10 11
ORDER 4BIT 2BIT 0 1 2 3
0000 0 AI M, I AD r, M TMTR r, M SLTI M, I
0001 1 AIS M, I ADS r, M TMFR r, M SGEI M, I
0010 2 AIN M, I ADN r, M SEQ r, M SEQI M, I
0011 3 AIC M, I AC r, M SNE r, M SNEI M, I
0100 4 AICS M, I ACS r, M LD r, M TMTN M, N
0101 5 AICN M, I ACN r, M ST M, r TMT M, N
0110 6 ORIM M, I ORR r, M MVGD r, M TMFN M, N
0111 7 ANIM M, I ANDR r, M MVGS M, r TMF M, N
1000 8 SI M, I su r, M IN1 M, c
1001 9 SIS M, I sus r, M IN2 M, c
1010 A SIN M, I SUN r, M CALL ADDRI IN3 M, c
1011 B SIB M, I SB r, M OUT1 c, M
1100 c SIBS M, I SBS r, M OUT2 c, M
1101 D SIBN M, I SBN r, M OUT3 c, M
1110 E XORI M, I XORR r, M JUMP ADDR1 DAL ADDR2, r
RN, RNS, WAIT
1111 F MVIM M,I MVSR M1, M2 CKSTP, NOOP
16 2001-06-19
TOSHIBA TC9317F
11.Table of functions and operation of instruction
(Explanation of symbols in the table)
M : Data memory address
Generally one of data memory addresses 00H~3FH
r : General register
One of data memory addresses 00H~0FH
PC : Program counter (12bit)
STACK : Stack register (12bit)
G : G-register (4bit)
DATA : Data register (16bit)
I : Immediate data (4bit)
N : Bit position (4bit)
- : ALL "0"
C : Port code No. (4bit)
CN : Port code No. (4bit)
RN : General register No. (4bit)
ADDR1 : Program memory address (12bit)
ADDR2 High order 6bit of program memory address in page 0
Ca : Carry
b : Borrow
IN1--lhl3 : Port treated by execution of |N1~|N3 instruction
OUT1--OUT3 : Port treated by execution of OUT1--OUT3 instruction
( ) : Contents of register or data memory
[ lc : Contents of port indicated by Code No. C
[ I : Contents of data memory shown by the contents of register or data
memory
[ ]p : Contents of program memory (16bit)
IC : Instruction code (6bit)
.7.o( : Instruction with skip function
DC : Data memory column address (4bit)
DR : Data memory row address (2bit)
17 2001-06-19
TOSHIBA
TC9317F
SKIP MACHINE LANGURAGE
INST. EXPLANATION OF EXPLANATION OF (16bit)
GR. MNEMONIC 12fi- FUNCTION OPERATION IC A B c
6bit 2bit 4bit 4bit
Al M,l Add immediate data Me-iM) +I 000000 DR DC I
to memory
Add immediate data
AIS M, I Fd. to memory, then skip M50“) H 000001 DR DC I
. Skip if carry
if carry
Add immediate data
AIN M, I .7.4 to memory, then skip yt-ly) +I 000010 DR DC I
. Skip if not carry
if not carry
AIC M, I Add immediate data Me-(M) +I+ca 000011 DR DC I
to memory with carry
Add immediate data h/le-IM) +I+ca
._. AICS hll,l .)K. to memory with carry, . . 000100 DR DC I
Addition h ki if Skip if carry
ins_truc- t en s Ip I carry
tion Add immediate data Me(M) +I+ca
AICN h/l,I .yd. to memory with carry, . . 000101 DR Dc I
. . Skip if not carry
then skip if not carry
AD r M Add memory to re-(r) + (M) 010000 D D R
' general register R C N
Add memory to
ADS r, M .)K. general register, then T.(r). + (M) 010001 DR DC RN
. . Skip if carry
skip if carry
Add memory to
ADN r, M .7.4 general register, then T.(r). + (M) 010010 DR DC RN
. . Skip if not carry
skip if not carry
Add memory to
ACr, M general register with re-(r) + (M) +ca 010011 DR Dc RN
Add memory to
ACS r, M .)K. general register with T.(r). + (M) +ca 010100 DR DC RN
. . Skip if carry
carry,then skip if carry
Add memory to
. general register with re-(r) + (M) +ca
ACN r, M carry, then skip if not Skip if not carry 010101 DR DC RN
2001 -06-1 9
TOSHIBA
TC9317F
MACHINE LANGURAGE
borrow, then skip if
not borrow
Skip if not borrow
INST. SKIP EXPLANATION OF EXPLANATION OF (16bit)
GR. MNEMONIC 1gt FUNCTION OPERATION IC A B c
6bit 2bit 4bit 4bit
Subtract immediate
SI M, I data from memory h/le-tM) -l 001000 DR DC I
Subtract immediate
SIS M, I .yd. data from memory, yt-ty), " 001001 DR DC I
. . Skip if borrow
then skip if borrow
Subtract immediate
. data from memory, Me-(M) -l
SIN M, I then skip if not Skip if not borrow 001010 DR DC I
borrow
Subtract immediate
SIB M, I data from memory Me-(M) -l-b 001011 DR Dc 1
with borrow
Subtract immediate
SIBS hll,I .yd. dire from memory il/lt-ly). -l-b 001100 DR DC I
Subtrac- with borrow, then Skip if borrow
tion skip if borrow
instruc- Subtract immediate
. = data from memory Me-(M) -l-b
tion SIBN M, I X with borrow, then Skip if not borrow 001101 DR DC I
skip if not borrow
Subtract memory from
SUr, M general register re-(r) - (M) 011000 DR Dc RN
Subtract memory from
SUS r, M .yd. general register, then 1;; l bhrrIOW 011001 DR DC RN
skip if borrow p
Subtract memory from
SUN r, M .)K. general register, then rfr.(r). (M) 011010 DR Dc RN
. . Skip if not borrow
skip if not borrow
Subtract memory from
SB r, M general register with rs-(r) - (M) -b 011011 DR Dc RN
borrow
Subtract memory from
tfd general register with re-(r) - (M) -b
SBS r, M X borrow, then skip if Skip if borrow 011100 DR DC RN
borrow
Subtract memory from
SBN r, M X general register with re-(r) - (M) -b 011101 DR DC RN
2001 -06-1 9
TOSHIBA
TC9317F
SKIP MACHINE LANGURAGE
INST. EXPLANATION OF EXPLANATION OF (16bit)
GR. MNEMONIC 1gt FUNCTION OPERATION IC A B c
6bit 2bit 4bit 4bit
.w. Skip if memory is less . .
SLTI M,l .yd. than immediate data Skip if(M)Skip if memory is
SGEI M, I .)K. greater than or equal Skip if(M) 2| 110001 DR Dc I
C to immediate data
t,'i'gr" Skip if memory is
instruc- SEQI M, I X equal to immediate Skip if(M) =l 110010 DR Dc I
tion data
Skip if memory is not
SNEI M, I .)K. equal to immediate Skip if(M) #:l 110011 DR DC I
Skip if general
SEQ r, M yd. register is equal to Skip if (r) = (M) 100010 DR Dc RN
memory
Skip if general
SNE r, M .yd. register is not equal Skip if (r) = (M) 100011 DR Dc RN
to memory
Load memory to
LD r, M general register re-(M) 100100 DR Dc RN
Store general register
T M M 1 1 1 D D R
S , r to memory e-(r) 00 0 R c N
T f Move memory to
112235113 MVSR M1, M2 memory in the same (DR, DCI)e-(DR, DC2) 011111 DR Dc1 DC2
tion row
MVIMM, I Move immediate data ME-l 001111 DR Dc I
to memory
Move memory to
destination memory
MVGD r, M referring to G-register [(G),(r)le-(M) 100110 DR DC RN
and general register
Move source memory
referring to G-register
MVGSM, r and general register Me-[(G),(r)l 100111 DR DC RN
to memory
'23:? |N1 M, c Input lN1 port data Me-[lhl1lc 111000 DR DC CN
output to memory
ins_truc- Output contents of
tion OUT1C, M memory to OUT1 port [OUTIlce-(M) 111011 DR DC CN
20 2001-06-19
TOSHIBA
TC9317F
SKIP MACHINE LANGURAGE
INST. EXPLANATION OF EXPLANATION OF (16bit)
GR. MNEMONIC 12fi- FUNCTION OPERATION IC A B c
6bit 2bit 4bit 4bit
Input IN2 port data
IN2 M, C to memory Me-flhl2lc 111001 DR DC CN
Input Out
put contents of
03:: t OUT2 C, M memory to OUT2 port [OUT21ce-(M) 111100 DR DC CN
instruc- IN3 M, c Input lN3 port data Me-fmII: 111010 DR DC CN
tion to memory
Output contents of
OUT3 C, M memory to OUT3 port [OUT31ce-(M) 111101 DR DC CN
ORR r M Logical OR of general re-(r) (M) 010110 D D R
' register and memory V R C N
Logical AND of
ANDR r, M general register and re-(r)A(M) 010111 DR Dc RN
memory
Logical ORIM h/l,l Log.ic.al OR.°fmem°ry h/R-ON/l)) 000110 DR DC I
opera- and immediate data
tion Logical AND of
instruc- ANIM M, I memory and Me-(M)Al 000111 DR Dc I
tion immediate data
Logical exclusive OR
IXORIM M, of memory and h/le-tlvl)) 001110 DR DC I
immediate data
Logical exclusive OR
XORR r, M of general register re-(r) 69 (M) 011110 DR Dc RN
and memory
Test general register
'."e; bits by memory bits, Skip if r[N (M)]
TMTR r, M .)K. then skip if all bits =all "1" 100000 DR DC RN
specified are true
Bit Tast general regis1er . .
judge TMFR r, M X bits by .me.m°ry lits, Skip if r[N(M)] " " 100001 DR DC RN
instruc- then skip if all bits =all 0
tion specified are false
Test memory bits,
TMT M, N X then skip if all bits Skip if M(N) =all "1" 110101 DR DC N
specified are true
Test memory bits,
TMF M, N X then skip if all bits Skip if M(N) =all "o" 110111 DR Dc N
specified are false
2001 -06-1 9
TOSHIBA
TC9317F
SKIP MACHINE LANGURAGE
INST. EXPLANATION OF EXPLANATION OF (16bit)
GR. MNEMONIC 12fi- FUNCTION OPERATION IC A B c
6bit 2bit 4bit 4bit
Test memory bits, . .
TMTN M, N X then not skip if all Skip if (r,?]),, 110100 DR DC N
Bit . . . =not all 1
judge bits specified are true
instruc- Test memory bits, Ski if M (N)
tion TMFN M, N ).k. then not skip if all p " " 110110 DR DC N
. . . =not all 0
bits specified are false
. STACIG-(PC) +1 and .
CALL ADDR1 Call subroutine PG-ADDRI 1010 ADDR1 (12bit)
Sulyou- Return to main
. tine RN . PC_STACK) 111111 00 - -
Instruc- routine
tion Return to main
RNS .yd. routine and skip PCe-(STACK)and skip 111111 01 - -
unconditionally
instruc- JUMP ADDR1 mm?” the address PG-ADDR, 1011 ADDR1 (12bit)
tion specified
Load program
DAL ADDR2, r memory in page 0 to aAT::[:DDR2+ (r)] P 111110 ADDR2 RN
DATA register p g (6bit)
At P= "0" H, the
condition is CPU
Other 21/213159 (Soft wait
instruc- . . .
tion WAIT P At P="1" H, except Wait at condition P 111111 10 0000 P
for clock generator,
all function is waiting
(Hard wait mode)
Stop clock generator
CKSTP Clock generator stop in m=uon 111111 10 1000 -
NOOP No operation - 111111 11 - -
(Note 1) Low order 4 bits out of the program memory address 10 bits designated by DAL
instruction are to be indirectly address according to contents of the general register.
DAL instruction execution time is 80ps (2 machine cycles).
(Note 2) MVGS instruction execution time is 80ps (2 machine cycles).
2001 -06-1 9
TOSHIBA
C) IIO map
TC9317F
All ports within the device are expressed by a matrix of 6 HO instructions (OUT1--3 instruction,
IN1--3 instruction) and a 4bit code number.
The allocation of these ports is described as I/O map in the following page. In this l/O map, port
names treated in execution of I/O instructions are assigned on the axis of ordinates and port code
numbers on the axis of abscissas. The G-register and data register are treated also as ports.
The OUT1--3 instruction and lhll--3 instruction are designated at an output port and input port,
respectively.
(Note 1) The oblique lined ports shown on the I/O map are actually not existed in the device.
If data are outputted to a non-existing output port when an output instruction is
executed, other ports or the contents of data memory are not especially affected.
If a non-existing input port is specified when an input instruction is executed, the
contents loaded to data memory is all "I".
(Note 2) Ports with *mark out of output ports on the I/O map are unused ports. Data
outputted to these ports will become "don't care".
(Note 3) The contents of the ports expressed by 4 bits, Y1 corresponds to LSB of data of the
data memory and Y8 correspond to MSB.
Ports that are designated by 6 HO instructions and No. C are expressed in coding as follows.
¢l£/_lenlgl
Describing 6 kinds of I/O instructions with 1-3.
l l, The contents of select port (indirectly specified data, 0-F[HEX])
IIO instructions operand CN (0~F[HEX])
l/O Instruction
Describes IIO port.
K : Input port (1N1~|N3 instructions)
L : Output port (OUT1~OUT3 instructions)
(Example) The G-register setting is allotted in the code 'T'' of OUT1 instruction. At this time
the encoded expression is 'HLIF''.
2001 -06-1 9
2001 -06-1 9
I/O map
OUT1 INSTRUCTION
OUTZ INSTRUCTION
0UT3 INSTRUCTION
|N1 INSTRUCTION
|N2 INSTRUCTION
|N3 INSTRUCTION
Y1IY2IY4IY3
Y1IY2IY4IY8
Y1] Y2 IY4
Y1IY2|Y41Y8
IF offset
1 A/D control
l/0—1 data
IF control dJaTta
xA/Duata
I f 0-1, dat'a
AD SELOI AD SEL1 IREF SELOIREF SEL1
—oI-1I-2
BUSY I Manual I OVER
ADO [Am I AD2
-oI—1I—2I—3
Programmable counter select
A / 0 control
I/O-2 data
IF data
A/D data
I /0-2 data
STA IDCREF 0NIAD1 ONIADZ ON
-oI—1I—2
f0| f1
I f2 If3
ADA I ADS I BUSY
—o|—1I-2I-3
Programmable counter
SIO control
I/0-3 data
IF data
edge I SCVK-INV Iﬁ-I/ﬁ suo ON
I-1I-2
f4I f5
I f6 If7
I/O—3 data
-oI-1I—2I—3
Reference port
SIO control *
I/O-4 data
IF data
SIO contorl data
l/O-4 data
STA | 504/6 I4/§ hit
—oI—1I—2
I ﬁt) If11
BUSY ICOUNTISIO F/ F
—oI—1I—2I-3
IF counter control
SIO output data
I/O-5 data
IF data
SIO input data
I/O-5 data
IIF/WTI
soIs1IszI53
-oI-1I-2
f13 I in [HS
I51I52
-oI-1I—2I—3
IF counter control
SIO output data
|/O-6 data
IF data
SI input data
I / 0-6 data
STA/ﬁrP
Manual |
MI 55 saIs7
-oI—1I—2
f16 I f17
I ns If19
IssIsa
-oI-1I-2 —3
MUTE OUT
Timer reset TEST data
1/0-7 data
I POL [UNLOCK
2HzF/FI Timer #4 I #5
-oI—1I—2
| /0—7 data
2H2 F/FI 10Hz I 100Hz
—oI-1I-2I—3
UNLOCK RESET
001 control
Key scan start
I/O-S data
UNLOCK
KS1 I K52 I K54 I KS8
—oI-1I-2
F/F IENABLE
Key scan digit
| /0—8 data
KR1 I KRZI KR4 IKRg
- I-1I—2I—3
PWM/BUZR data
Key scan and
|/0-9 data
UNLOCK da1a
Key input data
| / 0-9 data
PWo / BO
PW1/B1
Isz / BZI PW3 / 33
KEI I KEZ | KE4 | KE8
-oI—1|—2
UN1I UN2 |UN3
IK1IK2
—oI-1I—2I—3
PWM IBUZR data
Key scan co ntrol
I/0-1O data
PW4 / B4
PW5/85
|PW5/B6IPW7/B7
KCO I um I KC2 TKc3
—oI—1I—2
Key scan data
I/O-10 data
IK1IK2
—oI—1I—2I—3
PWM data
Key scan data select
l/O-11 data
KSD1 I KSDZ I KSD4 I KSD8
—oI—1I-2I—3
I/O-11 data
- I-1I-2I—3
PWM ON
BUZR 0N
Buffer
transfer
I/O-12 da1a
—oI—1I-2
HOLD 1
I /O-12 data
—o|—1I-2|-3
TEST data
I/0-13 data
DATA-reg
—oI—1I-2
d0| d1
| d2 |d3
1/0-13 data
—oI—1I—2I—3
SEG data select
IIO-14 data
DATA-reg
s1IszIs4Iss
—oI—1I—2I—3
d4] d5
I d6 Id7
|/0-14 data
-o -1-2 —3
SEG-‘l data
IIO control select
DATA-reg
COM1 I COMZ I COMB I SEG
I/O1II/02II/04Il/08
d8] d9
I d10 Id11
|N3 1 1 1
SEG-Z data
I/O control data
DATA-reg
com I com I COM3 I SEG
Io-oI |O-1 I IO-Z | IO-3
d12 | (113
I d14 |d15
T(9317F - 24
TOSHIBA
TC9317F
TOSHIBA TC9317F
C) Connection of crystal resonator
Connect a 75kHz crystal resonator to crystal oscillator terminal of the device (XIN, XOUT) as shown
below.
This oscillation signal is supplied to clock pulse generator, reference frequency divider and generates
various CPU timing signals and reference frequency signals. The crystal circuit uses voltage
(VXT= 1.3V Typ.) supplied from a built-in regular voltage circuit as power supply. Because of this, it
can stabilizes the crystal resonator and reduces the consumption current.
' (XOUTHXIN) (VXT) ,
' Q9 ta) 74 75 76 tr) '
CL CL Cx X'tal = 75kHz
J l CL=15pF Typ. Cx--th47pzF Typ,
(Note) Use a crystal oscillator of good starting characteristic such as low Cl value.
C) System reset
When "L'' level signal is input to the mrs-tT terminal or more than 0~1.8V is supplied to the VDD
terminal (Power on rest), system reset is applied to a device. After standby period of 100ms has
passed after system reset, a program will start from address 0.
Since it normally uses POWER ON RESET function, fix T1TiTri?t" terminal at "H" level.
(Note 1) During system reset and the subsequent stand-by period, LCD common and segment
outputs are fixed at "L'' level.
(Note 2) The internal ports shown in the following table are fixed after system reset, but the other
ports are not fixed. Accordingly it is necessary to initialize them by program.
Fixed internal port
PORT FIXED TO "0" PORT FIXED TO "1"
SCON bit (¢L14) _ Manual bit (¢L15) Reference port (¢L13)
IO, POL, UNLOCK bit (¢L16) MUTE bit (¢L16)
DO1control port (¢L17) IF/W (¢L14)
PWMON, BUZRON, PWM/BUZR, Transfer bit (¢L1B)
Test port (il-IC ¢L26)
CKSTP MODE bit (¢L1E)
AD control port (iL20,. ¢L21)
SIO control port HL22, ¢L23)
Timer port (¢K26)
Key scan start, control port (stL27, ¢L290~¢L295) Key scan end port (¢L28)
VLCD OFF bit (¢L2FF)
IO-l-IO-ti IO control port (/L3FO--/L3F5) DISP OFF bit (¢L2FF)
SEG bit (LCD/IO switching bit
; fH-2E0-- /l-2EFs ¢L2F0~¢L2FE)
25 2001-06-19
TOSHIBA TC9317F
O Backup mode
When CKSTP or WAIT instruction is executed, the following three kinds of backup modes are
selected.
1. Clock stop mode
It is a function to stop operating system and holds the operation state of device just before stop
with low current consumption (below IPA at VDD=3.0V). At this time the crystal oscillation
stops and the LCD display driver terminal and output ports are all fixed at "L" level or OFF
state automatically. The supply voltage can be reduced to 1.0V in this clock stop mode.
Program stops at the address of executing CKSTP instruction when CKSTP instruction is executed.
If clock stop mode is released, the next address is executed after lapse of stand-by time of
100ms.
Clock stop mode setting
The clock stop mode setting has two kinds of mode. The setting is selected by CKSTP
MODE bit. This bit is accessed when OUT1 instruction designated [CN=EH] in the operand
is executed.
Y1 Y2 Y4 Y8
t 0 : MODE-O
CKSTP mode setting
1 : MODE-1
¢L1E * * *
MODE-O
In this mode, CKSTP instruction is executed while HOLD terminal is "L" level, it becomes
clock stop mode. If CKSTP instruction is executed while HOLD terminal is "H" level, it does
the same operation as that of NOOP instruction.
MODE-1
In this mode, CKSTP instruction is executed regardless of the level of HOLD terminal, it
becomes clock stop mode.
(Note) The PLL will be off state while CKSTP instruction is executed.
Released condition of clock stop mode
MODE-O
When clock stop mode is set by this mode, the clock stop mode is released when HOLD
terminal is "H" level or changing the input condition of HO port (P1-0~3) set at input
MODE-I
When clock stop mode is set by this mode, the clock stop mode is released by HOLD
terminal or changing the input condition of I/O port (P1-0~3) set at input port.
26 2001-06-19
TOSHIBA TC9317F
(3) Clock stop mode timing
C) MODE-O
HOLD terminal :\—R—I
XOUT terminal ll ll ll I
CPU operation -i-nu-oock stop T atand-by
(Clock stop mode release)
CKSTP instruction K R, ll k
NOOP operation CKSTP execution NOOP operation
I CPU operation
It sets to clock stop mode when CKSTP instruction is executed while HOLD terminal
is "L" level.
© MODE-1
HOLD terminal 'l , 'l
XOUT terminal lllllllllllllll] " _i-azazpttinR-
_ I I CPU I Clock stop
CPU operation -t"-clock stop-C-""-','":);;);:,,, I
CKSTP instruction tlt ll ll C
(Release clock stop mode by changing the input condition)
(It sets to clock stop mode whenever CKSTP instruction is executed.)
(4) Example of circuit (example of MODE-O circuit)
VDD @ _ POWER
Example of backup circuit using battery Example of backup circuit using capacitor
27 2001-06-19
TOSHIBA TC9317F
2. Wait mode
This mode stops system and holds the operation state of a device just before stop and therefore
reduces current consumption. In this mode there are two kinds as follows:
0 HARD WAIT mode
It SOFT WAIT mode
Program stops at the address of executing WAIT instruction when WAIT instruction is executed.
If WAIT mode is released, the next address will be executed without stand-by time.
(1) SOFT WAIT mode
It stops only CPU operation internal a device when WAIT instruction is executed at
designated operand port [P=0H]. At this time others such as crystal oscillator and display
circuit, etc. operate properly. SOFT WAIT mode is efficient in reducing current consumption
for use in the program of clock function at clock operation.
(Note) Current consumption differs depending on the program.
(2) HARD WAIT mode
It stops all operations except crystal oscillation circuit when WAIT instruction is executed at
designated operand port [p=1H]. For this reason, this mode can reduce further current
consumption than SOFT WAIT mode. At this time, CPU and display circuit stop operation
and LCD display output terminals are all fixed at "L" level automatically.
(10pA Typ. at VDD=3V)
(3) WAIT mode setting
It will be in waiting condition whenever WAIT instruction is executed.
(Note) It will be PLL off condition during HARD WAIT mode but not during SOFT WAIT
mode. Therefore, it is necessary to set PLL off condition by program before SOFT
WAIT mode is executed.
(4) Released condition of WAIT mode
The WAIT mode is released under one of following conditions;
1. When the input level of 'it5Ll5 terminal changes,
2. When "H" level is inputted to key input terminal (K0--K3) (only when key input mode)
3. When 2Hz timer F/F is set to "I", (only SOFT WAIT mode)
4. When input level of I/O port (P1-0~3) set in input port is changed,
3. HOLD input port
Y1 Y2 Y4 Y8
¢K1B HOLD 1 1 1
The Tl"t5Tt5' terminal is used as an input port. Data is read in the data memory when |N1
instruction designated [CN=BH] in the operand.
When this clock stop mode is set, it is necessary to access to this port before CKSTP instruction is
executed. It may not be clock stop mode when CKSTP instruction is executed without accessing
to this port.
28 2001-06-19
TOSHIBA TC9317F
C) Programmable counter
It consists of external 2-modulus prescaler, 4bit+ 12bit programmable counter and port to control
these. Programmable counter controls ON/OFF according to the contents of reference port.
1. Programmable counter control port
It is a port to control frequency division number, frequency division system and IF correction (IF
offset) at FM band.
Y1 Y2 Y4 Y8
¢L10 * +1 -1 FM
IF offset
Y1 Y2 Y4 Y8
Dividing method setting
ffl-ll #1 #2 * *
Programmable counter select
Programmable counter data
(LSB) Y1 Y2 Y4 Y8
¢L12 (PA) (PB) (PC) (PD)
- 0 P0 P1 P2 P3
1 P4 P5 P6 P7
2 P8 P9 P10 P1 1
3 P12 P13 P14 P15 (MSB)
(Note) Whenever accessing to ¢L12, the ¢L11 data is +1 incremented.
The frequency division system and IF offset are accesse by OUT1 instruction designated [CN=0H]
in the operand.
The frequency division number setting is accessed by OUT1 instruction designated [CN=1H, 2H]
in the operand and write to PA~PD bit (¢L12).
This port is divided by the programmable counter select port (¢L11) and the programmable
counter data corresponding to the select port is set by setting data to them.
After the programmable data select is set to "3", set the programmable counter data (P12--P15)
and all of P0--P15 data are updated. Because of this, make sure to access to P12-- P15 port and
set the P12--P15 port data at last even if changing only partially.
The programmable counter select is +1 incremented whenever accessing to the programmable
counter data (¢L12). Normally the setting can easily be done by setting "0" to the
programmable counter select port and accessing to the programmable counter data successively.
29 2001-06-19
TOSHIBA
TC9317F
. Setting of frequency division system
The pulse swallow system or the direct frequency division system are selected according to FM
At AM band mode, the direct frequency division system is selected. When SW band, FM band or
VHF/TV band mode, it selects the pulse swallow system which combines with external 2-modulas
prescalers of TD6134AF, TD7101F and TD7103F.
EXAMPLE OF OPERATION FREQUENCY
FM FREQul1ufhly/lsKoN RECEIVING FREQUENCY TE'mPJAL DIVISION NUMBER PRESCALER
BAND RANGE (Note 2)
o 9.”??? frequency MW/LW o.5~12MHz AMIN n None
division system
(1/15 or 1/16) (Note 1)
TD71 IF
Pulse swallow system SW 1.5--35MHz n 0
TD 1 4AF
1/4x(1/15 or1/16) (Note I) 6 3
1 P Is all s stem FM 50--150MH FMIN 4.n TD7101F
u e sw ow y z TD7103F
1/8x (1/15 or 1/16) (Note I) TD6134AF
Pulse swallow system VHF/TV 50~250MH2 8 n TD7103F
(Note 1) It indicates the input frequency range for each prescaler of TD6134F, TD7101F and
TD7103F.
(Note 2) The "n" denotes a programmed divided frequency value.
3. f correction function at FM band
In the pulse swallow system, the actual frequency division number can be :1 variable without
changing programmable frequency division value by nlF+1 port and AIF-1 port.
This is used for IF offset condition at FM band.
At the direct division system, the IF offset function does not operate.
AIF+1 AIF-1 FREQUENCY DIVISION FREQUENCY DIVISION
NUMBER (VHF) NUMBER (FM OR HF)
0 0 2n n
0 1 2. (n - 1) n -1
1 0 2. (n + 1) n +1
1 1 Inhibit Inhibit
2001 -06-1 9
TOSHIBA TC9317F
4. Setting of frequency division number
Set frequency division number of the program counter in binary number to P0--P15bit.
o The pulse swallow system (16 bits)
MSB LSB
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
215 20
The range of frequency division number setting (The pulse swallow system) n=210H-FFFFH (528-65535)
o The direct frequency division system (12 bits)
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 Asf' /
The range of frequency division number setting (The direct dividing system)n=10H-FFFH(16-4095) don't care
(Note) Since offset is not provided to the program counter,a programmed division number
will become an actual division number. However when a prescaler is used, the actual
dividing value will become 4 times of the programmed value in case of FM band
mode and 8 times at VHS/TV band mode.
(Note) In the direct frequency division system, the P0~P3 ports data (¢L11) become
unconcerned and P4 port are used as LSB.
5. Programmable counter circuit configuration
0 Circuit configuration of the pulse swallow system
The circuit consists of : 2-modulus prescaler (TD6134AF, TD7101F, TD7103F), 4bit swallow
counter and 12bit binary counter. At FM band, 1/4 divider is added to the front stage of the
prescaler and 1/8 divider is added at VHF/TV band. The diagram with prescaler (TD6134AF)
as shown below.
OVHF/FM
'ste, F/F
0,001/1F
(iii)0c111-h cm
0.001pt5 + 15 16 P0~P3
._"_@ DIVIDER $36
(h01/zF '
si-cis BUF. Ci)-5 ea swallow counter
Preset
TD6134AF f
programmable counter To phase comparator
P4-P15
TC9317F
31 2001-06-19
TOSHIBA TC9317F
0 Circuit configuration of direct frequency division system
In this case, the external prescaler is unnecessary and a 12bit programmable counter is used.
Preset
AMIN m 12bit programmable counter
_ TO phase comparator
(Note) Both FMIN and AMIN terminals have built-in an amplifier respectively, and are
operable at small amplitude with coupled capacitors. When the input terminal
not selected according to the frequency division system and PLL off mode
(Setting be reference port) the input is pull-down.
0 Reference frequency divider
This frequency divider generates 7 kinds of PLL reference frequency signals l, 3, 3.125, 5, 6.25, 12.5
and 25kHz by dividing external 75kHz crystal oscillation signal.
This frequency selection is executed by the contents of reference port. The selected signal is used as
reference frequency of the phase comparator as described below. According to the contents of the
reference port, PLL ON/OFF is performed.
l. Reference port
It is an internal port to select the 7 kinds of reference frequency signals. This port is accessed
when OUT1 instruction designated [CN=3H] in the operand (¢L13) is executed. When the
contents of reference port are all "1", the programmable counter, IF counter and reference
counter will stop and be in PLL off mode.
Y1 Y2 Y4 Y8
¢L13 R0 R1 R2 R3 R3 R2 R1 R0 REFERENCE
'---o FREQUENCY
Reference frequency select code 0 O 0 O 0 1kHZ
1, 0 0 0 1 1 3kHz
0 0 1 0 2 3.125kHZ
0 0 1 1 3 5kHz
0 1 0 0 4 6.25kHZ
0 1 0 1 5 12.5kHZ
0 1 1 0 6 25kHz
“v0 1 1 1 7 Inhibit -
"'"'1 1 1 o E Inhibit -
1 1 1 1 F PLL off mode
32 2001-06-19
TOSHIBA
TC9317F
C) Phase comparator & lock detection port
The phase comparator compares the phase between reference frequency signal supplied from
reference frequency divider and programmable counter dividing output to output the difference. It
controls VCO through a low pass filter so that the frequency and phase difference of these two
signals can be equivalent.
Because two tri-state buffers DOI and DO2 terminals are outputted from the phase comparator, the
filter constant can be optimally designed for each FM/VHF band and AM band.
The DO1 terminal is usable as general output terminal by means of DOI control port. This terminal
is capable of setting to high impedance. By using two terminals of DO1 & D02, it is possible to
improve the characteristics of PLL loop lock-up type, etc.
The lock detection port is capable of detecting the lock state of PLL circuit.
1. DOI control port and unlock detection port
_-- OT output control bit
0 : DO1 phase difference output
- DO1output impedance setup
1 : DO1 high impedance
.' OT output "L"
- OT output data bit
1 : OT output "H"
(Note) Invalid when setting Hz=1.
i: : DOI phase difference output
1 .' OT data out ut
(Note) Invalid when setting Hz=1. p
Whenever setting data to "I", it resets the unlock HF and unlock enable.
Y1 Y2 Y4 Y8
¢L17 UNLOCK DOI CONTROL
RESET OTC OT Hz
Y1 Y2 Y4 Y8
, K17 UNLOCK
F / F ENABLE
—’ Unlock enable
( : PLL unlock detection possible
0 : PLL unlock detection in waiting
1 : PLL unlock state detected
Unlock detection bit
0 : PLL normal operating (Unlock not detected)
33 2001-06-19
TOSHIBA TC9317F
Y1 Y2 Y4 Y8
UN1 UN2 UN3 0
- UN3 UN2
PHASE DIFFERENCE
Unlock data
0/zs- +6.66/xs
-13.3pr-0ps, + 6.66ps-- + 20ps
-13.3ps-- - 26.6ps, + 20ps-- + 33.3ps
- 26.6ps-- - 40ps, + 33.3ps-- +46.6ps
- 40ps- - 53.3ps, +46.6ps-- + 60ps
- 53.3ps-- - 66.6ps, + 60ps-- + 73.3ps
- 66.6/15" - 80ps, + 73.3ps-- + 86.6ps
under -80ps, Over +86.6ps
_\_\_\_\oooo
A—sOO—i—soo
AO—‘O—‘O—‘O
\IO‘U'l-bWN—‘o
Each OTC, OT and Hz bit of DOI control port is a control bit as below condition.
0 DOI output terminal is used as general output port.
0 DOI output terminal is set to high-inspendance state without outputting DOI output
phase difference.
These are set by program according to the specification.
The UNLOCK F/F bit detects the phase difference between the programmable counter divider
output and the reference frequency when the phase is about 180° shift. If the phase
difference does not accord at this time, that is, if in unlock state, UNLOCK F/F will be set.
UNLOCK F/F will be reset whenever setting "I" to UNLOCK RESET bit.
DO output detects the phase difference at the cycle of reference frequency. It's necessary to
access the UNLOCK F/F that its has more time than a cycle of reference frequency after
resetting the UNLOCK F/F. Because ENABLE bit is prepared. After confirm that UNLOCK
enable bit sets to "I",UNLOCK F/F is accessed.
UNLOCK enable bit is reset whenever setting "I" to UNLOCK RESET bit.
UNLOCK F/F detects when the phase is about 180° shift. It has the unlock data port that uses
at more accurate detection of the phase difference. This port detects the phase difference as
shown before table and is capable of detecting between -80pr- +86.6ps. However if setting
to high reference frequency (at 25, 12.5kHz setting), it can't detect under the half cycle of
the reference frequency.
UNLOCK data port detects data constantly in the phase width between - 180°~180° of the
reference frequency cycle. Normally after it is detected by UNLOCK F/F, the UNLOCK data
will be referred.
Control of each port and data loading are performed when OUT1/IN1 instruction designated
[CN=7H or 8H] in the operand is executed.
(Note) When PLL OFF mode, the DO output becomes high impedance. However when DOI
is set as output port (OT output), the output data will be outputted directly.
34 2001-06-19
TC9317F
TOSHIBA
2. Phase comparator and unlock port timing
DO output
Programmable
counter output
"L" level
Phase difference
Lock detection strobe
Execute unlock reset
Unlock F/F
Unlock enable
/W//)g//H(f//t
Unlock data
Count phase
difference
2001 -06-1 9
TOSHIBA TC9317F
3. Phase comparator and unlock port circuit construction
Reference frequency signal VDD
ase iii) D02
Programmable comparator
counter output
I k - -'
Selector 65
binary -' _ D DO1/OT
counter
UNLOCK UNLOCK t 1
ENABLE F/F
1 OTC OT
UNLOCK XIN
RESET “a
DO2 "dg"
DO1/OT Ciii "
In case of setting the filter constant for each band In case of using LPF in common
(Switching of filter constant is done
by setting DOI to high impedance.)
DC-DC V (3V)
converter cf
ii), 0.01/1F
To VCO variable . R- +3 - tt,
capacitor Cg 1/1F 4.7k0,
u. ce; DO
5 2SC4116GR 2.2141
c 2SK209Y
Example of active low pass filter circuit (for reference)
(Note) Since the above filter circuit is just an example, the actual circuit should be
examined and designed in accordance with the system band construction and
desired characteristics.
36 2001-06-19
TOSHIBA TC9317F
C) IF counter
It is a 20bit general IF counter for counting FM/AM intermediate frequency (IF) and can be used
for detecting the auto stop signal, etc. It also has a function to measure the cycle of a low
frequency pilot signal. When not counting IF, this general IF counter can be used as a timer. The IF
counter consists of 20bit binary counter and control port.
l. IF counter control port, data port
Y1 Y2 Y4 Y8
* 1 : Set to IF input
ffL14 * SCON lF/IN1 IF/IN switching bit (
0 : Set to general input port
Cycle measurement/frequency measurement switching bit
t : Set to frequency measurement
1 : Set to cycle measurement
Y1 Y2 Y4 Y8
Selection of gate time for frequency measurement (measurement time)
¢L15 STA/CT? Manual Go GI
x_v_/ G1 Go GATE TIME
. 0 0 1ms
0 1 4ms
1 0 16ms
1 1 64ms
Auto/manual mode switching bit for frequency measurement
0 , Auto mode
(When auto mode, it performs measurement
in the gate time described above.)
1 : Manual mode
(It performs start/stop of measurement by STA/s-TP bit.)
- MANUAL G1 G0
It functions as a binary timer
counter.
(The timer counter is reset if setting "1" to STA/s-rr, bit.)
IF counter start/stop control bit
t : Count stop
1 , Count start (the counter is reset when timer counter setting.)
37 2001-06-19
TOSHIBA TC9317F
¢K10 Y1 Y2 Y4 Y8
0 : IF counter count value< 220-1
BUSY Manual OVER 1 Overflow detection ( ' 20
l : IF counter valuea2
(Overflow state)
. 0 : IF counter auto mode
Operation mode
1 : IF counter manual mode
. ' 0 : IF counter finishes counting
Operation monitor
: IF counter still counting
¢K11 ¢K12 ¢K13 ¢K14 ¢K15
Y1 Y2 Y4 Y8
f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 fl? f14 f15 f16 fly f18 f19
20 219
75kHz 75kHz - Frequency at
2 220 the timer
I I counter mode
LSB IF counter data MSB
(Note) The IF counter becomes disable at PLL off mode.
(It becomes enable at timer counter.)
(1) IF counter auto mode (frequency measurement)
The method to use IF counter auto mode is to set IF terminal to IF input by means of IF/
IN switching bit and set SCON bit to "o".
To set the gate time for IF input frequency bandwidth and STA/TTT- bit to "I" while
manual bit "o", then the IF counter is operated.
During the set gate time, the 20bit binary counter is inputted a clock pulse from IF
terminal, counted the inputted pulse and finished. Whether IF counter counting has
finished or not, it can be judged by referring to BUSY bit. The OVER bit becomes "1"
when a pulse number of more than 20 count value is inputted.
The frequency inputted to IF input terminal can be measured by loading fo~f19 IF data
after judging that both BUSY bit and OVER bit are "O".
(2) IF counter Manual mode (frequency measurement)
When the IF frequency is measured by the gate time which controlled by an internal time
base (10Hz, etc.), the manual mode is used.
In this mode, the setting IF counter input is set the same as auto mode. The GO/GI bit
data should be set except "I". Counting starts if setting Manual and STA/rip bits to "I".
Counting stops if setting "0" to STA/TIT bit and data will be loaded in binary.
38 2001-06-19
TOSHIBA TC9317F
(3) IF counter cycle mode (cycle measurement)
It is used for measuring the low frequency when it couldn't be measured by the frequency
measurement.
In the cycle measurement, the cycle can be measured by judging this pulse number during
the inputting reference clock (75kHz) to the 20bit binary counter.
As this input terminal, it uses as the IF input terminal, it switches to SCIN terminal if
setting SCON bit to "I".
It sets Manual, GO and G1 bits to "0" when SCIN setting.
The start of the cycle measurement is as same as the frequency measurement, the
counting data is loaded after confirming the operation state by BUSY bit.
(Note) Input rectang waveform by means of DC coupling when SCIN input.
(Note) The BUSY bit will not be "o" unless inputting a clock pulse to SCIN bit.
(4) Timer counter mode
When not using f counter, it can be used as a timer binary counter.
If setting each Manual, GO and G1 bit to "I", it will start counting a 75kHz clock in binary
as reference clock.
This counter will be reset whenever setting STA/W bit to "I''.
2. IF counter circuit configuration
XOUT (75kHz) fo--f19 OVER
IFIN/IN1/SCIN 20bit binary counter H OVERI
V - Manual
Gate tIme ' - GO
control circuit _ G
Gate clock
STA/SFP
The IF counter consists of input amplifier, gate time control circuit and 20bit binary counter.
The IF counter becomes OFF state when PLL OFF mode, but when timer counter is setting, the IF
counter can be operatable.
(Note) As an amplifier is built-in at IFIN terminal, small amplitude operation is possible in
coupling with capacitor.
(IFIN, mm M11111111mm11M111111E -l-1-l-1-l-1-
Data set to STA/ST_P bit -4;r- -9-i-i-
Busy bit -I-1- -l-l,-'-t-
Gateclock -rLrLrLrLrLrLrLrl- IkHz :mmmmimmmmmmr--7skuz
Gate - -
Binary counter input -lmmmmmi- -iMmm11-
Frequency measurement auto mode Cycle measurement mode
39 2001-06-19
TOSHIBA TC9317F
C) LCD driver
The LCD driver is of 1/3 duty and 1/2 bias drive (167Hz frame frequency) method.
The common output outputs three voltage potentials of VLCD, 1/LCD/2 (VEE) and GND. The
segment output outputs two voltage potentials of VLCD and GND.
It is possible to display maximum 90 segments by combining three common outputs and 30
segment outputs.
The LCD driver segment output of S19~530 is used both as the key return output for loading key
matrix data.
As the LCD driver is built-in a constant voltage circuit for display (VEE= 1.5V) and voltage circuit to
double (VLcD=3.0V), the contrast of LCD display will not change even if supply voltage varies.
The LCD driver is capable of switching to I/O port in a unit of 1bit and can be programmed
according to the system.
(In this case, set VLCD OFF bit to "I" and connect VLCD terminal to VDD terminal to use.)
1. LCD driver port
Y1 Y2 Y4 Y8
¢L2D $1 $2 $4 $8
SEG/IO
Segmentldata select Switching bit
t :Segment output
Segment-2 data Segment-l data 0 .' l/O port
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L2F COM1 COM2 COM3 SEG ¢L2E COM1 COM2 COM3 SEG
- 0 S17 - 0 S1
1 I S18 1 I S2
2 I S19 2 I S?
3I S20 COM/IO 3 S4
Switching bit
" $21 " $5
I I I I I l
I I I I I I
l l l I I l
I I I 1 :Common output: I I
Y1 Y2 Y4 Y8
0:I/O port
COM1 COM2 COM3 SEG
COM1 COM2 COM3 SEG segment data
{1 : Turn on
' 0 : Ture off
C I 529
DI s30
(Note) The segment data controls segment ON/OFF corresponding
to the common and segment outputs.
COM1 COM? COM3
(Note) When system reset and clock stop mode cancellation, the
DISP OFF bit is set to "I''.
E COM IIO switching port
(Note) When system reset, the contents of VLCD OFF bit is set to
DISP VLCD * * "O".
F OFF OFF (Note) The $30 terminal becomes the input port (IN3) by switching
* : don't care to an IIO port.
40 2001-06-19
TOSHIBA TC9317F
The LCD driver control port consists of segment data select port and segment data port. These
ports are accessed when OUT2 instruction designated [CN=DH-FH] in the operand is executed.
The LCD driver can uses both as I/O port and this control is done by SEG/IO control bit (¢L2E,
¢L2F). It will be segment output if setting "I" to this bit and I/O port if "O".
The LCD driver segment data is set at the segment data port (¢L2E, ¢L2F). The LCD display
turns off if setting "0" to the segment data port and turns on if setting "I". The segment-2
data (¢L2FF) designated FH at the segment select port are DISP OFF bit and VLCD OFF bit. The
DISP OFF bit can turns off LCD display completely without setting segment data.
If setting "I" to this bit, the common output will be non-selected waveform and the LCD display
will be completely OFF. The contents of the segment is held at this time and the preceding
display will appear as it is if setting "o" to DISP OFF bit.
The segment data is rewritable during DISP OFF state. The DISP OFF bit be set to "I" after reset
or after CKSTP instruction is executed.
In case of using LCD terminal as l/O port, avoid LCD drive voltage supply booster (VLCD
terminal) as much as possible. The reason is that current consumption may increase dramatically
by supply voltage (The relation between VLCD and VDD levels). In this case, the doubler voltage
circuit is off state by setting "1" to VLCD OFF bit and used as external input, then used connect
VLCD terminal to VDD. At this time, LCD display contrast changes by supply voltage change, it's
necessary to stabilize of supply voltage.
Further it can use the external supply which is efficient in changing the liquid crystal drive
voltage by means of VLCD OFF bit.
These data are outputted after they were divided by the segment data select port (¢L2D). The
segment output S19--S30 terminal also uses both as the key return timing signal to load key
matrix data. The segment output becomes the GND level by the timing as loaded a key data.
2. LCD driver circuit configuration
'" O O
a':- MF tz" M
.- N m 2 ld V St
i! i! i! ts co ' c, ' c,
F N m _- F F N N m
U U U m m m m vs vs V» m m
- Common output .
DISP circuit Segment driver/Segment data
250Hz _] , I
OFF Key return control circuit
io'"' F? E
1.5V constant Doubler E
voltage circuit voltage circuit g
0? Ti OFF ; VLCD OFF signal
VEE CI c2 VLCD
l 80 78 79 77 :
2t, th.
F. 0.1,uF F.
41 2001-06-19
TOSHIBA
TC9317F
= (Example of output data)
Segment data select (¢LZD)
S? SI COM1 ¢L2E
= Y1 Y2 Y4 Y8
0 0 1 0 1 SI
COM2 1 1 1 1 1 $2
"evil, = o 2 1 O 0 1 S?
COM3 COM 1 2 3 SEG/IO control
I 6ms I
p—H l.—
DISP OFF I
I I l I I LCD
COM1 I I
l l_l cl - GND
ll-l l-l - VLCD
cow y,
ll Cl Cl - GND
I l - V
I l I I I I LCD
COM3 ll
ll l-l - GND
l - VLCD
l, - GND
" - - VLCD
1" GND
I - VLCD
-l. - GND
-, - 80pa
- VLCD
s19/KR11 I
Key data loading V
COM1-S2 -z,
(ON waveform) - GND
_| _I - -VLCD
COM1-S2 - VLCD
(OFF “WW - GND
- -VLCD
The LCD driver wave voltage potential outputs VLCD and GND voltage potentials and half the
intermediate level of these voltage potentials. A key return signal is outputted from S19~530
when this switching is performed. When loading key data, it becomes "L" level during 80ps.
(Note)
terminal will be "L" level.
When CKSTP instruction or initialization is executed, the common and segment
2001 -06-1 9
TOSHIBA
C) Key input & key return timing
TC9317F
Since there are four kinds of the key loading method, please design according to the system.
1. Key control port and key scan data port
ff L2A
Y1 Y2 Y4 Y8
KSD1 K502 KSD4 K508
Key scan data select
Key scan control port
Y1 Y2 Y4 Y8
(KCO) (KC1) (KC2) (KC3) - Key input level control
DA1 DA2 DA3 VEE -
1 KR12 KR13 KR14 KR15 - I/O key return control C)
2 KT12 KT13 KT14 KT15 - IIO key return control ©
3 KOP K1P K2P K3P - Key input pull down control
4 KOHz K1Hz K2Hz K3Hz - Key input high impedance control
STA/ * * * Key scan start/stop
6 don't care ,
', ', ',
x F don't care
Key scan control port (
When a key pressed, the data will be "1".
When a key not presed, the data will be "O".
Y1 Y2 Y4 Y8
K0 K1 K2 K3
1 I KR1
2 I KR2
K0 K1 K2 K3
F KR15
The key scan control port is a port to excute the input level setting control key scan start/stop,
setting of I/O port output form (P1-0~P1-3) and key input form.
The key scanned key data are inputted to the key scan data port (¢K29), and loaded into data
memory by accessing to this port.
These ports are divided by the key scan data select port (¢L2A), and by setting data to this port
data corresponding to this data are accessed. When accessing to the key scan control port (¢L29)
or key scan data port, the key scan data select port (¢L2A) is +1 incremented.
43 2001-06-19
TOSHIBA TC9317F
Y1 Y2 Y4 Y8
¢L290 DA1 DA2 DA4 VEE
l Switching bit of reference voltage of key input level
Key input level setup l {”0" : Reference supply VDD terminal
"l" : Reference supply VEE terminal
DA3 DA2 DA1 KEY INPUT LEVEL (VKREF) V :When VEE bit is "I"; 1.5 constant voltage (VEE)
0 0 0 1 /9 XV When VEE bit IS 0 ; supply voltage (VDD)
0 0 1 2/9xV
0 1 0 3/9xV
0 1 1 4/9xV
1 0 0 5/9xV
1 0 1 6/9xV
1 1 0 7/9xV
1 1 1 8/9xV
It is a port to perform the key input level setting. The reference level of key input supply can
be switched to VEE terminal or supply voltage (VDD terminal) by means of VEE bit. By
comparing the level that divides the reference supply by means of DA bit to the key input
terminal level as shown in the above table, the result will be outputted to the key scan data
port and key input data port.
Y1 Y2 Y4 Y8
fbL291 KR12 KR13 KR14 KR15 t,' : l/O port
%—’ 1 , Output the key return signal when the LCD output changes.
1/0 port-1
Key return control C)
If setting "I" to this port, it becomes the output form as described below.
Segment output A tru/bu V VLCD(3V)
P1-0 (KR12) --',, 80ps F-
P1-0 (KR12) ll VDD
H-l----- GND
It becomes "L" level when key scanning.
[Output circuit and timing when setting KR12 bit to "I'']
The KR12--KR15 bits correspond to P1-0~P1-3 terminal, respectively. If setting "o" to this bit, it
becomes an I/O port.
44 2001-06-19
TOSHIBA TC9317F
Y1 Y2 Y4 Y8
¢L292 KT12 KT13 KT14 KT15 {o : IIO port
I/O port-I
Key return control ©
l : Output a key return signal by software
Y1 Y2 Y4 Y8
¢L30 PI-O P1-1 Pl-? P1-3
*,—w {0 : Output "L" level
I:Out t"H"level
I/O port 1 data - u PU eve
If setting "1" to the port of I/O port-1 key return control a), it becomes the output form as
described below. The "H" and "L" level settings of this output are controlled by the I/O port-1
PI-O (KR12)
I/O port data ---l>-
[Output circuit when setting KT12 bit to "1"]
Each KT12--KT15 bit corresponds to P1-0~P1-3, respectively. If setting "O" to this bit, it becomes
an l/O port.
When operating a key scan by means of the I/O port-1 key scan control port co & g), the
contents of I/O-1 control port is necessary to set the bit corresponding to the port to make key
scan operate (the output port state [¢L3F0]) to "I". In case of setting "I" to each of KR and KT
bit, the KT bit is given priority.
45 2001-06-19
TOSHIBA TC9317F
Y1 Y2 Y4 Y8
¢L293 KOP K1P K2P K3P : Key input pull down )
a—J I 1 : Key input pull up
Key input pull down setting
Y1 Y2 Y4 Y8
¢L294 KOHz K1HZ K2Hz K3Hz {0 : Key input pull down or pull up
*r—’ 1 : Key input high impedance
Key input high impedance setting
These ports perform the input form setting of key input. The input form is set under the
condition as below.
KOHz KOP INPUT FORM
0 0 Pull down
0 1 VEE pull up
1 0 VDD pull up
1 1 High impedance
CD VEE (15V)
Com pa rator
Comparison voltage (VKREF) Comparison voltage (VKREF) Comparison voltage (VKREF) Comparison voltage (VKREF)
[pull down] [VEE pull up] [VDD pull up] [high impedacne]
It will always be pull-down at pull down setting. At pull up setting, it will be pull-up only when
LCD segment changes, otherwise it becomes high impedance.
At pull-down or puII-up setting, the key input terminal configures a key matrix in combination
with the key return output signal. At high impedance setting, it can be used as a 3bit A/D
converter of the sequential comparison method by software.
Each of KOP~K3P bits and KOHz~K3Hz bits correspond to K0~K3 terminal. The key input
terminal at pull-down setting, if "H" level (VDDx0.6V or more) is applied when WAIT mode, it
cancels to execute WAIT instruction and it's possible to restart CPU operation. The CPU operation
restarts only at "H" level setting and not at puII-up or high impedance setting.
46 2001-06-19
TOSHIBA TC9317F
Y1 Y2 Y4 Y8 Key scan start/stop bit
¢L295 STA/S-TP * * * {o : key scan stops
1 : key scan starts
Whenever setting "I" to STA/WP bit, it starts scanning from the key scan start port data. If
setting "o" to this bit, it stops key scanning. When changing the key return control port or the
contents of key scan start/end port described the following, to change after the key scan
stopped and restart by setting "1" to STA/W bit afterwards. If not set like this, a key except
the ones between scan start data and scan end data may be loaded or key data within a cycle
of scan may not be loaded.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L27 KS1 KS2 K54 KS8 ¢L28 KE1 KE2 KE4 K58 ¢K27 KR1 KR2 KR4 KR8
Key scan start Key scan end Key scan operation monitor
¢K29 K0 K1 K2 K3
Scan within this range
Set up "0100"
.___. N —- o
‘Set up "0100"
15 KR15
The key scan start and end ports are ports to set up the range in which a key scan is
performed and they perform scanning within the range between start data and end data.
Set the data of these ports to be
"start data value s end data value".
Which key line is loaded during scan operation can be judged by referring to the key scan
operation monitor.
The key scan data (¢K29) outputs "I" when a key pressed, and "0" when not.
(Note) When supply voltage is less than 1.5V by CPU stop function, the CPU stopped. And
just after restarted, the key scan data is unknown. Due to this load key scan data
into data memory after judging that key scan scanned one cycle by referring to
STOP F / F.
Y1 Y2 Y4 Y8
fbK28 K0 K1 K2 K3
Key input data
From the key input data port, the key input data is loaded into data memory directly. If this
is higher than comparison voltage, it becomes "1" and "o" if lower. These ports are accessed
when OUT2/IN2 instructions designated [CN=7H--AH] in the operand is executed.
47 2001-06-19
TOSHIBA
TC9317F
2. Key scan circuit configuration
PIA) - 3
KT12--15
KR12-15 Key scan data
C) K3 K2 K1 K0
P1-3(KR15) Ci?, KR1 + cu, K0
P1-2(KR14) Ci? Output ; -
setting ( l Ciii
P1-1(KR13) Cai? circuit l +
W» *9 - = 5:25;;
I + circuit Cib' K2
S30(KR0) Q l + 9 K3
Decoder l
529(KR1) Cf22 l -
S28(KR2) Q I
I KOP --K3P
' LCD l K0Hz-K3Hz
I segment - I
l driver C- l
I l, Selector (n DA1--3
, V I 1
S20(KR10) a I "'xz,,,-,i,7e.,o,(i',. R o o R
KR14 o-o
S19(KR11) Ci:?, --o VEE \VEE
K0 K1 K2 K3
Timing Counter STA/STP
Start No.
Stop No.
The key input of key scan circuit consists of input setting circuit, 3bit D/A converter, comparator
and latch circuit for loading key data. The key return timing output consists of output setting
circuit of I/O port, LCD segment driver and counter/decoder to control I/O port output unit.
2001 -06-1 9
TOSHIBA TC9317F
3. Key matrix configuration
The key matrix can be configured in the following four ways.
(1) Key data loading by software
I P1-0 I I
P1-3 D _
P1 1 I I
P1-2 I-I
u1\_r\_r\_.
A I‘ ' \l '
't u fh P"h fh ' loading key
= I‘ V.' ' '
zs-M C) (I C)
H f"s r Ph
v.' ' I
Com parison
voltage
+ f,)"; A mg
Push key Diode jumper
When loading key data by program, it configures the key matrix as above.
The l/O port-1 data (¢K30) which you want to load the key line is "H" level, is pressed
load. The key input port (¢L28) data into the data memory and judge whether the key or
not. At this time, the HO port -1 data not to be loaded should be set to "L" level.
If a key is pressed, the key input port data "1" is loaded into data memory and "o" if
not pressed.
Only 4x4= 16 key matrices are usable in this method. However, since data is loaded at
high speed and the structure of high resistance is in N channel FET part of P1-0~P1-3, it is
unnecessary to have a diode for preventing reverse current owing to double key press.
As to the method for loading data by software, set the data to the port as described
below.
DAI--DA3 VEE KR12--KR15 KT12--KT15 KOP--K3P KOHz~K3Hz
With jumper 4/9 VDD 0 All "o" All "1" All "o" All "o"
Without jumper 3/9 VDD 0 All "0" All "1" All "0" All "0"
(Note) In case of using as NO output of I/O port -1, set the bit corresponding to
KT12--KT15 to "0".
(Note) When configuring a diode jumper, voltage of diode VF (-0.6V) lower than
supply voltage is applied to the key input voltage. For this reason, the key
input threshold value should be set low. As shown the above diagram, a
diode for preventing reverse current owing to double key press is necessary.
When configuring without a diode jumper, this diode is unnecessary.
In such mode, adding "H" level (VDDx0.6V or above) at WAIT mode, WAIT instruction
execution is canceled and CPU operation is restarted. (The "H" level at this time is not
related to DA1--DA3 bits.)
49 2001-06-19
TOSHIBA TC9317F
(2) Key data loading by LCD segment output
VEE(1.5V)
IC, . l
37 C) C)
+ I C) c, c, 4- dy
To key scan
data latch -
36 K2 fh fh fh fh fh
"rr-C.."'.? ,sJ-5,.F"
Comparison 35 K1 f"N fh fh fh fh gl E>
voltage % A \
ll - ,
M == 1.4 == LA ==
ib,( ty)
S29 KR
32 ( 1)
31 S 8(KR2)
VLCD I l l To LCD panel
-ei' észomam)
22 519(KR11)
(Note) Maximum 4x12=48 key matrices can be configured.
(Note) A push key and diode jumper cannot be mixed in the same key line. The
position of diode jumper should be on the side of key return signal output.
I w ' l , GND
S29(KR1) at) . /\/ ' , W” F" GND
S19(KR11) iiiiki' W "N-..." t AY VLcD
Key data
Key scan data HI I I 40/15” I I H II I I latch
latch signal ' ' / u
Key loading signal
Key pull up
50 2001-06-19
TOSHIBA TC9317F
In case of key data loading by means of LCD segment output, the key matrix as described
in the preceding diagram is configured. A diode for preventing reverse current is necessary
for this key matrix, therefore be careful for this diode and the diode jumper direction.
In this case, VLCD (3V) and GND voltage potentials are outputted from segment terminal
when LCD output changes. When key data loading, the segment signal to load will be
GND voltage potential at LCD output change and the key input terminal is pulled up to
VEE voltage potential. At this time, if a key is not pressed (or without diode jumper), VEE
level is inputted to the key input terminal and voltage worth of one diode voltage (-
0.6V) is inputted from GND voltage potential if a key is pressed (or with diode jumper).
The voltage potential inputted is compared with the D/A output level of which VEE
voltage potential is divided into nine and latches the signal comparated to the key scan
data port corresponding to the segment output line of key loading.
This key data becomes "I" when a key is pressed and "o" when not.
As to the method for key loading by means of LCD segment output, set up the data
described below to the port.
DA1~DA3 VEE KR12--KR15 KT12~KT15 KOP--K3P KOHZ~K3HZ
6/9 VEE 1 All "0" All "0" All "1" All "0"
If setting the range in which key scan is performed to the key scan start (¢L27) and key
scan end (¢L28) and setting "I" to STA/W bit after the above setting, key scan will load
key data one after another within the setting range.
The time required to load one line key data takes 2ms. Due to this the key scan data
(¢L29) will be loaded into data memory during referring to the key scan operation
monitor.
In case of changing the range in which key scan is performed, there are two ways as
follows:
It Restart by setting "1" to STA/WP bit again after change.
0 After stop the scan operation by setting "o" to STA/W bit, change the range. Then
start key scan again.
(Note) Because the diode jumper data is stored in the latch, the data memory space
can be utilized efficiently by referring to the contents of stored latch without
loading into data memory, as needed. After CPU operation has stopped by
CPU stop function and just after CPU restart, the contents of this latch will be
unknown.
(Note) The range in which key scan is performed is between KR0-- KR11.
51 2001-06-19
TOSHIBA TC9317F
(3) Key data loading by means of LCD segment output and HG port C)
IP13 KR
41 ( 15)
PIQ KR
EE P1-1 KR
39 ( 13)
P1- KR
" 38 0( 12)
To keyscan + 37 L_\l__\l__\ (.41.; H C) C) C) C)
36 K2 /\ /\ / \ /\ H fh fh fh f'h
datalatch - /__\1__\1__\ l__\l_.._\ ' ' ' v.r
35 K1 LI fh fh fh fh
t-2sl2sl2s l__\l_..A VI 'sk _ K} '
Comparison 34 ====== ==== M C) (r C) C)
voltage _ .
s30 ------
33( o)
S29 KR
32 ( 1)
1 S28(KR2)
3V I t
( ) I ', I To LCD panel
VL D l I .
' 520(KR10) I l
S19 KR
22 ( 11)
2ms IBOES
I , I I " " VLCD
S17(KR11) iiiluziY af W xtie1,g te
, I u 1 t u I , u t I GND
' I ' VDD
I I I I I t l l
P1-0(KR12) l i l l I I -GND
' I ' t I I
I I I I VDD
P1-1(KR13) l I I I -GND
s 2 VDD
P1-2(KR14) I : -GND
P1-3 (KR15) - GND
The method to load key data by LCD segment output and l/O port is the same as that
for loading key data by LCD segment output (3-(2)) except the following setting.
KR12--KR15 KT12--KT15
All "I'' All "0"
(Note) In case of using as I/O output of I/O ports (P1-0~P1-3), set the bit
corresponding to KR12--KR15 to "O".
(Note) Maximum 4x16=64 key matrices can be configured.
(Note) The configuration equivalent to the item 3-(2), [key data loading by means
of LCD segment output] is possible at KR0~KR15.
52 2001-06-19
TOSHIBA TC9317F
(4) Key data loading by LCD segment output and I/O port ©
It is a usage method combining the key loading
method by software and LCD segment output.
(Refer to 3-(1), (2).)
The characteristics of this method are below.
32;: -l>o-4
o It perform key loading on the I/O port side at
high speed.
K3 -<:C( - at" (343434) 0 It's possible to expand keys by allocating the
‘T i keys which need not to load at high speed on
K2 --<:Ci' - as)" C.) Cy (P 0 the LCD segment output side.
5‘ i As to key loading, the HO port side performs it
VEE at input data port (¢K28) and the segment
- output side at key scan data port (¢K29).
Accessing to the key input data port can be done
by switching comparison voltage of key input.
i", The setting of this method is performed as
To key
data latch
, , x M---x x described below.
K0 Setting of I/O port side
KR12 KR13 KR14 KR15 KT12 KT13 KT14 KT15
0 0 0 0 1 1 1 1
conparison
valtage
(3V) Key input setting
4 I S20(KR10) KOP K1P K2P K3P KOHz K1Hz K2Hz K3Hz
" ft S19(KR11) 1 1 o o o o o o
Ii: I The key input settings on the I/O port side and
on the LCD segment output side can be done in
a unit of 1bit.
(Note) In WAIT mode, supplying "H" level (VDDx0.6V or more) to the key input terminal
whose key input is set to pull down (K2 and K3 terminal in the above diagram),
WAIT instruction execution is cancelled and CPU operation is restarted.
(Note) Key data on the segment side is loaded when LCD segment changes. Therefore, if at
the same time loading data on the I/O port, the key input threshold level will be
different and data on the segment side will be loaded by mistake. For this reason,
control by key scan operation monitor will be required.
(Note) Set the contents of I/O port -1 control port (¢L3F0) to all "I" (output setting).
53 2001-06-19
TOSHIBA TC9317F
C) Serial interface
The serial interface is a serial I/O port to send/receive synchronously 4 or 8bit data with an
internal/external serial chock. By means of SI, so and SCK terminals, it performs sending/receiving
data of LSI (for expansion) and microcomputer, etc.
1. Serial interface control port and data port
Y1 Y2 Y4 Y8 Selection between I/O port -3 and serial interface
¢L22 edge sc-Kon, @4/5 SIO-ON {o : select lt/O port -3 (P3-0--P3-2)
1 : select serial interface function
- Selection of an external/internal of SCK clock
{0 : External sc5 clock
1 : Internal sc-K clock
Inversion of W clock signal (valid only when the internal clock setting)
{0 .' Outputm clock from "H" level
1 : Output S-CK clock from "L" level
Logical selection of serial data shift operation
{0 : Shift at rising edge of sc7
1 : Shift at falling edge of SW
Y1 Y2 Y4 Y8 Selection between serial data 4bit and 8bit
¢L23 STA sov6 4l§bit * {o : Abit data
1 : 8bit data
Switching between so output and SI input of SO terminal
{0 : so output
1 : SI input
Serial operation start and internal port reset
f,' : don't care
1 : COUNT bit and SIO F/F bit are reset and the serial output data is set to shift
register. The serial operation will start when selecting the internals-CK clock.
LSB Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 MSB
¢L24 soo $01 $02 $03 ¢L25 $04 $05 $06 507
Serial output data ...... The data which set to this port is outputted in serial.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢K24 SIO Sll SI2 SI3 ¢K25 Sl4 SIS Sl6 SI7
Serial input data ....... The data which is inputted in serial can be loaded into the data memory.
(Note) As for the serial input data, the contents of shift register is directly acceessed.
(Note) After system reset, the contents of serial interface control port (¢L22, ¢L23) is reset
to "o".
54 2001-06-19
TOSHIBA TC9317F
Y1 Y2 Y4 Y8
SIO start flag
¢K23 BUSY COUNT 90 HF 1 {0 : SIO operation not performed
1 : SIO operation performed
- The judge bit of SCK clock
{0 : clock count correct (The SCK clock count is 4 times as much.)
1 : clock count incorrect (The SCK clock count is not 4 times as much.)
SIO operation monitor
{0 : SIO operation finished
1 : SIO operation underway
The serial interface control and serial data are accessed when OUT2/IN2 instruction designated
[CN=2H-5]] in the operand is executed. The serial interface terminal is combined with P3-0, P3-1,
P3-2 of I/O port and if setting "1" to SIO ON bit, each I/O port-3 terminal is switched to SI, SO
and ?CIZ terminal, respectively.
(f) St-:K-INW, SiK-i/Cy bit
The S=-INV and st-yt-i/U bits are bits to set the input and output form of = terminal. By
means of this bit data, the condition as described following will be set.
SCK terminal state
INV U5 INPUT/OUTPUT "fRlTdCLOcKWAVEFORM
0 0 Output HIIIIII
1 0 Output IHHIII
Input -
© Edge bit
The edge bit sets the shift logic of serial data. By means of this data, data will be shifted as
shown below.
It When edge="0"
Set STA bit "l"
sisrmina"irlilu IIIIIIII
so operation ii)( soo t SOI X SO2 X SO? IW A soo X SOI X SO2 I 503
I I I I I I I I
SI operattion SI0 Sll SI2 SI3 SIO sn SI2 Sl3
When setting the edge bit to "o", the SO output is outputted at rising edge of TtTk-
clock, and the SI input, as well as the SO output, is inputted to shift register at rising
edge of clock.
55 2001-06-19
TOSHIBA TC9317F
c When edge = "I"
Set "I" to STA bit
Scisrminal IIIIIIII _IIIIIIII
so operation ti; soo I SOI i SO2 I 503 a soo i SOI X 502 I 503 F'"
I I I I I I I
SI operation SI0 Sll SI2 Sl3 SIO Sll SI2 Sl?
When setting edge bit to "I", SO output is outputted at falling edge of Tek- clock, and SI
input as well as so output is inputted to shift register at falling edge of clock.
(3) 4/§bit
The 4/lfbit is a bit to select the serial data length. When this bit is "o", it becomes 4bit
length and 8bit length when "I". If selecting the 4bit at an internal clock, TtR- clock outputs
4 clocks and 8 clocks if 8bit.
0 When 4/§bit is "O", (In case of edge="O", SCK-lNV=''0")
sc-ktermina; I I I I I I I I
Set "l" to STA bit
so operation iirsd' X SOI X SO2 X 503 W
I I I I
SI operation SIO SI1 SI2 Sl3
0 When 4/§bit is "I", (In case of edge="O", SCK-lNV=''0")
F; terminal
Set "l" to STA bit I
SO operation 'so': X SOI X SO2 X 503 X 504 i sos i 506 t SO? ir"
I I I I I I I I
SI operation SIG Sll Sli? Sl3 sm SIS SIG Sl?
56 2001-06-19
TOSHIBA TC9317F
© SO-I (i5 bit
The 504/5 bit is a bit to set the serial input/output of SO terminal.
When setting 804/5 bit to "o", SO terminal outputs the serial data. When setting this bit to
"I", it becomes the serial data input.
By means of controlled this bit, LSI of serial bus system such as T-BUS which conducts data
input/output by one terminal can easily be controlled.
sc-Kiera/mal {Illilll :l’lilill
: l l : l Floating
I I I I
so operation X so X SI , S2 , S3 //)K so X Sl X S2 X S3
Lso-I/E)="0" set so-I/6="1" set Input data by LSI to control
(Note) In this case, it is necessary to pull up so terminal for the floating timing.
In this system, when transmit mode, it performs SIO operation by setting data to the serial
output data port. When receiving, it performs SIO operation after so terminal is set to input
and loads the contents of the serial input data port into the data memory. Also when
selecting the serial interface, SI terminal is controllable as I/O port (P3-0). The l/O output
(P3-0) can be used as strobe pulse terminal in T-BUS, etc.
(Note) When SI terminal is use as serial data input mode, P3-0 bit of HO control port
which corresponding to I/O port-3 should be set to "O".
© Serial interface operation monitor
The operational state of serial interface can be judged by referring to BUSY, COUNT or SIO F
/F bit.
Since BUSY bit will be "I" during SIO operation, control data switching and serial data access
will be done when BUSY bit is "O".
The COUNT bit is a bit to judge whether data transmitting/receiving was performed in a unit
of 4bit. In case shift operation is performed by multiple of 4, this bit outputs "0" and in case
shift operation is not performed by multiple of 4, it outputs "I".
The SIO F/F bit is set to "I" when TtIT terminal starts clock operation.
The COUNT bit and SIO bit are all reset to "o" if setting "I" to STA bit. These two bits are
mainly used when §CT<_ terminal is set to an external clock. It can be judged that information
that an external clock was inputted and serial data was transfered/received and if operation
was properly performed.
© STA bit
Whenever setting "1" to STA bit during SCK internal clock setting, serial output data will be
set to shift register and clock pulse will be outputted from TCR" terminal to start shift
operation. At the same time COUNT bit and SIO F/F bit will also be reset to "O".
57 2001-06-19
TOSHIBA TC9317F
2. Serial interface configuration
SIO F / F COUNT
1 l l 'ir,c"-lNv=1c'-t,-sc--Ki"
48 sc" (P3-2)
STA-- Control circuit
"dt so (P3-1)
l Cle-edge
Shift register
(i) : C.'
4 l? 418bit rrc2rr,d E
|500|SO1 ISOZISO3ISO4ISOS|506|SO7| ”m -3l-2l-1l-0
IIO port 3 data IIO port 3 HO control
Shift "iis"9isti-r
(5 SI (p3-0)
SIO~SI3 Serial output data "i"'"
Serial input data
The serial interface consists of : control circuit, shift register and I/O port.
(Note) The SI terminal can directly be used as NO port-3 (P3-0).
(Note) The contents of data set to serial output data do not accord with the contents of
serial input data.
(Note) The SI terminal set as SI input, = terminal set as St:-yt input and SO terminal set at
input will be all Schmitt inputs.
3. Serial interface timing
When setting ?CIZ clock to an internal clock, the clock frequency outputted from TtIR- terminal is
37.5kHz (duty 50%).
The example of serial interface timing is as shown below.
-/ 26.6ps F-
sc-K terminal
I I I I '
I I I l
SO operation a soo X SOI I 502 I 503 I a X
l él J, l I
SI operation i a b c X d X x
I I I I I
522:3: a b
(¢K24) x a x : invalid
STA bit
BUSY bit
COUNT bit I
SIO F/F I l I
(sc_K-I/6=1,sc_K-INv=o,edge=1,so-I/6=o,4/§bit=0)
[Example of serial interface timing]
58 2001-06-19
TOSHIBA TC9317F
A converter (pulse-width modulation : PWM) output
The pulse-width modulation output (PWM) can obtain D/A conversion output easily by external
Iow-pass filter. The PWM output is a 12bit resolution and has one-channel output.
PWM control port and data port
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
PWo PW1 sz PW3 ff L19 PW4 PW5 PW6 PW7 $5 LIA PW8 PWg PW10 PW11
LSB PWM data MSB
Y1 Y2 Y4 Y8
PWM PWM Buffer
Buffer transfer bit
ON IBUZR transfer _ _ _
{0 : PWM output remains unchanged even if changing PWM data
1 .' Transfer PWM data
- Selection between PWM data and BUZR data
I: : Select BUZR data
l : Select PWM data
(Note) The PWM data and the internal port which performs the BUZR data setting
are identical. The data port is accessed by selecting PWM data or BUZR data
by means of this bit.
Selection between IIO port -2 P2-3 and PWM output
{0 : Select IIO port-2 (P2-3)
1 : Select PWM output
The pT/irfiif output combines the P2-3 I/O port. When the setting of PT/irfi7f output, the P2-3
switches to pTli7li7f output by setting PNT/h7f ON bit to "I".
The PWM data setting is done after setting PWM/BUZR bit to "I" and buffer transfer bit to
"O". If setting "I" to buffer transfer bit after PWM data setting, the PWM data will be
transferred to PWM data latch. After setting "I" to buffer transfer bit, maximum times of 109ms
is required. The PWM output would not chnage if this bit is set to "o" before transferring to
PWM data latch.
In PWM data, PWO is LSB and PW22 is MSB. The high 8bit (PW4-11) data controls the pulse-
width of pulse output. The low 4bit (PWO-3) data controls the position to output the pulse that
was added during one cycle of p17ifii"if output.
These data settings are performed when OUT1 instruction designated [CN=8H~BH] in the
operand is executed.
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TOSHIBA TC9317F
2. PWM output circuit configuration
37skHz-/ 12bit binary counter _ _
PW11 c)) Al;,
PW8 Additional
generation
PW7 PWM circuit
PMW data port ' i)) data " "
PW4 latch -
F/F C1 R2
PW? i) circuit
1 -l/ S - - R1 E
PWo ---- . Q s) PWM Simple D/A
Accordance signal output
Latch |_- R
signal
Buffer
PWM/BUZR
transfer
The PWM output circuit consists of : 12bit binary counter, PWM latch and comparison circuit.
3. PWM output waveform
Pulse width = (n + I) xto
TS=6t3/ns(TM/16) l l n : PW4~PW11 data value(0-255)
I : I t to: 267/15
*Pulse width nxto I * I l to-- "ct?' to
t I I ai- I I I '
PWMIII’II‘ll—Il—ll‘l llaalll’l:l_|l_|l_l
TS(15)' TS(O) l TS(1) i TS(2) i TS(3) I TS(4) l TS(S) l :15025 ll
I I I I I I I I II
TS( (13) l TS(14) l TS(15) l TS(O) l
I ' I , I
" TM=109.2ms(4096/37_5kHz) ﬂ
Example of PWM output timing (there are additional pulses in TS (4), TS(12): PW1 bit "I")
PW DATA THE RANGE IN WHICH AN ADDITIONAL PULSE IS OUTPUTTED
BIT (C) MARKS THE POSITION TO BE ADDED).
o 1 2 3 4 5 6 7 8 9 IO 11 12 13 14 15
PWo CD
PW1 O C)
sz C) C) O C)
PW3 C) C) C) C) O O C) C)
(Note) The above numbers indicate the i value of TS(i). When PW data bit is "I", the
additional pulse is outputted to the above O position.
One wave cycle of PWM output is TM=2‘2/37.5kHz=109.2ms and it outputs a pulse of 12bit
resolution. The high-order 8 bits, PW4--PW11 of PWM data controls the pulse-width of pulse
output whose cycle is TS (TS=TM/16=6.834ms). When the value of PW4-PW11 is n (n=0--255),
the low level pulse width whose cycle is TS will be nxto (to=1/37.5kHz).
The low-order 4 bits, PWO-3 controls the position to output the additinal pulse of "to" width in
TS(i) (i=0-15) between 16 sections within TM cycle. In the section where an additional pulse is
outputted, the low level pulse-width will be (n+1)xto.
When the low-order bit data are m (m=0--15), an additional pulse is outputted at m point
within TS(i) section. The section where this additional pulse is outputted is shown in the
preceding table. (However, the additional pulse is not outputted within TS(O) section.)
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TOSHIBA TC9317F
C) Buzzer output (BUZR)
The buzzer output is usable for outputting the confirmation and alarm sounds when key operation
or tuning scan mode. The buzzer frequency can freely be set and outputs a 50% duty waveform.
1. BUZR control port and data port
¢L18 Y1 Y2 Y4 Y8 /LI9 Y1 Y2 Y4 Y8 _ controls the BUZR output frequency and BUZR output off.
BO Bl B2 B3 B4 B5 B6 B7
LSB BUZR data MSB
Y1 Y2 Y4 Y8
¢L1B BUZR PWM Buffer Buffer transfer bit
ON IBUZR transfer {0 : BUZR output not varies even if changing BUZR data.
1 I BUZR data are transferred
- Selection between PWM data and BUZR data
"O" should be set before setting BUZR data.
- Selection between I/O port-3 P3-3 and BUZR output
{0 : Select I/O port-3 (P3-3)
1 .' Select BUZR output
The BUZR output combines the P3-3 I/O port. When BUZR output setting, the BUZR on bit is
set to "1", then the P3-3 output switches to BUZR output.
The BUZR data setting will be done after setting both PWM/BUZR bit and buffer transfer bit to
"o". If setting "I" to buffer transfer bit after BUZR data setting, the BUZR data will be
transferred to the BUZR data latch and the BUZR frequency will change.
The frequency of dividing 75kHz into 2xn (n .' BO~B7 value) is outputted to BUZR output and
the BO~B7 setting and frequency ranges are .'
2SnS255 'l'',-:",', =18.75kHzsfBuzRs mi =147Hz
x2 2x255
If the BO~7 setting is lower than l, it will be the condition as described below.
B7 B6 B5 B4 B3 B2 Bl BO BUZR OUTPUT
0 0 0 0 0 0 0 0 Fixed at "L" level
0 0 0 0 0 0 0 1 Fixed at "H" level
These data settings are performed when OUT1 instruction designated [CN=8H--BH] in the
operand is executed.
(Note) The BUZR ON bit will be reset to "o" after system reset.
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TOSHIBA TC9317F
2. BUZR circuit configuration
7SkHz Programmable counter counter Cog" BUZR
Data "1" f
BUZR data latch Buffer transfer
tC, PWM/BUZR
Latch signal
BUZR data port
The BUZR circuit consists of : 8bit programmable counter, 1/2 counter, BUZR latch and BUZR
3. BUZR output timing
BUZR output
l-ll-e-ll-lil-
Data port Be'" "ir? % AW2X Data all "O"
l Transfer "
Data latch W Ar2it" Data all "o"
Transfer bit _
e "l" se
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TOSHIBA TC9317F
C) A/D converter
The A/D converter is a 2-channel, 6bit resolution and usable for measuring field strength and
battery voltage.
1. A/D converter control port and data port
Y1 Y2 Y4 Y8
fbL20 AD AD REF REF
SELO SEL1 SELO SEL1
u n J x J DC-REF select
SEL1 SELO DC-REF VOLTAGE
O 0 Supply from DC-REF terminal
0 1 VDD (Supply voltage)
1 O VEE (1.5V constant voltage)
1 1 Inhibit
AD input select
SEL1 SELO A/D INPUT
0 0 ADIN1
0 1 ADINZ
1 0 VEE (1.5V constant voltage)
1 1 Inhibit
Y1 Y2 Y4 Y8
¢L21 STA DC-REF AD1 AD2
ON ON ON
Selection between A/D input and I/O port
"ir=C, 2 : I/O port
1 .' A/D input
DC-REF input and NO port
{0 : l/Oport
1 : DC-REF
A/D converter start bit
It performs A/D conversion whenever setting "I''.
¢K20 Y1 Y2 Y4 Y8 ¢K21 Y1 Y2 Y4 Y8
ADO AD1 AD2 AD3 AD4 AD5 BUSY 1
LSB A/D conversion data MSB A/ D operation monitor
{0 : A/D conversion finished
1 .' During A/D conversion
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TOSHIBA TC9317F
The A/D converter is a 6bit resolution. The reference voltage of A/D conversion can select the
external voltage (DC-REF terminal), supply voltage and 1.5V constant voltage (VEE). The A/D
conversion input is a multiplex method of 2-channel external input terminal (ADIN1, ADINZ
terminal) and also switchable to 1.5V constant voltage (VEE) as well.
Normally field strength and volume level are measured by selecting external voltage or supply
voltage as reference voltage and A/D converting the external input level.
The A/D converter can also measure battery and supply voltages. It outputs a battery signal or
performes control for backup mode when battery voltage or supply voltage drop. Following is
the description as to this method.
1.5V constant
voltage
1.5V constant
voltage
A/D Analog A/D Analog 42
data comparator data comparator
Reference voltage VDD 72
Reference voltage (DC-REF) (DC-REF) converter
(when battery direct driving) (when battery boosting drive)
The VDD supply voltage application system has two methods:
It Method to drive directly from battery.
It Method to drive LSI by boosting low voltage battery using DC-DC converter.
In the case of direct-driving from battery, by setting the reference voltage of A/D converter to
supply voltage (VDD) and A/D converting the internal 1.5V constant voltage, battery voltage is
judged. If, for example, A/D converting when VDD=3V, the A/D bit data will be about 20H
(32) and about 30H (48) when VDD=2V.
In case of boosting battery of low voltage, the battery voltage level can be judged by inputting
battery voltage (battery voltage at this time must beS1.5V) to A/DIN terminal and setting the
internal 1.5V constant voltage (VEE) to reference voltage for A/D conversion. For example, the
A/D data when battery voltage=1.5V will be about 3FH (63) and about 2BH (43) when 1.0V.
The A/D converter does A/D conversion whenever setting "1" to STA bit and the conversion
will complete after 7 machine cycles (280ps). Whether A/D conversion is completed can be
judged by referring to BUSY bit. After A/D conversion is completed, the data will be loaded
into data memory.
These controls are accessed when OUT2/IN2 instruction designated [CN=0H, 1H] in the operand
is executed.
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TOSHIBA
TC9317F
2. A/D converter circuit configuration
_ AD 92
[a" AD
Com arator INI
p Sample T C', C', .
+ hold
_ REF @ ADIN2
SELO-N
A/D "di DC-REF
A/D data ADO conversion l
port A, data latch
control
. . 1.5V
circuit - R constant "do? VEE
I I Decoder . voltage
STA BUSY . cirucit
6bit D IA converter
The A/D converter consists of : 6bit D/A converter, comparator, A/D conversion latch, control
circuit, A/D
data port and 1.5V constant voltage circuit (supply for LCD driver).
The A/D converter will latch the data to A/D conversion data latch sequentially by means of
the 6bit sequential comparison method.
(Note)
(Note)
The DC-REF terminal is built-in an amplifier and is high impedance input.
During A/D conversion, a proper data is not obtainable even if referring to the A/
D conversion data. Therefore, make sure to confirm that the conversion has finished
by referring to the A/D operation monitor.
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TOSHIBA TC9317F
C) Input/output port (l/O port)
The I/O port consists of 56 ports (l/O port-1~|/O port-14), which are usable as control signal input
/output. Within the 56 HO ports, the I/O port-1, I/O port-2, I/O port-3 and I/O port-F-l/O
pore-l/O port-14 combines a key return signal, A/D converter and PWM output, serial interface
and buzzer output and LCD driver output, respectively.
The NO port-F-l/O port-14 are normally used as LCD driver output.
1. HO port control and I/O port data
Y1 Y2 Y4 Y8
¢L3E lOl IO2 lO4 IO8
I/O port control select
Y1 Y2 Y4 Y8
¢L3F -0 -1 -2 -3 "t
0 |/O-1
1 l/0-2 's,
2 I/O-3 \ no control data
's, "s, "s, F l
"s, X " I/O port in/output setting
"s, 0 1 2 3 {o ; l/O port input
(Y1) (Y2) (Y4) (Y8) 's, 1 : I/o port output
-0 -1 -2 -9 -i/ty portNo. D I/O-IO
E don't care
¢KL30 l/O-l ,
F don't care J
¢KL31 IIO-Z
¢KL32 UO-?
0 :In/out ut in "L" level
l F IIO port data ( p p
l l : In/output pin "H" level
¢KL3D l/O-14
¢K3E IN2 1 1 1 '
(Note) After system reset, the contents of l/O-I-- I/O-6 of the I/O control data will be set
to "0" (input port).
(Note) The I/O-1, UO-il .-I/O-14 correspond to the terminal names of P1-0~3, P-20--3 ...
P14-0--3, respectively.
(Note) The S30 terminal will be the input port (IN2) when I/O port switching.
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TOSHIBA TC9317F
The I/O port in/output will be set by the contents of HO control data port. If setting to an
input port, the bit of HO control data port corresponding to the port should be set to "o" and
"I" if output port.
The I/O control data port is divided by the HO control select port (¢L3E). The l/O control data
port should be accessed by setting data corresponding to the port you wish to set to l/O
control select port. Normally whenever accessing to I/O control data port, the HO control select
data will be +1 incremented. Therefore, the I/O control data will be set successively after "OH"
is set to the I/O control select.
When output port setting, the output state of I/O port is controlled when OUT3 instruction
corresponding to each I/O port is executed. The contents of data just outputted will be loaded
into data memory when lN3 instruction is executed.
When input port setting, the input state of HO port is controlled when IN3 instruction
corresponding to each I/O port is executed. At this time the contents of latch on the output
side will never affect the input data.
The I/O port-7~14 combines the LCD driver output. In case of using even one terminal of LCD
driver for l/O port, it is recommended to use after setting "I" to VLCD OFF bit and connecting
VLCD terminal to VDD terminal. (Refer to item of LCD driver)
I/O port-1~3 combines A/D converter and BUZR output. After system reset, these ports will be
set to l/O port. Furthermore, after system reset, I/O port will be set to input port and
combination terminal of LCD driver and HG port will be set to LCD driver output.
In the I/O port-1, when the input state of I/O port designated at input port is changed,
execution of WAIT/CKSTP instruction is cancelled and CPU operation is restarted. Likewise, when
I/O bit of MUTE port is "I", MUTE bit of MUTE port will forcibly be set to "I" by changing of
the input state.
(Note) In the combined terminal of LCD driver and I/O port, the HO port input/output
and HG port data will be "don't care" when LCD driver setting.
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TOSHIBA
C) Register port
TC9317F
The G-register and data register mentioned in the description of CPU are used also as internal
ports.
1. G-register (P L1F)
It is a register for addressing data memory row addresses (DR=4H-FH) when MVGD/MVGS
instruction is executed. This register is accessed when OUT1 instruction designated [CN=FH] in
the operand is executed.
(Note) The contents of this register is valid only when MVGD/MVGS instruction is executed
and not valid when other instructions are executed.
(Note) Also all the row addresses of data memory can indirectly be
Y1 Y2 Y4 Y8
#0 fl f2 f3
c-v--"
Specify the row address
of data memory
#3 #2 #1 #0 DR
0 1 0 0 4H
0 1 0 1 5H
0 1 1 0 6H
, f l l f
1 1 1 0 EH
1 1 1 1 FH
data OFF-FH to G-register. (DR=0H--FH)
2. Data register (¢K1C~¢K1F)
specified by setting
It is a 16bit register for loading program memory data when DAL instruction is executed.
The contents of this register is loaded into data memory in a unit of 4 bits when lbll instruction
designated [CN=CH--FH] in the operand is executed.
This register can be used for loading LCD segment decoding operation, radio band egde data
and coefficient data at "binary to BCD" conversion, etc.
Y8 Y4 Y2 Y1 -- --
d d d d d d d d d d d
15 14 13 12 11 10 8 7 6 1
¢K1F ¢K1E ¢K1D fbKIC
MSB Program Memory 16bit Data LSB
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TOSHIBA TC9317F
C) Timer & CPU stop function
The timer has 100Hz, 10Hz and 2H2 F/F bits. It is used for counting clock operation and tuning
scan mode, etc.
The CPU STOP function is a function to stop CPU by voltage detection circuit when VDD supply
voltage drops lower than 1.5V, in order to prevent CPU miss-operation.
1. Timer port and STOP F/F bit
' It is set to "l" if less than
Reset port Timer port
l—I l—I VDD=1-5V
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
2Hz 2Hz STOP
ffL26 Timer ¢K26 10Hz 100Hz
F/F F/F F/F
l l l l
l 1 - l
k-v--'
Wenever setting "1", the 2Hz F/F, STOP F/F, 10Hz and 100Hz will be reset.
The timer port and STOP F/F bit are accessed when OUT2/IN2 instruction deisgnated [CN=6H]
in the operand is executed.
2. Timer port timing
The 2Hz timer F/F is set by 2H2 (500ms) signal. It is reset by setting "1" to 2H2 F/F of reset
port. This bit can normally be used for clock counting.
Since the 2H2 timer F/F is reset only by 2H2 F/F of reset port, count error will occur and
correct time can not be obtained unless resetting within 500ms cycles.
2Hz timer F/F output t<500ms
I I I t -
2Hz F/F reset execution l ' l I I I
I 3‘ , Il?. l fi!' ty-
2Hz clock E
' 500ms l
The 10Hz and 100Hz timers are outputted to 10Hz and 100Hz each by 50% duty pulse of 100ms
and 10ms cycle. Wenever setting "I" to the timer bit of reset port, a counter lower than 1kHz
will be reset.
10Hz 50ms I I I
100Hz 5ms I I I
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TOSHIBA TC9317F
3. CPU stop function and STOP F/F bit
In order to prevent miss-function of CPU operation, the STOP F/F bit is set to when VDD
voltage lower than 1.5V is supplied, and the CPU operation stops. The CPU operation stops
program counter at a timing of which voltage lower than 1.5V is supplied to VDD terminal, and
the execution of instruction stops.
If voltage more than 1.5V is supplied to VDD terminal again, the CPU operation will restart.
Since the CPU operation, during this period, is not performed, the clock timing, etc. will be not
correct. Whether such condition occurred can be judged by the contents of STOP F/F.
Initialization and clock correction should be done as necessary.
The STOP F/F bit will be reset to "o" whenever setting "1" to the 2Hz F/F of reset port.
VDD operation 1.5V - I - I
GND -------- Ir - -', ------
CPU l CPUstop : CPU
2Hz F/F reset operation l l operation
. A I I A
execution v; l I w
STOP F/F
(Note) The contents of timer port and STOP F/F will be reset to "o" after system reset
or CKSTP instruction is executed.
(Note) When clock stop mode setting, the CKSTP instruction will not be executed if VDD
voltage is below 1.5V. Execute the CKSTP instruction when VDD voltage is above
1.5V at the timing of radio off, etc.
(Note) The key scan data just after CPU operation is restarted will be unknown.
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TOSHIBA TC9317F
C) MUTE output
It is a 1bit CMOS type output port exclusive for muting control.
1. MUTE port
Y1 Y2 Y4 Y8
¢L16 MUTE I/O POL UNLOCK Selection of phase difference output of phase comparator
{0 : phase difference not outputted
1 : phase difference outputted
- Control of polarity of MUTE output
{0 : positive logic-MUTE bit outputted as it is
l : negative logic-MUTE bit outputted inversely
(Note) Also the phase difference output is controlled simultaneously.
- Selection of control by means of HO port input condition variation
0 : MUTE output does not change even if l/O port-l input condition
changes.
1 : MUTE bit is set to "1" by means of IIO port input state variation.
MUTE output setting
0 : The MUTE output becomes "L" level at positive logic and "H" level at
( negative logic.
1 : The MUTE output becomes "H" level at positive logic and "L' level at
negative logic.
This port is accessed when OUT1 operation designated [CN=6H] in the operand is executed. The
MUTE output is used for muting control. This has a function to set MUTE bit to "1" at band
switching by means of I/O port-1 input, etc.
This function is to prevent noises which occur at the time of linear circuit switching, in case of
band switching by HG port-1 input with a slide switch, etc. This control is done by the contents
of HO bit.
The POL bit sets up the MUTE output logic.
The MUTE output is also capable of performing muting control by means of the phase
difference output. The unlock state (when PLL system is not in lock state) is outputted as pulse.
In this case, with an external low-pass filter this output is used for MUTE output. This selection
can be done by UNLOCK bit.
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TOSHIBA TC9317F
2. MUTE output configuration and timing
"H" level
High impedance
. . . . 2 ....... . . .
POL bit DO output I I I I I L l
ll ll,,
MUTE bit Phase difference I L level
ID Cid? MUTE J LI I l-l Ic"-''''''; l,
UNLOCK bit I
UNLOCK
IIO bit bit MUTE bit
I Phase difference
l/O port-1 signal of phase comparator
of input variation
-il-l l‘l
s'-- Input phase difference
MUTE output
(Note) When POL bit="0"
(Note) When using the phase difference output of phase comparator, MUTE output should
be externally affixed with low-pass filter.
C) Test port
It is an internal port to test the function of a device.
It is accessed when OUT1 instruction designated [CN=CH] in the operand and OUT2 instruction
designated [CN=6H] in the operand are executed. In normal program it should be set to "O".
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L1C #0 #1 #2 f? /L26 #4 #5
c-v---" L-, '
Test port Test port
(Note) These contents will be reset to "o" after system reset.
C) Application for evaluator chip
If "H" level is supplied to TEST terminal (test mode), the device will operate as evaluator chip.
Three kinds of the test modes are prepared. The software development tool is configured by means
of three devices.
By connecting this software development tool to a tuner IC, confirming the radio operation while
proceeding software development can be done.
As to the development tool specifications, please refer to the specifications of TC9317F software
development tool.
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TOSHIBA TC9317F
MAXIMUM RATINGS (Ta =25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.3--4.0 V
Input Voltage VIN -0.r-VDD+0.3 V
Power Dissipation PD 400 mW
Operating Temperature Topr -10--60 "C
Storage Temperature Tstg -55--125 °C
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Ta =25°C, VDD=3.OV)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Range of Operating .
Supply Voltage VDD - .)K. 1.8 3.0 3.6 V
Range of Memory V - Crystal ocillation stopped X 1 0 ..- 3 6
Retention Voltage HD (CKSTP instruction executed) . .
Under ordinary operation and PLL on
IDD1 - operation, no output load - 0.5 1.5 mA
Operating Current IDD2 - CPU only operating (PLL off, display lit) - 50 100
In stand-by mode
IDD3 - (PLL off, crystal oscillator only) - 10 20 pA
Memory Retention I - Crystal oscillation stopped - 0 1 1 0
Current HD (CKSTP instruction executed) . .
feet Oscillation fXT - It. - 75 - kHz
requency
Crystal Oscillation . . -
Startup Time tST - Crystal oscillation fXT=75kHz - - 1.0 s
Voltage doubler circuit
Voltage Doubler
Reference Voltage VEE - GND reference (VEE) 1.3 1.5 1.7 V
Constant Voltage
Temperature DV - GND reference (VEE) - -5 - mV/°C
Characteristics
Voltage Doubler
Boosting Voltage VLCD - GND reference (VLCD) 2.6 3.0 3.4 V
Operating frequency ranges for programmable counter and if counter
FMIN fFM - Sine wave input when 1/lN=0.2Vp-p .y.f 0.5 -_- 2.5
AMIN fAM - Sine wave input when V|N=0.2Vp-p >.< 0.5 '.%- 12 MHz
IFIN hr: - Sine wave input when V|N=0.2Vp-p .):4 0.35 -- 12
Input Amplitude VIN - FMIN, AMIN, IFIN input X 0.2 _ Y3? Vp-p
FMIN-PSC
Transmission Delay tpd - PSC Ft. - - 400 ns
For conditions marked by an
asterisk (M), guaranteed when VDD=1.8--3.6V, Ta =10~60°C.
2001 -06-1 9
TOSHIBA TC9317F
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
LCD common output/segment output, general-purpose I/O ports
(COM1/P7-0--COM3/P7-2, S1/P7-r-S30/IN2)
Output High Level IOH1 - 1/LCD=3V, VOH =2.7V -300 -600 - A
Current Low Level IOU - VLCD=3V, VOL=0.3V 300 600 - /2
Output Voltage 1/2 V35 - No load 1.3 1.5 1.7 V
VIH =VLCD, VIL=0V +
Input Leak Current Ity (when I/O port or IN port) .10 pA
High Level VIH2 - (when I/O port or IN port) VLCD '.- VLCD
Input x0.6 V
Voltage VLCD
Low Level VIL2 - (when I/O port or IN port) 0 -- x0 1
HO port 1 (P1-0/KR12~P1-3/KR15)
Output High Level IOH2 - VOH=2.7V -300 -600 - A
Current Low Level IOLZ - VOL=0.3V 300 600 - /2
Input Leak Current Ity - VIH =3.0V, 1/IL=0V (when I/O port) - i 1.0 pA
Input High Level VIH2 - (when I/O port) 2.4 -- 3.0 V
Voltage Low Level 1/IL2 - (when I/O port) 0 -- 0.6
N-ch/P-ch Load VOL=3.0V, VOH =0V
- 1 2 k0
Resistance RON (when key return output) 50 00 00
HOLD input port
Input Leak Current ILI - VIH =3.0V, lhL=0V - i1.0 pA
Input High Level VIH? - - 2.4 -- 3.0 V
Voltage Low Level l/IL? - - 0 ..- 1.2
A/D converter (A/DIN1, A/DIN2, DC-REF)
Analog Input Voltage
V - AD ' AD 0 ~ V V
Range AD lhl1 lN2 DD
Analog Reference VDD
- - = . ' . V 1. -- V
Voltage Range VREF DC REF, VDD 2 0 3 6 0 x0.9
Resolution VRES - - - 6 - bit
Conversion Total - - VDD=2.0--3.6V - 11.0 14.0 LSB
VIH = 3.0V, lhL=0V +
Analog Input Leak Ity - (ADINL ADIN2, DC-REF) _1.0 pA
For conditions marked by an asterisk ()K), guaranteed when VDD=1.8--3.6V, Ta =10~60°C.
2001 -06-1 9
TOSHIBA TC9317F
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Key input ports (K0-K3)
Key Input Voltage - - --
Range VKI 0 VDD V
A/D Conversion .
Resolution VRES - - - 3 - bit
A/D Conversion VDD=1.8--2.0V - - i1.5 LSB
Combined Error - - VDD=2.0~3.6V - - $0.5
N-ch/ P-ch Input
Resistance RIN1 - - 50 100 200 k0
Output High Level VIH1 - When WAIT instruction released 1.8 ~ 3.0 V
Current Low Level VIL1 - When WAIT instruction released 0 ~ 0.3
Input Leak Current Ity - When input resistance OFF, VIH =3.0V, - - $1.0 PA
lhL=0V
DO1/OT, D02 output; MUTE, PSC output
Output High Level IOH1 - VOH=2.7V -300 -600 - A
current Low Level IOL1 - VOL=0.3V 300 600 - /4
Output Off Leak - - - - - +
Current ITL VTLH =3.OV, VTLL=OV (DOI, D02) -100 nA
General-purpose I/O ports (P2-0~P6-3)
Output High Level IOH1 - VOH=2.7V -300 -600 -
Current Low Level IOL1 - VOL=0-3V 300 600 - pA
Input Leak Current Ity - VIH =3.0V, lhL=0V - i 1.0
Input High Level VIH2 - - 2.4 '.%.. 3.0 V
Voltage Low Level VIL2 - - 0 ."- 0.6
|N1/ SCIN, RESET input port
- VIH =3.0V, lhL=0V - - +
Input Leak Current Ity (excluding SCIN input) _1.0 PA
Input High Level VIH2 - - 2.4 .'%.' 3.0 V
Voltage Low Level VIL2 - - 0 ..%- 0.6
Others
Input Pull-Down
Resistance RINZ - (TEST) 15 30 60 k0
XIN Am Feedba k
Resistange c RfXT - (NN-XOUT) - 20 - Mn
XOUT Output
Resistance ROUT - (XOUT) - 4 - kn
In t Am Feedback
kne'busttaSl'' RfIN1 - (FMIN, AMIN, IFIN/SCIN) 500 1000 2000 kn
Voltage Used to
Detect Supply Voltage VSTp (VDD) 1.35 1.5 1.6 V
Supply Voltage Drop
Detection Temperature Ds - (VDD) - -3 - mV/°C
Characteristics
For conditions marked by an asterisk (X), guaranteed when VDD=1.8--3.6V, Ta =10~60°C.
2001 -06-1 9
TOSHIBA TC9317F
PACKAGE DIMENSIONS
LQFP80-P-1212-0.50A Unit : mm
14.0:02 _
12.0i0.2
1 .25TYP
12.0i02
14 0:0 2
1.25TYP_ "
0.1 :3...
13.0i0.2 9;?
e"? JEE
0.5i0.2
Weight : 0.45g (Typ.)
76 2001-06-19
TOSHIBA TC9317F
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
77 2001-06-19
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www.loq.com
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Partno	Mfg	Dc	Qty	Available	Descript
TC9317F	TOSHIBA	N/a	50	avai	DTS MICROCONTROLLER (DTS-21)
TC9317F	TOS	N/a	295	avai	DTS MICROCONTROLLER (DTS-21)