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TC9309AF
SINGLE CHIP DTS MICROCONTROLLER (DTS-10)
TOSHIBA TC9309AF
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9309AF
SINGLE CHIP DTS MICROCONTROLLER (DTS-10)
The TC9309AF is a 4bit CMOS microcontroller for single
chip digital tuning system with built-in prescaler, PLL and
LCD driver.
The CPU has 4bit parallel addition/subtraction (Al, SI
instructions, etc.) logical operation (OR, AN instructions,
etc.) multiple bits judgment, comparison instructions (TM,
SL instructions, etc.) and time base functions.
The TC9309AF is housed in as 80pin mini-flat package
and is provided with ample I/O ports and exclusive key
input ports which are controlled by powerful l/O
instructions (IO, KEY instruction, etc.) and 1/2 duty and 1 QFP80-P-1420-0.80A
/2 bias driving ample LCD use exclusive output terminals. Weight : 1.57g (Typ.)
In addition, the TC9309AF has built in 2 modulus prescaler, PLL circuit, and IF counter that counts
intermediate frequency (IF) in FM and AM bands for detecting broadcasting stations.
Furthermore, the TC9309AF has built in serial bus control function (SIO instruction) to powerfully
control peripheral ICs, 6bit A/D converter and D/A converter that are usable for field strength
measurement and electronic volume control, and provides with many functions needed for digital
tuning system.
FEATURES
0 4bit microcontroller single chip digital tuning system.
It 5Vl 10% single power supply, CMOS structure for low power dissipation.
o Built-in prescaler (Max. 140MHz signal is directly input in FM band), PLL and LCD driver (1 /2 duty,
1/2 bias, frame frequency : 100Hz, 64 segments).
0 Easy back up of data memory (RAM) and various ports (by the IN-H terminal).
0 Program memory (ROM) : 16 bitsx3968 steps
0 Data memory (RAM) .' 4 bitsx 256 words
It 61 kinds of powerful instructions sets (all single word instructions)
1 2001-06-19
TOSHIBA TC9309AF
0 Instruction execution time 11.1ps (7.2MHz crystal connection)
0 Abundant add and subtract instructions (Add instruction : 12, subtract instruction : 12)
It Powerful composite judging instructions (TMTR, TMFR,
TMT, TMF instructions, etc.)
0 Data transfer at the same row address is possible.
0 Register indirect transfer is possible (MVGD, MVGS instructions)
0 Powerful 16 general registers (arranged in RAM)
It Stack level : 2 levels
0 Program memory (ROM) has no conception of page and field, and JUMP and CAL instructions can
be freely contained in 3968 steps.
Further, contents of 16bits data at any address in 1024 steps can be freely referred (DAL
instruction)
0 Built-in 16bit general-use IF counter (IFIN1, IFINZ)
0 Independent frequency input terminals for FM and AM (FMIN, AMIN), 2 phase comparator outputs
(D01, D02)
0 10 reference frequencies are programmable selectable (1, 3.125, 5, 6.25, 9, 10, 12.5, 25, 50, 100kHz)
0 Pulse swallow system and direct frequency division system are selectable by program according to
receiving frequency band.
0 IF correction at FM band is possible (Internal port for IF offset)
It Built-in powerful serial bus control function (I/O port-2 terminals are selectable by program.)
It Powerful I/O instructions (IO, KEY, SIO instruction, etc.)
0 Exclusive key input port (KO--K3), abundant 32 terminals LCD driver.
0 IF counter inputs (IFIN1, IFINZ) and input ports (IN1, IN2) are selectable by program.
0 Max. 34 HO ports (I/O settable ports : 15, output ports : 12, input ports : max. 7)
It Clock stop is possible by program (at CKTSP instruction : supply current below 10pA)
o Built-in 2H2 timer F/F, 10/100Hz internal pulse output (Internal port for time base)
It Locked state of PLL is detectable (Internal port for PLL lock detection)
0 Built-in 6bit A/D and D/A converters (Selectable by selecting I/O port-3 terminals (P3-1--P3-3) by
program).
9 OTP product : TC93PO9F
2 2001-06-19
TOSHIBA TC9309AF
PIN CONNECTION
m I - -
- 0 V - u Cl o
V) vs U W Cy 4 <
"ss "s, "s "s "ss "s "s
- '- N m
- m I I I I l I I I I I I I I I I '- N m "
E a Lu '- '- '- '- N N N N m m m - _ CL CL n. n. 0. a. a. n. n. n. n. n. n. n. o. C) C) C) O - _
54 53 46 45
IFINzllNZ I I T5
I/O Ports (15) output port
lFIN1/lN1 T4
D02 T3
Key Return
D01 output T2
GND2 TI
FMIN T0
AMIN K3
MFP-80PIN
DD Key input
GND1 TOP VIEW port K1
7T l 74 K0
XT I75_ N.C
COM? COM1
SI S32
S2 S31
S3 $30
S4 LCD driver output (34 : 2x32 = 64 segment) S29
tr3_ttg'yuyrsa3trtC)m-CqtvtxttrttDrsa7
x-r-r-es-er-tNNN}''"}?.)?.
M5V5V5M9V9V3V5V9C0V5V5V5V5M9C0V,
3 2001-06-19
TOSHIBA
BLOCK DIAGRAM
INH Wait 100Hz SOHZ 10Hz
CPU Timing Gene.
2Hz F/F
TC9309AF
Reference Divider I DOI
1 3 D02
__1 t, -
LL th SYSTEM WI
't E Reset
_ _. U
FM 2 Modulus 4bit Swallow 4 o
IN Prescaler Counter 3 Power on VDD
E Reset
AMIN 12bit ''g'1T,"na" Wait
Detector
IFIN1/lhll 16bit IF Counter
'FINz/INZ IF Counter Count. PLL Port La. TEST
GND2 - --ifAra BUS
CODE BUS l
COLUMN Comparator l
fl RAM 6bit D/A Conv l
"' - ---- - - u P3-3/ADIN2
g (4x256 Word) La IDAOUT
H P3-2/ADIN1
E ROM P3-1/D0REF
'fe 4 La.
i',' (16x3968 Step) R/W Buf
m 4 4 Shift Reg.
3 SIO Cont
Select
P2-4/STB
. PZ-3/CK
Instruction P2-2 ISO
Dec. P2-1 ISI
Addr. Dec.
12 P4-2
Prog, Counter
12 PI-?
50Hz100Hz Stack Reg.(2 Level)
LCD ment La.
LCD Driver
COM12 SI2345- 2829303132K0123T0123 T4567 OT1234
TOSHIBA
TC9309AF
PIN FUNCTION
SYMBOL
PIN NAME
FUNCTION/OPERATION
REMARKS
LCD Common
Output
Common signal output terminals to LCD.
Maximum 64 segments can be displayed in
a matrix with S1~S32.
Three levels of VDD, 1/2 VDD and GND
are output to these terminals in a 50Hz
cycle at intervals of Sms.
(Note) At time of system reset and
execution of CKSTP and DISP OFF,
output is automatically fixed at "L"
level.
S1--S4
S5--S32
LCD Segment
Output
Segment signal output terminals to LCD.
Maximum 64 segments can be displayed in
a matrix with COM1 and COM2.
Data are output to these terminals by
executing SEG instruction (COM1 system)
and MARK instruction (COM2 system).
As to segment decoding, it is possible to
perform it by creating its decoding pattern
in ROM area and using DAL command.
(Note) At time of system reset and
execution of CKSTP command and
DISP OFF, output is automatically
fixed at "L'' level.
(Refer to Note 3.)
No Connection
As this terminal is not connected to
internal chip, it can be left open or
connected to GND or VDD freely.
In case of OTP product TC93P09F, this
terminal serves as I/pp terminal and
TC93P09F is readily usable when connected
to VDD.
Key Input Port
4bit input ports for key matrix input.
When KEY instruction these ports specified
in the operand is executed, data of these
terminals are read in RAM.
All terminals have built in pull-down
resistors.
Further, the output ports TO-T? are
normally used for key return timing signal.
2001 -06-1 9
TOSHIBA TC9309AF
m“ SYMBOL PIN NAME FUNCTION/OPERATION REMARKS
4bit (T0~T3) and 4bit (T4-T7) output VDD
Ke Timin terminals.
35--42 T0--T7 y g These ports are normally used for key
Output Port . . . .
return timing signal output of key matrix.
(Refer to Notes 2 and 3.)
General-Purpose 4bit output ports.
4 ~4 T4~ T1
3 6 O 0 Output Port (Refer to Notes 2 and 3.) il-
4bit (P4-1--P4-4) and 4bit (P1-1~P1-4) l/O
ports. VDD
I/O designation for every bit can be made
47--50 P4-4--P4-1 I/O Port 4 for these ports. F
58--til P1-4~P1-1 l/O Port 1 This designation is made according to
contents of the internal ports called PORT4, "
PORT1 I/O CONTROL.
(Refer to Notes 1, 2 and 3.)
2001 -06-1 9
TOSHIBA TC9309AF
['l') SYMBOL PIN NAME FUNCTION/OPERATION REMARKS
3bit I/O ports.
l/O designation for every bit can be made
for these ports.
This designation is made according to
contents of the internal port called PORT-3
I/O CONTROL.
Further, these terminals also serve for the
analog input of the built-in 2-channel A/D
converter and analog output of I-channel
D/A converter.
51 P3-3 l/O Port 3 A/D and D/A converter input/output
/ADIN2 /AD Analog . . .
Voltage Input selection IS controlled according to contents
/DAOUT /DA Analog of ADO.N’.DAON or ADSEL p't' VDD
Voltage The built-in A/D converter IS of
programmably sequential comparison type, '-
Output . .
52 P3-2 y? P3-1 IS the referen.ce voltage Input, P3- "
/ADIN1 /AD Analog 2 IS the ahalog comparison voltage input,
Voltage Input .and P3-3 IS the analog comparison voltage To AD or DA
53 P3-1 input or analog voltage output. converter
(Note) A ladder resistance that generates
/DC-REF /Reference . .
Voltage Input internal D/A reference voltage IS
used commonly by the A/D and D/
A converters.
When both the A/D and D/A
converters are used simultaneously,
DAON bit is set to "o" and D/A
output is made to high impedance
at time of A/D conversion.
It is therefore necessary to hold
potential with a capacitor, etc.
(Refer to Notes 1, 2 and 3.)
4bit I/O ports.
I/O designation for every bit can be made
for these ports.
I/O Port 2 This designation is made according to
P2-4/STB /Strobe Pulse contents of the internal port called PORT-2 VDD
Output I/O CONTROL.
P2-3/CK /Serial Clock Further, these terminals are also used as F
54--57 Output the serial interface (SIO).
P2-2/SO /Serial Data Selection of SIO is controlled according to F
Output contents of SIO ON bit and in case of these
P2-1/SI /Serial Data serial interface, peripheral optional ICs can
Input be controlled by executing SIO command.
Serial transfer in NCD mode is
programmably selectable.
(Refer to Notes 1, 2 and 3.)
2001 -06-1 9
TOSHIBA
TC9309AF
SYMBOL
PIN NAME
FUNCTION/OPERATION
REMARKS
Test Mode
Control Input
Test mode control input terminal.
The device is put in the test mode when
"H" level signal is input and becomes the
normal operating state when "L" level
signal is input or in NC state.
(A pull-down resistor has been built in.)
Initialize Input
Device system reset signal input terminal.
As long as the N terminal is kept at "L"
level, a system is kept in the reset state
and when it becomes "H" level, a program
startes from address 0.
Normally, the system is reset when 0~3.5V
is supplied to the VDD terminal (Power ON
Reset) and therefore, this terminal is used
by fixing at "H" level.
(Note) After the system reset, l/O ports
are set in the input mode.
However, the output state of output
ports is indefinite and it is necessary
to initialize them by program.
Inhibit Input
Terminal
This is the m port input terminal.
Normally, this terminal is used for radio
mode selecting signal input or battery
detection signal input.
When CKSTP instruction is used in a
program and this CKSTP instruction is
executed while the IN-H terminal is at "L''
level, it is possible to stop the internal
clock generator and CPU operation and put
a system in the memory backup state with
low current consumption (below 10pA).
(Note) CKSTP instruction is effective when
the IN-H terminal is at "L'' level and
when this instruction is executed at
"H" level, the same operation as
NOOP instruction results.
(Note) In the radio OFF mode or back-up
mode, it is necessary to set
reference internal ports (4 bits) at
all "I" (PLL OFF mode).
2001 -06-1 9
TOSHIBA
TC9309AF
SYMBOL
PIN NAME
FUNCTION/OPERATION
REMARKS
lFIN2/IN2
IFIN1/lbl1
lF Signal
Input 2
/Input Port 2
IF Signal
Input 1
/Input Port 1
IF signal input terminal of IF counter that
detects auto stop by counting IF signal in
FM and AM bands.
Input frequency range is 0.1--20MHz
(om/p-p Min.)
Having a built-in input amplifier, operates
at small amplitude in C-connection.
These terminals are usable programmably
as input ports, and are selectable according
to contents of the IN CONTROL Port.
(Note) When IF counter is used, reference
internal ports (4 bits) are set at all
"1" or inputs that are not selected
by IFIN1 bit (input selecting bit) are
pulled down.
(Refer to Note 1)
Comparator
Output
PLL phase comparator output terminal.
Tri-state output.
If devided output signal from the
programmable counter is higher than
reference frequency, "H" level signal is
output and if it is lower, "L" level signal is
output and if matched, it becomes high
impedance.
Signals from DOI and D02 are parallelly
output.
Analog GND
Terminal
GND terminal only for PLL, lF counter and
AD/DA converter analog units.
FM Band Signal
Programmable counter input terminal for
FM band.
The 1/2 +pulse swallow system (FMH
mode) and the pulse swallow system (FML
mode) are selectable by PLL instruction.
In case of the pulse swallow system, local
oscillation output (VCO output) of
10--140MHz (0.3Vp_p Min.) is input and in
case of 1/2 prescaler input, 10--185MHz
(0.5Vp_p Min.) is input.
Having a built-in input amplifier, operates
at small amplitude with a capacitor
connected.
(Note) When reference internal ports (4
bits) are set at all "I" or LF Mode
or HF Mode is set, this input is
pulled down.
2001 -06-1 9
TOSHIBA
TC9309AF
SYMBOL
PIN NAME
FUNCTION/OPERATION
REMARKS
AM Band Signal
Programmable counter input terminal for
AM band.
The direct dividing system (LF mode) and
the swallow system (HF mode) are freely
selectable by PLL instruction.
In case of the direct dividing system (LF
Mode), local oscillation output (VCO
output) of 0.5~20MH2 (om/p-p Min.) and
in case of the pulse swallow system,
1~40MH2 (0.3Vp_p Min.) is input.
Having a built-in input amplifier, operates
at small amplitude with a capacitor
connected.
(Note) When reference internal ports (4
bits) are set at all "I" or FMH
Mode or FML Mode is set, this input
is pulled down.
Power Supply
Terminal
Power supply terminal.
At time of PLL operation, 5V1 10% is
applied.
In the back-up state (when executing
CKSTP instruction), voltage can be reduced
to 2V.
Further, when voltage drops below 3.5V
during the operation of CPU, CPU stops
(CPU Wait Mode) to prevent miss-function,
it restarts when voltage increases above
As (Wait Mode) resulted under this
condition can be detected by Wait F/F bit,
perform initialization, clock correction, etc.
by program.
Further, when 0 to 3.5V is applied to this
terminal, a device is reset and a program
starts from address 0 (power On Reset).
(Note) Rise time of supply voltage on a
device shall be 10--100ms for the
power ON reset operation.
(Refer to Note 1)
Digital GND
Terminal
GND terminal for CPU and the logic unit.
2001 -06-1 9
TOSHIBA TC9309AF
KIT SYMBOL PIN NAME FUNCTION/OPERATION REMARKS
Crystal resonator connecting terminal. sz '
- Crystal Connect a 7.2MHz crystal to this terminal. VDD
74 XT 0 ill ti Adjust oscillation frequency (7.2MH2) while
SCI a Ion .
75 XT Terminal observing LCD segment waveform. X F-
When CKSTP instruction is executed, T
oscillation stops automatically. "
(Note 1) When a device is reset NDD--0-93.5V and "flii"if=''L''-9"H''), I/O ports are set to
the input, terminals serving as l/O ports and AD/DA converters are to the input
of I/O ports, terminals serving as I/O ports and serial I/O ports are set to the
input of I/O ports, and terminals serving as IF counter input and input port are
set to IF counter input.
(Note 2) When CKSTP instruction is executed, outputs of the output ports and HG ports
are all set at "L" level.
(Note 3) When a device is reset, contents of output ports and internal ports are indefinite
and it is therefore necessary to initialize them by program.
11 2001-06-19
TOSHIBA TC9309AF
DESCRIPTION or OPERATION
CD CPU
The CPU consists of a program counter, stack register, ALU, program memory, data memory,
G-register, data register, carry F/F, and judge circuit.
PC PC1 1 PC10 PC9 PC8 PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO
Program counter (PC)
The program counter is a counter for addressing program memory (ROM) and consists of a
12bit binary up counter.
This counter is cleared by system resetting and a program starts from address 0.
Normally, whenever one instruction is executed, the count value is incremented by one.
When JUMP instruction or CAL instruction is executed, the address designated in the operand
of that instruction is loaded.
Further, when an instruction having the skip function (AIS, SLT, TMT, RNS instructions, etc.) is
executed and the result is a condition to be skipped, the program counter is incremented by
two and skips next instruction.
MSB LSB
12 bits
2. Stack register (STACK)
This is a register consisting of 2x 12 bits and a value of the program content+ 1, that is,
return address is stored in this register when the subroutine call instruction is executed.
The content of the stack register is loaded on the program counter when a return instruction
(RN, RNS instruction) is executed.
The stack register has 2 stack levels and nesting is 2 levels.
The ALU has the binary 4bit parallel addition and subtraction, logical operation, comparison
and multiple bit judging functions.
Further, this CPU has no accumulator and contents of the data memory are directly treated in
all operation.
12 2001-06-19
TOSHIBA TC9309AF
4. Program memory (ROM)
The program memory, consisting of 16 bitsx3968 steps, stores programs.
Usable address range is 3968 steps from address OOOH to address F7FH.
The program memory has no concept of page and field, and JUMP and CAL instructions are
freely usable in 3968 steps.
Further, it is possible to use any address of the program memory as data area and to load its
contents in 16 bits in the data register by executing DAL instructions.
(Note) Data area in the program memory shall be provided at address outside the
program loop.
(Note) Address in the program memory designatable as data area at time of DAL
instruction execution is within 1024 steps from OOOH to 3FFH.
F7FH 000H
ROM 16 bitsx 3968 steps
3968 steps
5. Data memory (RAM)
The date memory consists of 4 bitsx256 words and is used for data storage.
These 256 words are expressed by row address (4 bits) and column address (4 bits).
192 word (row address=4H--FH) in the data memory are indirectly addressed by G-register.
Therefore, when data in this area are processed, it is necessary to perform the processing
after designating row address in advance with G-register.
Further, address 00H ~0FH in the data memory are called the general register and usable only
by designating column address (4 bits).
These 16 general registers can be used for operation and transfer with the data memory.
In addition, it is also possible to use them as ordinary data memories.
(Note) Column address (4 bits) designating a general register becomes Register No. of
that general register.
(Note) It is also possible to indirectly designate all row addresses (0H~FH) by G-register.
13 2001-06-19
TOSHIBA TC9309AF
COLUMN ADDRESS : DC
0123456789ABCDEF
l 0 GENERAL REGISTER
Jf l 1 (One of Addresses 00H--OFH)
Indirectly designate 9
row address(4H-FFO
by G-register. A
.).K. Indirect designation of E
row address 0H~FH is F
also possible.
RAM (4 bits x 256 words)
6. G-Register (G-REG)
The G-register is a 4 bits register for addressing row addresses (DR=4H--FH) of 192 words of
the data memory.
Contents of this register becomes effective when MVGD/MVGS instruction is executed and
have nothing to do with execution of other instructions.
This register is treated as one of ports and its contents are set when IO instruction is
executed.
(Refer to Item 1 of Resister Ports.)
7. Data register (DATA REG)
This register consists of 1x 16 bits and 16bit data of any address 000H--3FFFH of the program
memory is loaded when DAL instruction is executed.
This register is treated as one of ports and its contents are read in 4 bits unit into the data
memory when KEY instruction out of I/O instructions is executed.
(Refer to Item 2 of Register Ports.)
8. Carry F/F (C.F/F)
This carry F/F is set when carry or borrow was generated as a result of execution of the
calculation instruction and is reset when there is no carry nor borrow.
Contents of the carry F/F change only when the addition/subtraction instruction was
executed and remain unchanged when other instructions were executed.
14 2001-06-19
TOSHIBA TC9309AF
9. Judge circuit (J)
When any instruction having a skip function was executed, this circuit judges that skip
condition. If the skip condition was satisfied, the program counter is incremented by two and
skips a following instruction.
There are 29 instructions having the skip function.
(Refer to instructions with the *mark on the List of Function and Operation of in Item 11)
10.List of instructions sets
Total 61 instruction sets are available and they are all one word instruction.
These instruction are expressed in 6 bits instruction code.
HIGH ORDER 00 01 10 11
ORDER 2 BITS
4 BITS 0 1 2 3
0000 0 Al M, I AD r, M SLTI M, I
0001 1 AIS M, I ADS r, M CALL ADDR1 SGEI M, I
0010 2 AIN M,I ADN r, M SEQI M,I
0011 3 SI M, I su r, M SNEI M, I
0100 4 SIS M, I sus r, M MVSR M1, M2
0101 5 SIN M, I SUN r, M MVIM M, I
0110 6 LD r, M ORR r, M MVGD r, M JUMP ADDR1
0111 7 ST M, r ANDR r, M MVGS M, r
1000 8 AIC M, I AC r, M PLL M, c TMTR r, M
1001 9 AICS M, I ACS r, M SEG M, c TMFR r, M
1010 A AICN M, I ACN r, M MARK M, c TMT M, N
1011 B SIB M, I SB r, M IO M, c TMF M, N
1100 c SIBS M, I SBS r, M KEY M, c TMTN M, N
1101 D SIBN M, I SBN r, M SIO M, c TMFN M, N
1110 E SEQ r, M ORIM M, I XORIM M, I DAL ADDR2, r
RN,RNS,
1111 F SNE r, M ANIM M, I XORR r, M CKSTP, NOOP
15 2001-06-19
TOSHIBA
TC9309AF
11.List of functions and operation of instructions
(Explanation of symbols on list)
: Data Memory Address
Usually, one of data memory addresses 00H~3FH
: General Register
One of data memory addresses 00H~0FH
: Program Counter(12 bits)
: Stack Register(12 bits)
: G-Register(4 bits)
: Data Register(16 bits)
: Immediate Data (4 bits)
: Bit Position (4 bits)
: ALL "o"
: Port Code No. (4 bits)
Low order 3 bits of Port Code No.
: General Register No.(4 bits)
: Program Memory Address(12 bits)
High order 6 bits of Program Memory Address in Page 0.
: Carry
: Borrow
: Port treated by execution of PLL instruction
: Port treated by execution of SEG instruction
: Port treated by execution of MARK instruction
: Port treated by execution of IO instruction
: Port treated by execution of KEY instruction
: Port treated by execution of SIO instruction
: Contents of register or data memory
: Contents of port shown by Code No. C(4 bits)
: Contents of Data Memory shown by contents of Register or Data Memory
: Contents of Program Memory(16 bits)
: Instruction Code(6 bits)
.' Instruction with skip function
: Data Memory Column Address (4 bits)
.' Data Memory Row Address(2 bits)
16 2001-06-19
TOSHIBA TC9309AF
a? a MACHINE LANGUAGE (16bit)
(0 MNEMONIC I: EXPLANATION OF EXPLANATION OF
b-, g% FUNCTION OPERATION IC A B c
3 YE? (6bit) (2bit) (4bit) (4bit)
AI M, Add immediate data M_-(M) +I 000000 DR Dc I
to memory
Add immediate data
AIS M, to memory, then skip “W” M 000001 DR DC I
. Skip if carry
if carry
Add immediate data
AIN M, to memory, then skip MW” M 000010 DR DC I
. Skip if not carry
if not carry
AIC M, Add immediate data M_-(h/1) +I+ca 001000 DR Dc I
to memory with carry
Add immediate data
AICS M, to memory with carry, “#0” +I+ca 001001 DR Dc I
. . Skip if carry
then skip if carry
a Add immediate data
.: AICN M, to memory with carry, MW” +I+ca 001010 DR Dc I
U . . Skip if not carry
a then skip if not carry
F- Add memory to
Z AD r, M general register re-(r) + (M) 010000 DR Dc RN
2 Add memory to
E ADS r, M general register, then T.(r). + (M) 010001 DR Dc RN
Cl ki if Skip if carry
2 s Ip I carry
Add memory to
ADN r, M general register, then T.(r). + (M) 010010 DR DC RN
. . Skip if not carry
skip if not carry
Add memory to
AC r, M general register with re-(r) + (M) +ca 011000 DR Dc RN
Add memory to
general register with re-(r) + (M) +ca
ACS r, M carry, then skip if Skip if carry 011001 DR DC RN
Add memory to
general register with re-ir) + (M) +ca
ACN r, M carry, then skip if not Skip if not carry 011010 DR DC RN
2001 -06-1 9
TOSHIBA
TC9309AF
MACHINE LANGUAGE (16bit)
borrow, then skip if
not borrow
Skip if not borrow
0. MNEMONIC 1: EXPLANATION OF EXPLANATION OF
b-, .es/sl FUNCTION OPERATION IC A B c
3 YE? (6bit) (2bit) (4bit) (4bit)
Subtract immediate
M, I data from memory Mt- (M) -l 000011 DR Dc I
Subtract immediate
M M -l
M, I data from memory, t-(. ) 000100 DR Dc I
. . Skip if borrow
then skip if borrow
Subtract immediate
data from memory, Me-(M) -l
M, I then skip if not Skip if not borrow 000101 DR DC I
borrow
Subtract immediate
M, I data from memory, Me-iM) -l-b 001011 DR DC I
with borrow
Subtract immediate
data from memory h/le-IM) -l-b
a M, I with borrow, then Skip if borrow 001100 DR DC I
f?: skip if borrow
g Subtract immediate
= data from memory iVR-(M) -l-b
'il M, I with borrow, then Skip if not borrow 001101 DR DC I
a skip if not borrow
ir-" r, M Subtract me.Tory from re-(r) - (M) 010011 DR Dc RN
3 general register
td Subtract memory from
F- . re-(r) - (M)
g r, M ge-ne-ral register, then Skip if borrow 010100 DR Dc RN
W skip if borrow
Subtract memory from
r, M general register, then 3:“). (M) 010101 DR Dc RN
. . IP if not borrow
skip if not borrow
Subtract memory from
r,M general register with re-ir) - (M) -b 011011 DR Dc RN
borrow
Subtract memory from
general register with re-(r) - (M) -b
r, M borrow, then skip if Skip if borrow 011100 DR DC RN
borrow
Subtract memory from
r, M general register with re-ir) - (M) -b 011101 DR DC RN
2001 -06-1 9
TOSHIBA
TC9309AF
INST. GR.
MNEMONIC
FUNCTION
EXPLANATION OF
FUNCTION
EXPLANATION OF
OPERATION
MACHINE LANGUAGE (16bit)
(6bit)
(2bit)
(4bit)
(4bit)
SLTI M, I
Skip if memory is less
than immediate data
Skip if(M) 1 10000
SGEI M, I
Skip if memory is
greater than or equal
to immediate data
Skip if (M) 2|
SEQI M, I
Skip if memory is
equal to immediate
Skip if(M) =l
SNEI M, I
Skip if memory is not
equal to immediate
Skip if (M) #l
COMPARISON iNSTRUCTlON
SEQ r, M
Skip if general
register is equal to
memory
Skip if (r) = (M)
SNE r, M
Skip if general
register is not equal
to memory
Skip if(r) = (M)
LD r, M
Load memory to
general register
re- (M)
ST M, r
Store general register
to memory
Me- (r)
MVSR M1, M2
Move memory to
memory in the same
(DR, DCI)e-(DR, DC2)
MVIM M, I
Move immediate data
to memory
TRANSFER INSTRUCTION
MVGD r, M
Move memory to
destination memory
referring to G-register
and general register
((G),(r)) --(hll)
MVGS M, r
Move source memory
referring to G-register
and general register
to memory
Me- ((G),(r))
2001 -06-1 9
TOSHIBA
TC9309AF
m. a MACHINE LANGUAGE (16bit)
L9. MNEMONIC 1: EXPLANATION OF EXPLANATION OF
tr, t.sfi/: FUNCTION OPERATION IC A B c
3 tiii? (6bit) (2bit) (4bit) (4bit)
Input PLL port data to Mt- (PLL) C DR DC 0 CN
PLL M, C gjngcycontents of 101000
memory to PLL port ( PLL) ce-IM) DR DC 1 CN
Input SEG port data to Mt- ( SEG) C DR DC 0 CN
memory
a SEG M, C Output contents of 101001
f? memory to SEG port (SEG) ce-(M) DR DC 1 CN
2 Input MARK port data Mt- ( MARK) C DR DC 0 CN
F- to memory
m MARK M, C Out ut contents of 101010
F..i.r. p ( MARK] ce-(hh) DR DC 1 CN
r- memory to MARK port
'd: Input IO port data to Mt- ( IO) C DR DC 0 CN
CD IO M c memory 101011
0 ' Output contents of
( IO) ce- (M) DR Dc 1 CN
C23 memory to IO port
F- Input KEY port data Mt- ( KEY) C DR DC 0 CN
CD to memory
IL KEY M, C Output contents of 101100
- memory to KEY port ( KEY) ce-iM) DR DC 1 CN
Serial input port data
of external device to h/R- ( SIO] C DR Dc 0 CN
memory
SIO M, C Serial output contents 101101
of memory to port of [SIO] ce-M DR Dc 1 CN
external device
Logical OR of general
(23 ORR r, M register and memory rt- (r)V(M) 010110 DR DC RN
1: Logical AND of
'd ANDR r, M general register and re-(r)A(M) 010111 DR Dc RN
E memory
a Logical OR of memory
a ORIM M, I and immediate data Me-(M)VI 011110 DR DC I
Q Logical AND of
t ANIM M, I memory and Me-(M)/NI 011111 DR Dc I
E immediate data
8 Logical exclusive OR of
__. XORIM M, I memory and Me-iM) (Pl 101110 DR Dc I
if, immediate data
6 Logical exclusive OR of
Il XORR r, M general register and re-ir) ff) (M) 101111 DR Dc RN
memory
20 2001-06-19
TOSHIBA TC9309AF
of a MACHINE LANGUAGE (16bit)
L9. MNEMONIC 11' EXPLANATION OF EXPLANATION OF
tr, t.sfi/, FUNCTION OPERATION IC A B c
3 if/i? (6bit) (2bit) (4bit) (4bit)
Test general register
bits by memory bits, Skip if r ( N(M)]
TMTR r, M then skip if all bits =all "1" 111000 DR DC RN
specified are true
Test general register
bits by memory bits, Skip if r ( N(M)]
s5 TMFR r, M then skip if all bits =all "o" 111001 DR DC RN
t," specified are false
a: Test memory bits, . .
'ii TMT M, N * then skip if all bits Skip if M(N)=a, "I" 111010 DR DC N
T.i specified are true -
© Test memory bits
Ch ' . .
R TMF M, N * then skip if all bits Skip if M(N)=a, "o" 111011 DR DC N
bc: specified are false -
Test memory bits, . .
TMTN M, N * then not skip if all Skip if M(N) " " 111100 DR Dc N
. . . =not all 1
bits specified are true
Test memory bits, . .
TMFN M, N * then not skip if all Skip if M(N) " " 111101 DR DC N
. . . =not all 0
bits specified are false
. STACKe-(PC) +1 and .
Q CAL ADDR1 Call subroutine PG-ADDR, 1000 ADDR1 (12bit)
Lula Return to main
F212 RN . PCe-(STACK) 111111 00 - -
31- routine
OZ.' Return to main
g RNS * routine and skip t','fi,tisTAcK)and 111111 01 - -
m unconditionally p
MG Jump to the address
:23: JUMP ADDR1 . . PCe-ADDRI 1101 ADDR1 (12bit)
2r,tE specified
w Load program
mCZ) DAL ADDR2, r memory in page 0 to "et/ere e 0 111110 A(Etligz RN
$5 DATA register P p g
CE CKSTP Clock generator stop 1tiill?i-cicro,ctyenerator 111111 10 - -
S if INH - 0
- NOOP No operation - 111111 11 - -
21 2001-06-19
TOSHIBA TC9309AF
(Note 1)
(Note 2)
(Note 3)
(Note 4)
When executing I/O instruction, input/output of the instruction is automatically
controlled according to a value of the most significant bit of Port Code No. (C).
It MSB of Code No.(C) ="1" : Output instruction
9 MSB of Code No. (C) ="0" : Input instruction
Basically execution of SIO instruction is treated similar to execution of other l/O
instructions (PLL instruction, SEG instruction, etc.) except the following points :
0 First, it is necessary to select an external device that becomes a destination of
transferring serial data by the chip select code ((C)=FH).
(Refer to Item 1 of Serial Interface.)
0 SIO instruction execution time is 55.5ps (5 machine cycle).
As the TC9309AF has no input port that is treated in the execution of SEG and
MARK instructions, this input instruction cannot be used.
Low order 4 bits out of the program memory address 10 bits designated by DAL
instruction are to be indirectly addressed according to contents of the general
register.
DAL instruction execution time is 22.2ps (2 machine cycle).
22 2001-06-19
TOSHIBA TC9309AF
O Connection of crystal resonator
Connect a 7.2MH2 crystal resonator to the crystal oscillator terminal (XT, Fterminal) of a device
as illustrated below. This oscillation signal is supplied to the clock generator and the reference
frequency divider for generating various CPU timing signals and reference frequency signals.
Adjust crystal oscillation frequency while monitoring segment output terminal.
(FT) (XT) t
ll 'tal X'tal=7.2MHz
CL=10~50pF (30pF Typ.)
CL; CL
(Note) Use a crystal resonator having a low CI value and good starting characteristic.
C) System reset
When "L" level signal is input to the fiiTi" terminal or O--3.5V is supplied to the VDD terminal
(Power ON Reset), system reset is applied to a device. After 10ms of standby time passed after
the system reset, a program starts from address 0.
Normally, as the Power ON reset function is used, the TNif terminal shall be fixed at "H" level.
(Note 1) During the system reset and subsequent standby time, LCD common output and
segment output are fixed at "L" level.
(Note 2) After the system reset, I/O ports are all set in the input mode.
However, no initialization of output ports and internal ports (G-Register, etc.) is
performed. In particular, contents of these ports become indefinite when the power
source is initially turned on and therefore, it becomes necessary to initialize them
programmatically as necessary.
23 2001-06-19
TOSHIBA TC9309AF
C) Clock stop mode
If CKSTP instruction was executed when the Ttil-pf terminal is at "L" level, the clock generator and
CPU in a device stop to operate completely and it becomes possible to get the memory back-up
state with low current consumption (10/1A Max. at VDD=5V).
At this time, the LCD display output terminals and output ports are all fixed at "L" level
automatically and programmatic process of the output terminals are not necessary.
In this clock stop mode, supply voltage can be dropped to 2V.
In the clock stop mode, a program stops at the executing address of CKSTP instruction, the clock
stop mode is released when the W terminal becomes "H" level and after 10ms of standby time
passed, the instruction of next address is executed.
(Note 1) In the clock stop mode, the output terminals are all fixed at "L" level but data
immediately before the clock stop mode are kept in the contents of the output ports.
(Note 2) If CKSTP instruction was executed during W: "H" level, the same operation as NOOP
instruction is carried out. (The system is not put in the clock stop mode.)
(Note 3) ON/OFF of PLL circuit is performed according to contents of the reference port. It is
therefore necessary to put a device in the PLL OFF mode (to set the reference port
data "F") before CKSTP instruction is executed.
VDD 72 . . " ( Power Power
tj. 5, +
;l t , E t l
'" El 2 ..
Example of Battery Back-Up Circuit Example of Capacitor Back-Up Circuit
24 2001-06-19
2001 -06-1 9
O IIO PORT
PLL(¢1)
SEG [com 1
MARK ( c0M2]
IO (¢4)
KEY (¢ 5)
510 (¢a)
Y1|Y2|Y4|Y8
Y1]Y2|Y4|va
Y1‘Y2|Y4|Y8
Y1|Y2|Y41Ys Y1
[Y2IY4|
Y1|Y2|Y4|Y8
IIO PORT-1
-2 | -3 I -4
IF COUNTER DATA
Fo|F1|F21F3
IIOPORT-Z
—1 [ -2 | -3 I —4
IF COUNTER DATA
F4 F5 F6 F7
IIO PORT-3/DA REF. DATA
KEY INPUT
-1 —2 —3 —4
[ARC /AR1 IARZ IAR3 K0
IF COUNTER DATA
F8 1 F9 | F10 1 F11
|/O PORT-3
—1 -2 -3 -4
35 OUT
IF COUNTER DATA
F12 | F13 | F14 ] F15
DATA REGISTER
IN 0 0 0 d0
[d1ld2]
(yutlod .Lnle
DATA REGISTER
2H2 F/F 10H: 100Hz
F/F d4
[dslds]
IF COUNTER CONTROL
BUSY MANUAL OVFLW 0
DATA REGISTER
|d9]d1o|
U N LOCK PORT
|N1 1N2 ENABLE
UNLOCK
DATA REGISTER
d13 d14
SERIAL INPUT
CODE No. (C)
=0H~7H
HF IF OTFSE FM
IIO PORT-1
PORT-1 IIO CONTROL
54 [—21—3l-4 —1
I-Zl-3l
PROGRAMMABLE COUNTER
Po[P1|P2|P3
IIO PORT-Z
PORT-Z | IO CONTROL
5'3 -11-21—3l—4 —1
I-Zl-3
PROGRAMMABLE COUNTER
P4 P5 P6 P7
|/0 PORT-3/DA REF. DATA
PORT-3 IIO CONTROL
IDA REF. DATA
51 —1 —2 -3 -4 —1
IARO IAR1 IARZ IAR3 IAR4
/AR5 IAD SEL
PROGRAMMABLE COUNTER
P8 1 P9 | P10 | P11
PORT-4 | [O CONTROL
|lOPORT-4
5‘6 -1|—2[—3]-4 —1
PROGRAMMABLE COUNTER
in) 180d mamo
P12 | P13
G—REGISTER
52° #0 #1 #2
SIO ON SIO NCD
DISP OFF
REFERENCE PORT
2H2 F/F CLOCK
524 RESET RESET '
IF COUNTER CONTROL
STA IWIMANUAL
KEY TIMING PORT
OUTPUT PORT
‘28 [T1l‘r2]
T3 0T1 | 0T2 0T3
SERIAL INPUT
CODE No. (C)
= 8H~EH
IN CONTROL
IN“! I |N2
UNLOCK
KEY TIMING PORT
T4|T5|Ta]
T7 #1 | #2
CHIP SELECT
#o|#1|#2l#3
TC9309AF(E) - 25
TOSHIBA
TC9309AF
TOSHIBA TC9309AF
Ol/O map
All ports in the device are expressed by a matrix of 6 I/O instructions (PLL, SEG, MARK, IO, KEY
and SIO, instruction) with 4bit Code No. C. Allocation of these ports are shown above as the l/
0 Map. In this Map, port names treated in execution of HO instructions are assigned on the
axis of ordinates and port code numbers on the axis of abscissas. G-register and data register are
also treated as ports.
Basically, data of all ports are treated in unit of 4 bits, and Code No. (C)=0H--7H are
designated as the input ports and Code No. (C)=8H--FH as the output ports.
(Note 1) The oblique lined ports shown on the HO map are actually not existed in the device. If
data was output to an unexisted port when an output instruction was executed,
contents of other parts and the data memory are not especially affected.
If an unexisting input port was designated when executing an input instruction,
contents of data to be read in the data memory will become indefinite.
(Note 2) Ports with *mark out of output ports on the HO map are unused ports. Data being
output to these ports will become don't care.
(Note 3) Contents of ports expressed in 4 bits, that is, Y1 corresponds to LSB of data of the data
memory and Y8 corresponds to MSB. Data of all ports are treated in positive logic.
(Note 4) Ports that are designated by 6 I/O instructions and Code No. C are expressed by
encoding as shown below.
ff (K/L) m
Operand CN of I/O instruction
(A value of low order 3 bits of port Code No. : 0~7)
6 kinds of HO instructions are described in 1~6.
I/OINSTRUCTION PLL SEG MARK IO KEY SIO
m 1 2 3 4 5 6
Indicates l/O port (K : Input port, L : Output port)
C) Programmable counter
The programmable counter consists of 2-modulus prescaler, 4bit+ 12bit programmable binary
counter, and PLL I/O port group that controls these prescaler and counter.
Further, the programmable counter is turned ON/OFF according to contents of the reference
port, that is, when contents of the reference port (4 bits) are all "I", the programmable counter
is put in the PLL OFF Mode and otherwise, it is put in the PLL ON Mode.
26 2001-06-19
TOSHIBA TC9309AF
1. PLL l/O ports (pKL10--sbKL14)
These are exclusive ports for PLL to control all of frequency division number, frequency
division system, and IF correction (IF offset) at FM band, and are accessed by PLL output
instructions designated [CN=0--41 in the operand field (¢L10~¢L14).
1) Construction of PLL ports
¢L10 ¢L11 ¢L12 ffL13 ffL14
1 2 4 8 1 2 4 8 1 2 4 a 1 2 4 8 1 2 4 8
ttttttt
ttttttttttttt
ll llll llll llllllll
HF +1 -1 FM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
I LSB MSB
IF Offset
I I I I
Setting of frequency division Setting of 16 bits for Programmable Counter frequency division number
system
2) Setting of frequency division system
The pulse swallow system or the direct frequency division system are selected according to
HF and FM ports.
Select any of 4 systems available as shown in the following table according to frequency
band to be used.
EXAMPLE OF INPUT INPUT FREQUENCY
MODE HF FM FREQUENCY DIVISION SYSTEM RECEIVING FREQUENCY TERMINAL DIVISION
BAND RANGE NUMBER
LF 0 0 Direct frequency division system LW, MW, SWL thr- 20MHz AMIN n
HF 1 0 (K,-),)-, swallow system SWH l-- 40MHz AMIN n
FML o 1 (F/W)pulseswallowsystem FM 10--140MHz FMIN n
(1,-x,1-,,/,1-,,) le all
- - - us sw ow
FMH 1 1 2 15 16 p WB * 10~185MH2 FMIN Tn
system
* : Weather Band
(Note) n denotes a programmed divided frequency value.
3) IF correction function at FM band
When the pulse swallow system was selected, actual frequency division number is variable
of :1 without changing programmed frequency division value by A|Fi1 port.
This function can be used for IF offset at FM band.
And when the direct division system was selected, the IF offset function does not operate.
FREQUENCY DIVISION FREQUENCY DIVISION
A'F“ nlF-1 NUMBER (FMH) NUMBER (FML)
O 0 2-n n
0 1 2-(n - 1) n -1
1 O 2-(n + 1) n +1
1 1 2-(n - 1) n -1
27 2001-06-19
TOSHIBA TC9309AF
4) Setting of frequency division number
Set frequency division number of the program counter in binary number in P0--P15 ports.
It Pulse swallow system (16bit)
MSB LSB
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
215 20
* Frequency division number setting range (pulse swallow system)
n =210H--FFFFH (528--65535)
It Direct frequency division system (12bit)
MSB LSB
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
215 20 Y
Unconcerned
* Frequency division number setting range (Direct Frequency Division system)
n =10H~FFFH (16--4095)
(Note) Since no offset is provided to the program counter, a programmed division
number will become an actual division number. However, it will become 2 times
of a programmed value in case of FMH mode.
(Note) In case of the direct division system, data of P0~P3 ports (¢L11) become
unconcerned and P4 port becomes LSB.
(Note) All data of frequency division number are updated at the same time when MSB
port (¢L14) data are set. This is to prevent the Iock-up time from being adversely
affected by successive change of frequency division number. Therefore, MSB port
(¢L14) data must be set lastly when frequency division numbers are set. Further,
even if data set is considered unnecessary (if data is the same as the previous
data), it is necessary to execute data setting only for MSB port (¢L14).
2. Circuit configuration of prescaler and programmable counter
1) Circuit configuration in case of pulse swallow system
The circuit consists of 1/15/1/16 2-modulus prescaler, a 4bit swallow counter, and a 12bit
binary programmable counter. Further, in case of FM mode, 2 1/2 divider is added to the
front stage of the prescaler.
28 2001-06-19
TOSHIBA
TC9309AF
Swallow Counter
Preset
12bit To Phase
Programmable Counter Comparator
ai''''"'?
-12--j,s-s'sC:-,,iF /
P4-P15
2) Circuit configuration in case of direct frequency division system
In this case, a 12bit programmable counter is only used instead of the prescaler.
Preset
12bit Programmable Counter
P4-P15
- To Phase Comparator
(Note) Both the FMIN and AMIN terminals have built-in an amplifier respectively, and are
operable at small amplitude with coupled capacitors. Further, when the input
terminal not selected according to the frequency division system and the reference
port data (4 bits)are all "I", the inputs are pulled down.
C) Reference frequency divider
This frequency divider generates 10 kinds of PLL reference frequency signals 1, 3.125, 5, 6.25, 9,
10, 12.5, 25, 50, and 100kHz by dividing external 7.2MHz crystal oscillation frequency signals.
These frequency signals are selected according to the reference port data.
A selected signal is supplied as the reference frequency of the phase comparator described
below.
Further, according to the contents of the reference port, PLL ON/OFF is performed.
1. Reference port (¢L15)
This is the internal port to select 10 kinds of reference frequency signals. It is normally
accessed by PLL output instruction having [CN=5] designated in the operand. Further, when
the contents of the reference port are all "I", the programmable counter and the reference
counter stop and it becomes PLL OFF mode.
2001 -06-1 9
TOSHIBA TC9309AF
¢L15 Reference Frequency Table
Y1 Y2 Y4 Y8 REFERENCE
#0 #1 #2 #3 #3 #2 #1 #0 FREQUENCY
a—J 0 0 0 0 0 1kHz
Reference Frequency Select Code 0 0 0 1 1 50kHz
0 0 1 0 2 5kHz
0 0 1 1 3 100kHz
0 1 0 0 4 9kHz
0 1 0 1 5 10kHz
0 1 1 0 6 12.5kH2
0 1 1 1 7 25kHz
1 0 0 0 8 3.125kHz
1 0 0 1 9 6.25kHz
1 0 1 0 A
S S S S S Inhibit
1 1 1 0 E
1 1 1 1 F PLL OFF Mode
C) Phase comparator
The phase comparator compares phase difference between the reference frequency signal
supplied from the reference frequency divider and the programmable counter division output
and transmits their difference and then, controls VCO through a low-pass filter so that these
two signal frequencies and phases agree with each other.
As there are two parallel tri-state buffer terminals DOI and D02 for output from the phase
comparator, it is possible to design optimum filter constant for every FM/AM band.
Reference Frequency Signal
Programmable s Comparator
Counter Output
Standard
Vcc Tr1 : 25C1815
Tr2 : 2SK246
. Examples of Low-Pass
R -l I-] l_l l_l L ' RL T V _ Filter Constants
o arlcap
l l I I High level
(Reference Values at
Do - - - - s- JL - - - -
Diode of VCO FM band)
C--0.33ptF
Tr2 R1 =10kQ
R2 =8.2kQ
Floating , R3 =33OQ
Low level RL=10kQ
DO output Timing Chart Example of Active Low-Pass Filter Circuit
A DO output timing chart and an example of the active Iow-pass filter circuit through the
Darlington connection of FET and transistors are shown in the above diagram.
Further, the filter circuit shown in the above diagram is one example for reference and an
actual circuit shall be examined and designed according to the receiving band structure of a
system and desired characteristics.
30 2001-06-19
TOSHIBA TC9309AF
C) Unlock detecting bit (¢LK17)
This is a bit to detect the lock state of PLL system. In the unlocked state, that is, the state
where reference frequency is not in accord with the programmable counter division output,
(phase error) pulses are output to the unlock F/F at reference frequency cycle from the phase
comparator. The unlock F/F is set by these phase pulses. Further, whenever the unlock reset bit
is set to "1" by the PLL output instruction designated [CN=7] in the operand, the unlock F/F is
reset (¢L17).
After resetting the unlock F/F, the lock state can be detected by accessing the unlock detecting
bit by the PLL input instruction designated [CN=7] in the operand (¢L17).
Since pulses are input at reference frequency cycle, it is necessary to access the unlock detecting
bit with providing a time more than reference frequency cycle after resetting the unlock F/F.
If this time was short, the proper lock state cannot be detected.
Therefore, the test enable F/F is provided. This test enable F/F is reset whenever is set for
the unlock reset bit and is set to "1" at the unlock detection timing. That is, the unlock state
can be properly detected only when this test enable bit (¢K17) is set at "I".
Reference frequency f L
Programmable counter output
DO output I I
Phase error
Lock detecting strobe t,
Execution of unlock reset -e / /' / /2
Unlock detecting bit ( "tiff \<)
Test enable bit I I J
-———--———-e>
31 2001-06-19
TOSHIBA TC9309AF
Y1 Y2 Y4 Y8
ffL17 Unlock Reset
_ I Whenever data "I" is set, the unlock detection F/F and the test
I enable F/F are reset.
¢K17 Test Enable Unlock Detect
Test Enable - Unlock Detection
1 : PLL unlock detectable 1 : PLL unlock state detected
0 .' PLL unlock detection waiting state 0 .' PLL normally operating (Unlock not detected)
C) General purpose IF counter
This is a 16bit general purpose IF counter that is used to count FM or AM intermediate
frequency (IF) and is usable for detection of auto stop signal, etc.
The IF counter consists of a 16bit binary counter and IF counter control ports.
1. IF counter data ports (¢K11~¢K14, ¢K16)
These are the data input ports for reading count data and operating state of the IF counter.
Data are read in the data memory by the PLL input instruction designated [CN--r-51 in the
operand.
¢K11 ¢K12 ¢K13 ¢K14
Y1 Y2 Y4 Y8 - - -
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
LSB IF Counter Data Input
Date counted by the IF counter can be input in binary number through the input ports
F0--F15.
32 2001-06-19
TOSHIBA TC9309AF
Y1 Y2 Y4 Y8
BUSY MANUAL OVFLOW 0
L Overflow Detection
0: IF Counter countsit16-1
1 : IF Counter count:ir216-1 (Overflow state)
Operation Mode
0 , IF Counter Auto Mode
1 : IF Counter Manual Mode
Operation Monitor t , IF Counter Count End
1 : IF Counter Under Counting
This is an input port (¢K16) to detect the operating state of the IF Counter. When using the
IF counter, count data (FO--FI5) shall be processed after confirming that BUSY bit is "0"
(Count end) and OVFLOW bit is "0" (no overflow).
2. IF counter control ports (¢L16, ¢L17)
These are ports to output data for control of IF counter operation, and are accessible by the
PLL output instruction designated [CN =6 or 7] in the operand.
Y1 Y2 Y4 Y8
STA/ste MANUAL #0 #1
f] IF counter gate time selecting bit
#0 #1 Gate Time ( ms] (Note) . .
Gate time at time of
0 0 1 (1.111) 9kHz reference signal
1 0 4 (4.444) are shown in ( ).
o 1 8 (8.888) That is, if reference
1 1 16 (17.77) 9kHz was selected, the
gate time will become
10/9 times.
IF counter auto/manual mode selection
1 : Manual Mode
0 : Auto Mode
IF counter auto/manual mode control
1 : Count start
0 .' Count stop
In the auto mode (MANUAL bit is set to "o"), IF count starts whenever STA/W bit set to
"1". IF count ends automatically after passing a gate time selected by #0 or #1 bit. Further,
in the manual mode, when STA/W is set to "1", IF count starts and continues till STA/STP
bit is set to "0".
33 2001-06-19
TOSHIBA TC9309AF
Y2 Y4 Y8
(Note)
IF input selection control bit
INZ fl _
1 : IFIN1 input
u-v---" 0 : IFINZ input
IN control bit
1 : IN input setting
0 : IF input setting
Input ports and IF input are selectable in 1bit unit.
In case that IF counter is used, IN control bit that corresponds to an input terminal to be
used shall be set to "o" and IF input selection control bit shall be designated.
(Note)
(Note)
In the PLL OFF mode, IF counter is reset by force and IF counter input is pulled
down. Further, the input that is not selected by IF input selection control bit(IF 1bit)
at the IF counter is pulled down.
After system reset, IN control bit is set to "0" and IF input selection control bit is
set to "1".
3. IF counter circuit configuration
The IF counter consists of input amplifiers, gate time control circuit, and 16bit binary counter.
(Note)
F0--F15 OVFLOW
fl ("s, t
bi . Overflow
16 It Binary Counter Detection
Gate Time Control Circuit
Gate Signal l 1 l I
START MANUAL BUSY MANUAL
IFIN terminals have built-in amplifiers and are capable of operating at small
amplitude with coupled capacitors.
34 2001-06-19
TOSHIBA TC9309AF
C) LCD driver
The TC9309AF has a built-in 1/2 duty and 1/2 bias drive (frame frequency=100Hz) LCD driver.
Two common outputs (COM1, COM2) output 3 potential of VDD, 1/2 VDD and GND with 1/4
phase difference. It is possible to display 64 segments of LCD by a combination of these common
outputs and 32 segment outputs ($1~S32). That is, this LCD driver is of dynamic type that
displays 2 system segments, COM1 system segment and COM2 system segment by one segment
output.
The LCD driver has no built-in segment decoder and 64 segments are freely usable for 7-segment
display as well as mark segment display programmatically.
COM1 system segment outputs and COM2 system segment outputs are controlled through
execution of SEG instruction and MARK instruction, respectively.
1. LCD driver timing chart
F''"-'''"-!
------------- VDD
COM1 I ----- 1/2 VDD
l ---------- VDD
I I LCD Segment
COM2 I /_/H
l COM1 COM2
System System
I I I I I l OFF OFF
Segment Output
l I l I I I l OFF ON
fLrififl-
ON OFF
(Note) During system reset and clock stop mode (When executing CKSTP instruction),
common outputs and segment outputs are all fixed at "L" level automatically.
2. COM1 system segment ports (iL20-iL27)
This is a group of ports to output 32 segment data of COM1 system. These ports are accessed
by SEG output instruction. Segment data are treated in a unit of 4 bits.
When data "I" is output, COM1 system segments are turned "ON" and when data "o" is
output, they are turned "OFF".
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
1234 5678 91011121314151617181920 21222324 25262728 29303132
¢L20 ¢L21 ¢L22 fL23 ¢L24 ¢L25 ¢L26 ¢L27
35 2001-06-19
TOSHIBA TC9309AF
3. COM2 system segment ports (PL3tr-PL37)
This is a group of ports to output 32 segment data of COM2 system. These ports are accessed
by MARK output instruction. Segment data are treated in a unit of 4 bits.
When data "1" is output, COM2 system segments are turned "ON" and when data "o" is
output, they are turned "OFF".
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
1234 5678 91011121314151617181920 21222324 25262728 29303132
¢L3o ¢L31 ffL32 ¢L33 ffL34 ¢L35 ¢L36 ¢L37
o DISP OFF BIT (¢L54)
This bit controls ON/OFF of the LCD display. When data "I" is set in this bit, common
outputs and segment outputs are all fixed at "L" level and all displays are turned off.
When data "o" is set in this bit, normal display operation is performed.
Further, after system reset, this bit is reset to "O".
Y1 Y2 Y4 Y8
1 : ALL LCD displays are turned off.
0 : Normal LCD display
(Note) Names of COM1 system and COM2 system ports correspond to names of the
segment output terminals, respectively. Further, since contents of all ports are
not affected by DISP OFF bit, data can be output as usual even when LCD
displays are kept turning off by DISP OFF bit.
(Note) Segment decode can be executed by that a segment decode pattern of that
segment is provided in the program memory and read into the data memory
by using DAL instruction. Therefore, the LCD driver has no built in segment
detector.
As DAL instruction refers to data stored in the program memory in a unit of
16 bits, the segment ports for 7-segment displays are successively allocated in a
unit of 8 bits (7 segments+1 mark) like Port sr-sl sr-s8 ...... ' commonly for
COM1 and COM2 systems.
36 2001-06-19
TOSHIBA TC9309AF
C) HO ports
HO ports -1, -2, -3 and -4
I/O Ports -1, -2 and -4 are 4bit ports where input/output are selectable in a unit of each bit
and HG Port-3 is 3bit port where input/output are selectable in a unit of each bit. Input/
output are set in I/O ports according to the contents of I/O control inner port. To set input
in I/O port, set "0" in l/O control port bit corresponding to that l/O port and to set output
in I/O port, set "1".
In case of setting input port, data that have been currently input to I/O ports are read in
the data memory when IO input instructions corresponding to respective l/O ports are
executed. At this time, the contents of the output side latch gives no effect on input data.
In case of setting output port, the HO port output state is controlled by executing IO output
instructions corresponding to respective I/O ports. Further, the contents of data currently
being output are read in the data memory when IO input instruction is executed.
Further, l/O Port-3 is also used as the analog input/output of 6bit A/D and D/A converters,
and HG Port-2 is also used as the serial interface. Therefore, when l/O Port-2 and -3 are
used, the contents of A/D ON bit and SIO ON bit should be set to "o".
(Refer to items of A/D and D/A Converters and Serial Interface.)
(Note) Output side latch P3-4 data are input from Input Port P3-4.
(Note) Output side latch P3-4 data are normally unconcerned, and when A/D converter is
in operation it becomes effective. Further, after system reset, the contents of AD ON
bit and SIO ON bit are reset to "o", and D/A converter and serial interface terminal
becomes l/O port.
(Note) After system reset, the contents of I/O control ports are all reset to "0" and all l/O
ports are set in the input mode.
(Note) During the clock stop mode, the output state of all l/O ports that have been set in
the output mode is automatically fixed at "L" level but the contents of all output
latches are kept at the preceding data.
37 2001-06-19
TOSHIBA
TC9309AF
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
Pl-l P1-2 P1-3 P1-4
KL40 P1-1 P1-2 P1-3 P1-4 L50
, ff IIO I/O IIO IIO
*r—’ *r—’
l/O Port-1 IIO Port-1 IIO Setting
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2
P2-1 P2-2 P2-3 P2-4 IO IO
¢KL41 P2-1 P2-2 P2-3 P2-4 ¢L51 ¢L54 S S
IIO IIO l/O IIO ON NCD
—V—) I-v---"
l/O Port-2 IIO Port-2 l/O Setting - Serial Interface
f I Selecting Bit "o'"
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
P3-1 P3-2 P3-3 AD
¢KL42 P3-1 P3-2 P3-3 P3-4 ¢L52
HO HO HO ON
l/O P rt-3 -
o l/O pry - A/D, D/A Converter
l/O Setting Selecting Bit "0"
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
P4-1 P4-2 P4-3 P4-4
¢KL43 P4-1 P4-2 P4-3 P4-4 sbL53
IIO I/O IIO IIO
IIO Port-4
I/O Port-4 I/O Setting
2001 -06-1 9
TOSHIBA TC9309AF
2. Key timing output (T0~T7), general purpose output ports (OT1--OT4)
T0~T7 are CMOS 8bit output and OT1~OT4 are CMOS 4bit output ports. Normally TO-T? are
used for output of key return timing signal of the key matrix and OT1~OT4 are used for
control of mute signal, linear circuit, etc.
T0~T7 are accessed by the IO output instruction designated [CN=6 or 7] in the operand, and
OT1~OT4 are accessed by the KEY output instruction designated [CN =6] in the operand.
(¢L46 or ¢L47 or ¢L56)
(Note) During the clock stop mode, T0~T7 and OT1~OT4 outputs are automatically fixed at
"L" level but the contents of the ports are kept at the preceding data.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L46 T0 T1 T2 T3 ¢L47 T4 T5 T6 T7 ffL56 0T1 0T2 0T3 0T4
3. General purpose input ports (IN1, IN2)
lbl1 and Ihl2 are CMOS 2bit input ports. These ports are also used as the IF counter input and
they are selected according to the contents of IN control port.
(Refer to Item of General Purpose IF Counter.)
In case of setting the input ports, IN control port bit shall be set to "1" by the PLL output
instruction designated [CN=7] in the operand and data of the input terminals are read in the
data memory by executing the PLL input instruction designated [CN=7] in the operand.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
IN1 IN2
9517 INI IN2 Control Control
\ l V v J
IN Port Set "I" to IN port and IF counter input selecting bit.
(Note) When IF counter is used, the contents of IN Port becomes "o".
(Note) After system reset, the contents of IN control port are reset to "o".
4. Key input ports (K0--K3)
K0~K3 are the 4bit exclusive key input terminals for key matrix input. Each of these 4
terminals has a built-in pull-down resistor.
Data is read in the data memory from the key input terminal when the key input instruction
designated [CN=2] in the operand is executed.
Y1 Y2 Y4 Y8
¢K52 K0 K1 K2 K3
39 2001-06-19
TOSHIBA TC9309AF
C) Register ports
G-Register and Data Registers described in the explanation of CPU are also treated as the inner
ports.
G-Register (sl L44)
This is a register for addressing row addresses (DR=4H--FH) of the data memory when MVGD
/MVGS instruction are executed. This register is accessed by IO output instruction designated
[CN=4] in the operand.
(Note) The contents of this register becomes valid only when MVGD/MVGS instruction are
executed, and are not concerned with other instructions.
Y1 Y2 Y4 Y8
¢L44 M) #1 #2 #3 #3 #2 #1 #0 DR
Row address of the data memory 0 1 0 0 4H
is designated. 0 1 0 1 5H
0 1 1 0 6H
1 l l S l
1 1 1 0 EH
1 1 1 1 FH
(Note) All row address of the data memory also can be designated indirectly by
setting data 0H~FH in the G-register. (DR--0H-FH)
. Data register (ssk54--pK57)
This register is a 16bit register into which the program memory data are loaded.
The contents of this register are read in the data memory in a unit of 4 bits when KEY input
instruction designated [CN--4-7] in the operand are executed.
This register can be used for LCD segment decoding operation and taking radio band edge
data, coefficient data of Binary to BCD conversion, etc.
Y8 Y4 Y2 Y1 -
d d d d d d d d d d d d d d d d
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ffK57 ¢K56 ¢K55 ¢K54
MSB Program Memory 16bit Data LSB
40 2001-06-19
TOSHIBA TC9309AF
C) Internal control ports
The internal control ports are used for reading the internal state of a device into the data
memory, that is needed to know for program execution, and for resetting the internal state of a
device.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
- 2Hz Wait
¢K44 l H o o o ¢K45 F/F 10Hz 100Hz F/F
Timer Interval Wait
F/F Pulse Output F/F
Y1 Y2 Y4 Y8
’23: CLOCK * '
f RESET RESET
1. TNIT-T input port (¢K44)
This is a single bit input port for input the TFIT-f terminal data. The contents of this port are
read in the data memory by executing IO input instruction designated [CN=4] in the
operand. When CKSTP instruction is executed during "L" level being applied to this terminal,
the device is put in the clock stop mode.
(Note) In executing the CKSTP instruction, make sure that the contents of the W input
port is "0" and set the PLL OFF mode (set the contents of the reference port to all
"1".) before executing the CKSTP instruction.
2. 2Hz timer F/F (¢K45)
The 2Hz timer F/F is set by 2Hz (500ms) signal, and is reset when data "1" is set to 2H2 F/F
RESET bit by executing the IO output instruction designated [CN=5] in the operand. This F/F
output is read in the data memory when the IO input instruction designated [CN=5] in the
operand is executed.
Since the 2H2 timer F/F is automatically set at intervals of 500ms, it can be used for ordinary
clock count.
The 2H2 timer F/F can be reset only by 2Hz F/F RESET bit, therefore, if data "1" can not be
set to the 2H2 RESET bit within the 500ms period, a count error is caused and a correct time
may not be obtained.
(Note) When the power source is applied or after the CKSTP instruction was executed, the
state of 2H2 timer F/F output becomes uncertain.
2Hz Timer F/F Output
_-o t<500ms
(, I *1 Set
500ms I *2 Reset
(2Hz F/F RESET
bit is set to "I'')
2Hz clock
41 2001-06-19
TOSHIBA TC9309AF
10Hz/100Hz interval pulses (¢K45)
10Hz interval pulse is a 100ms period, 50% duty pulse, and 100Hz interval pulse is a 10ms
period, 50% duty pulse and both are output to 10Hz and 100Hz bits. These pulses are read
in the data memory when the IO input instruction designated [CN=5] in the operand is
executed. These outputs have no flip-flop and are available for counting of muting time, and
scanning time of tuning, etc.
#3223312? L l_l |_l |_l l-
Jo-mil
100Hz Interval
Pulse Output _l |_l |_l |_l L.
CLOCK RESET bit (¢L45)
Whenever data "1" is set to this bit, time base below 50Hz is reset. (10Hz interval pulse is
also reset but 100Hz interval pulse is not reset.)
This bit is used for adjustment of clock time. Accuracy of clock at the time is +0.02/ -0s.
. Wait F/F bit (¢K45)
IF the power supply voltage at the VDD terminal dropped below 2.5-3.5V during CPU
operation, CPU comes to halt to prevent its malfunction at a timing when voltage drops
below 2.5~3.5V (Wait Mode).
The Wait F/F is set under this state, and when voltage at the VDD terminal rises above 3.5V,
CPU restarts to run.
Therefore, if Wait F/F bit data was read in the data memory by executing the KEY input
instruction designated [CN=5] in the operand and Wait F/F bit was set to "I'', the
initialization, clock correction, etc. shall be performed when necessary.
Wait F/F bit is also reset when "1" is set to 2Hz F/F RESET bit.
CPU Operation CPU Halt CPU Operation
l (Wa it Mode)
2Hz F/F RESET ------
bit is set to "1" I 7 2
Wait F/F l 'si
(Note) In the Wait mode, the inner data just before the Wait Mode are retained and no
instruction can be executed.
42 2001-06-19
TOSHIBA TC9309AF
6. TEST port (¢L57)
This TEST Port is an internal port for testing function of device. This port is accessed by
executing the KEY output instruction designated [CN=7] in the operand. In case of ordinary
Program, data "o" shall be always set.
Y1 Y2 Y4 Y8
¢L57 #1 #2 * *
; Always set data "0"
C) A/D and D/A converters
The TC9309AF has built-in programmatic sequential comparison type 6bit A/D and D/A
converters. 3 I/O port terminals are used for the A/D and D/A converters, which are selected
by AD ON bit.
When data "1" is set to AD ON bit, P3-1 is switched to the reference voltage input (DC-REF), P3-
2 to the analog voltage input (ADIN1), and P3-3 to the analog voltage input/output (ADINZ/
DAOUT).
In this case, 4 bits of I/O port-3 output side latch, (¢L42) and 3 bits of I/O Control Port-3
output side latch (¢L52) become A/D and D/A converter control data ports.
The A/D, D/A converter consists of 2 6bit D/A converter, comparator, operational amplifier,
and control circuit.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
" ¢KL42 (P3-1) (P3-2) (P3-3) (P3-4) ¢L52 5333 )l(et ) 7/363 ) AD
ARO ARI AR2 AR3 Am AR5 ADSEL ON
LSB MSB
DC-REF _
(1.5V-VDD) <53) . 6bit D/A , ( 1 : AID, D/A Converter Setting
0 : I/O Port-3 Setting
- Reference Voltage
ADim (sb-rs b1> La
Comparator Y1 Y2 Y4 Y8
OP Amp -
UF- A/D
ADINZ/DAOUT (ii "ii"''-'"'-"::':??-] ff 5 OUT 0 0 0
,, AD ON
Construction of A/D, D/A Converters
(Note) After system reset, AD ON bit, DA ON bit, ADSEL bit, AR5 bit are all reset to "o".
(Note) The 6bit D/A circuit for generating reference voltage is commonly used for the A/D
converter and D/A converter.
43 2001-06-19
TOSHIBA TC9309AF
1. A/D converter
The A/D converter is of 2 channel multiplex type and can be used for field strength
measurement, analog voltage level detection, etc.
When ARO--AR3 bits data (¢L42) are set after setting of AD ON bit, ADSEL bit, and AR4/AR5
bits (¢L52) data, comparison voltage corresponding to ARO--AR5 data is compared with input
voltage (AD input) in the A/D converter, and the result of this comparison is stored in the
comparator output latch.
This comparison result is output to the AD-OUT Port (¢K53), and this data is read in the data
memory when the KEY input instruction designated [CN=3] in the operand is executed.
The relation between input voltage and comparison voltage, and the result of comparison to
be output is as follows:
W=”O" when input voltage>comparison voltage
W="1" when input voltageFurther, comparison voltage is caluculated according to the following equation ,
. n-0.5 n is ARO--AR5 data value [decimal number]
Comparison Voltage =VREF x -
64 63gng1
AD input of ADIN1 or ADINZ is selected according to the contents of ADSEL bit.
That is, ADINZ input is selected when ADSEL bit is "o'' and ADIN1 input is selected when
ADSEL bit is "I".
1/2R R R R R
J, AVAVA' AM AAA I - T"--""''-
3 ......... 61 62 63
AMP-AM I )
Selector "
Com parison
Voltage
La AD OUT
3/2R DC-REF
(VREF)
AD Input -
Co m pa rator
Construction of A/D Converter
(Note) Whenever ARO--AR3 data are
AD SEL
AD INPUT
Invalid
(Note)
(Note)
set, comparison carried out.
(Note) .)K. : don't care.
In case of A/D converter used, DA ON bit shall be set to "O".
Even if DA ON bit is set to "I" and the comparing operation is carried out
(data is set to ARO--AR3 bit), the contents of AD-OUT become indefinite.
String resistor of A/D converter is set at values lower by 1/2 LSB.
2001 -06-1 9
TOSHIBA TC9309AF
2. D/A converter
The D/A converter is available for control of electronic volume which is controlled by analog
voltage, etc.
In case of D/A converter used, when "I" is set to both AD ON bit and DA ON bit, D/A
output corresponding to ARO--AR5 data is output from the DA output terminal.
When ARO-AR5 data is changed successively, output ripple is generated at time of carry to
AR4 because I/O memory layout differs between ARO--AR3 data and AR4--AR5 data.
Therefore, at time of carry to AR4, the carry shall be performed after making output to high
impedance by setting DA ON bit to "o". In this case, a voltage holding capacitor is connected
to the output because of being high impedance.
Further, D/A output voltage is calculated according to the following equation:
D/A output voltage=VREFx H (n is ARO--AR5 data [decimal number] 632n2 1)
When the A/D converter and the D/A converter are simultaneously used, perform A/D
conversion with D/A ON bit set at "o" and thereafter, output D/A analog voltage by setting
DA ON bit at "1".
R R R R R DC-REF
'N. IAA - , W__.M_
J, l (VREF)
ARO--AR5
Selector
Reference voltage
DA OUT 51 "iso-a
u, _ AD ON bit=1
D/A converter operates when '
DA ON bit=I
.- AD ON
Construction of D/A Converter
(Note) Add an external buffer circuit to the D/A output if necessary, although it
has a built-in buffer.
(Note) D/Aoutput range is 0V~VDD- 1.0V and so, be careful when VREF=VDD.
(Note) DA ON bit becomes invalid when AD ON bit is "O".
(Note) Voltage value of string resistor of D/A converter is a 64 divided VREF value.
45 2001-06-19
TOSHIBA TC9309AF
C) Serial interface
l/O Port-2 can be programmatically switched to the serial interface. The serial interface is a
serial l/O dedicated for powerful control of a group of peripheral optional ICs.
When switched to the serial interface, 4 terminals of HO port-il are switched to SI, SO, CK and
STB terminals. These terminals are connected to external device with 4 serial bus lines for data
transfer.
By connecting peripheral optional ICs on these bus lines according to system, functions can be
expanded.
Various external devices such as l/O port extension IC, static display driver, etc. are available.
Serial data transfer is carried out by executing the SIO instruction and during this instruction
execution time (55.5ps), all data transfer is completed.
It is possible to handle all ports of external devices simply as inner ports that are handled
through execution of other l/O instructions. Further, two kinds of serial transfer are
programmatically selectable.
1. Serial transfer control port (¢KL53)
l/O Port-2 and the serial interface are selected and controlled by the KEY output instruction
designated [CN=4] in the operand (¢L54).
When SIO ON bit is set to "o", HO port-2 is selected and when "1" is set, the serial interface
is selected. Further, two kinds of the serial transfer formats are selectable by SIO NCD bit.
When SIC) NCD bit is set to "O", Nt-yy mode serial transfer format is selected.
In the N-CIT Mode, Port Code No. designated in the operand of SIO is serially transferred
together with data. When "I" is set, the NCD Mode results. In the NCD mode, Code No. is
not transferred and data only are exchanged. (CN value in the operand of SIO instruction
become don't care.)
Y1 Y2 Y4 Y8
SIO SIO
¢L54 ON NCD
t, Serial Transfer Format Designation
<1 : NCD Mode
0 : W Mode
I/O Port-2 and Serial Interface Selection
( 1 : Serial Interface Function Selection
0 : I/O port-2 Selection
(Note) All serial transfers to external devices described in the following table are carried
out in the WD mode.
(Note) In the serial transfer in the NCD mode, designation of chip select code has no
meaning. That is, designation of transfer is not selectable.
(Note) After system reset, the contents of SIO ON bit and SIO NCD bit are automatically
cleared to "O". (HO Port-2 has been selected.)
46 2001-06-19
TOSHIBA TC9309AF
Serial Interface E. , Serial Bus Line(SO/Sl/CK/STB) _
DTS Controller , / 1 . d f .
I /O STATIC
TC9309AF DRIVER
TC9173P, TC9173F TC9175N
TC9174P, TC9174F TC9180N
2. Chip select
As shown in the above diagram, it is possible to freely connect many external devices to the
serial bus lines. It is therefore necessary to first select a destination device for serial transfer.
Each of external devices on the serial bus lines is allocated with a destination address
expressed by 4bit data, that is called chip select code. When this chip select code is
designated, data is exchanged with an external device corresponding to that Code No.
The chip select port (¢L67) is an internal port for designating this chip select code and is
accessed by the SIO output instruction designated [CN=7] in the operand. Maximum 16
external devices are selectable with the 4bit chip select code. (Actually, there are some
devices each of which may have more than two (2) Chip Select Code No. For example;
TC9227P has 2 Chip Select Code No. and TC9189F has 3 Chip Select Code No.)
Y1 Y2 Y4 Y8 External Device's Chip Select Code Table
ffl-67 #0 #1 #2 #3 CHIP SELECT CODE No. EXTERNAL DEVICE
PRODUCT
x v J #3 #2 #1 #0 NAME
0 0 O 0 0 - -
Chip Select Code of
Serial Transferring Device 0 0 0 1 1 TC9172AP
0 0 1 0 2 TC9227P/ PLL .y.4
0 0 1 1 3 TC9173P/F For I/O port expansion
0 1 o o 4 TC9174P/F For out.put port
expansion
0 0 5 TC9175N VFL static display driver
0 1 1 0 6
0 1 1 1 7 General purpose static
1 0 0 0 8 C9 80 display driver (LED/LCD)
1 0 0 1 9 TC9189F Dynamic display driver
1 O 1 0 A TC9190N )K (LED/VFL/LCD)
1 0 1 1 B TC9191P
1 1 0 0 C - -
"-..--, _---"--" ----,-..-.,..-----""''""-"""'"-
(Note) Chip Select Code No. of products with X mark are
the same.
47 2001-06-19
TOSHIBA TC9309AF
(Note) In executing the SIG instruction, first of all, Chip Select Code for a device of
transfer destination should be designated by the SIG output instruction. As the
Chip select Code No. which is set once remains unchanged unless another Code
No. is designated, it is not necessary to designate Chip Select Code whenever
executing the SIG instruction.
(Note) It is not possible to connect devices having the same chip select code to the
serial bus line simultaneously.
(Note) After designating Chip Select Code No., data is output to the port of the
external device corresponding to chip Select Code No. designated in the
instruction's operand by execution of the SIG output instruction, and the contents
of the port of the external device are read in the data memory by execution of
the SIG input instruction.
(Note) It is inhibited to proqram the SIG input instruction as an instruction to be
executed next to the SIO output instruction.
When the SIG input instruction programmed execution following the SIO output
instruction, the NOOP instruction or the instruction should be inserted between
3. Serial I/O timing chart
0 NCD mode output timing
"fflflf_Lrlflflfl,
wiczxm i )(Y2)(v4 r'')
53, 3/15
Code No. of External Device Port Output Data
At the timing shown in the above chart, Code No. (Cr-C8 : 4 bits) of the output port of
destination device to which data is sent and data (Y1~Y8 : 4 bits) are output serially from
LSB synchronizing with the fall timing of CK signal.
(Note) When excuting the SIG output instruction (NCD Mode), C8 bit of Code No.
becomes"I".
o NCD mode output timing
so Y1 Y2 Y4 Y8
Serial output in the NCD Mode will be 4bit data only. Further, STB output is always fixed
at "L" level.
48 2001-06-19
TOSHIBA TC9309AF
0 NCD mode input timing
"fflffl, ffff,
so I CI C2 c4 c8: "0"
Code No. of External Device Port
Y1 Y2 Y4 Y8 (
Input Data
When Code No. (cr-ce : 4 bits) of the input port of destination device is output from
the SO terminal at the timing shown in the above timing chart, the contents (Y1~Y8 : 4
bits) of that input port are serially input into the SI terminal from LSB. SO data is output
synchronizing with the fall timing of CK signal and similarly, SI data is input synchronizing
with the fall timing of CK signal.
(Note) When executing the SIG input instruction (NCD Mode), Cg bit Code No.
becomes "O".
O NCD mode input timing
SI don't care I Y1 X Y2 I Y4 I Y8
At time of serial input in the NCD Mode, STB output and so output are always fixed at
"L" level. SI data is input synchronizing with the all timing of CK signal.
4. Serial timing pulse width
Pulse width of each timing signal is shown below.
2.2/15
-1 Typ.
CK CK 2.2ps CK
Typ. 1.0ps Max. 1.0ps Min.
49 2001-06-19
TOSHIBA
TC9309AF
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage VDD -0.r-7.0 V
Input Voltage VIN - 0.3--VDD + 0.3 V
Power Dissipation PD 400 mW
Operating Temperature Topr -40-85 "C
Storage Temperature Tstg - 65~150 "C
ELECTRICAL CHARACTERISTICS (Unless otherwise
specified, Ta= -40~85°C, VDD=4.5~5.5V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
CPU operation/PLL stop
Operating Power Supply .
Voltage Range VDD1 - PLL Stop/CPU operation 3.5 5.0 5.5 V
Memory Holding Voltage VHD - Cristal oscillation stop 2.0 ._ 5.5 V
Operating Power Supply PLL Stop/CPU operation
Current IDD1 - VDD = 5v, Ta = 25°C - 0.7 1.5 mA
. IHD1 - VDD=5V. . - 0.1 10
Memory Holding Power Cristal oscillation stop
Supply Current I VDD = 2V 5
HD2 - Cristal oscillation stop - -
Crystal Oscillation Frequency fXT - - - 7.2 - MHz
CPU/PLL operation
Operating Power Supply .
Voltage Range VDD2 - CPU/PLL operation 4.5 5.0 5.5 V
. CPU/PLL operation
2,e,2tting Power Supply IDD2 - (FM|N= 140MHz) - 10 25 mA
VDD = 5V, Ta = 25°C
PLL operating frequency range
FMIN (FMH Mode) fFMH - V|N=0.5Vp-p 10 _ 185 MHz
FMIN (FML Mode) fFML - V|N=O.3Vp_p 10 -- 140 MHz
AMIN (HF Mode) fHF - V|N=O.3Vp_p 1 -- 40 MHz
AMIN (LF Mode) fLF - V|N=0.3Vp_p 0.5 ' 20 MHz
IFIN1 fiFI - VIN = 0.3Vp-p 0.1 '"- 20 MHz
IFINZ fiF2 - VIN = 0.3Vp-p 0.1 _ 20 MHz
50 2001-06-19
TOSHIBA TC9309AF
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
PLL operating input amplitude range
FMIN (FMH Mode) VIN (FMH) - fIN =10-185MHz 0.5 ''%.. VDD - 0.5 Vp-p
FMIN (FML Mode) VIN (FML) - 'le =10--140MHz 0.3 -- VDD - 0.5 Vp-p
AMIN (HF Mode) VIN (HF) - fIN =1~40MH2 0.3 '"- VDD - 0.5 Vp-p
AMIN (LF Mode) VIN (LF) - fIN = 0.5~20MHZ 0.3 -- VDD - 0.5 Vp-p
IFIN1 VIN (IFIN1) - fIN =0.1--20MHz 0.3 -- VDD -0.5 vp.p
IFINZ VIN(IFINZ) - hN=0.1--20MHz 0.3 -- VDD-OS Vp-p
LCD common output (COM1, COM2)
Output " H" Level 'OH1 - VOH = 4.5V, VDD = 5V - 350 - 900 - A
Current " L" Level Korn - VOH = 0.5V, VDD = 5V 350 900 - [J
1/2 Bias Voltage v35 - VDD=5V, No Load 2.30 2.50 2.70 v
LCD segment output (S1--S32)
Output " H" Level IOH2 - VOH = 4.5V, VDD = 5V - 50 - 450 - A
Current "L" Level IOLZ - VOL=0.5V, VDD = 5V 50 450 - #
P1-1~P1-4, P2-1--P2-4 (SO, CK, STB), P3-1--P3-3, P4-1--P4-4, T0~T5, OTI--OT4 output port
Output "H" Level loH3 - VOH =4.5V, VDD = 5V - 1.0 - 3.0 - mA
Current "L" Level IOL? - VOL=0.5V, VDD-- 5V 1.0 3.0 -
W input port
"flrslTif Input "H" Level VIH2 - - VDDx0.85 '''- VDD V
Voltage "L" Level VIL2 - - 0 ' VDDx0.5
Input Leak "H" Level IIHI - V|H=VDD=5-5V - - 2 A
Current "L" Level IIL1 - lhL=0V, VDD = 5.5V - - 2 /2
Key input port (K0~K3)
Input "H" Level VIH1 - - VDD x0.7 -- VDD V
Voltage "L" Level VIL1 - - 0 - VDDx0.3
Pull-down Resistance R - VIH = VDD = SV, 50 100 150 km
IN1 Ta = 25°C
51 2001-06-19
TOSHIBA TC9309AF
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
FIT, IN1, lN2, P1-1~P1-4, P2-1-P2-4 (SI), P3-1-P3-3, P4-1-P4-4 port
Input "H" Level 1/IH1 - - VDD x0.7 _ VDD V
Voltage "L" Level V|L1 - - 0 -... VDDXO.3
Input Leak "H" Level 'IH1 - VIH =VDD= 5.5V - - 2 A
Current "L" Level lIL1 - lhL=0V, VDD = 5.5V - - 2 ”
DOI, D02 outputs
Output "H" Level loH4 - VOH = 4.5V, VDD = 5V - 1.0 - 3.0 - mA
Current "L" Level IOL4 - V0L=0.5V, VDD-- 5V 1.0 3.0 -
. VTLH = VDD = 5.5V,
- L k I - - - AI A
Tri State ea Current TL VTLL=0V ,u
A/D, D/A converter (DC'REF, A/DIN1, A/DIN2, D/AOUT)
Analogue Input Voltage
V - AD AD ._.. V V
Range AD1 INI, IN2 0 DD
Analogue Reference
- D .REF 1. -- V V
Voltage Range VREF C 5 DD
Resolution VRES - - - - 6 bit
Analogue Reference DC-REF, Ta = 25°C
- - . 1. A
Voltage Input Current IREF VIH =VDD = 5V 0 5 0 m
Analogue Output
- DA -%.. V - 1. V
Voltage Range VDAO OUT 0 DD 0
Analogue Output IDA-- i100/1A, + +
- - - - 1 V
Voltage Deviation AVDA VDD = 5V, Ta = 25°C 50 50 m
Conversion Total Error - - - - $0.5 $1.5 LSB
FMIN, AMIN, IFIN Input
. - = ' = o 2 1 kn
Feedback Resistance Rfl VDD 5V Ta 25 C 50 500 000
XT .lnpUt Feedback Rf2 - VDD = 5v, Ta = 25°C 500 1000 1750 kn
Resistance
TEST Input Pull-down VIH =VDD = 5V,
Resistance RIN2 Ta = 25°C 15 30 60
52 2001-06-19
TOSHIBA TC9309AF
PACKAGE DIMENSIONS
QFP80-P-1420-0.80A Unit : mm
1 . OTYP
, F :i
3.05MAX
0.2i0.1
l i 1.2i0.2
Weight : 1.57g (Typ.)
53 2001-06-19
TOSHIBA TC9309AF
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
54 2001-06-19
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