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TC9271F-TC9271FS-TC9271N
MODULATION/TRANSMISSION IC FOR DIGITAL AUDIO INTERFACE
TOSHIBA
TC9271F/N/FS
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC92Til F, TC9271 N, TC9271 FS
MODULATION/TRANSMISSION IC FOR DIGITAL AUDIO INTERFACE
TC9271F/N/FS are modulation/transmission ICs for
digital audio interface based on EIAJ CP-1201 standards.
FEATURES
Based on EIAJ CP-1201 standards.
Data input format selectable between MSB first or LSB
first. Data length is 24bit max.
Two modes : 2 channel and 4 channel
Channel status data easily set with external pins. The
data can be input serially by microcontroller.
User data can be transmitted.
Double-speed operation
Selectable LRCK polarity
Three packages : 28-pin and 30-pin flat package, 28-pin
shrink DIP package
TC9271 F
SOP28-P-450-1.27
TC9271 N
SDIP28-P-400-1.78
TC9271FS
SSOP30-P-300-0.65
Weight
SOP28-P-450-1.27 . 0.8g (Typ.)
SDIPZ8-P-400-1.78 : 2.2g (Typ.)
SSOP30-P-300-0.65 : th17g (Typ.)
2001 -06-1 9
TOSHIBA
PIN CONNECTION
TC9271F/N/FS
TC9271F, TC9271N TC9271FS
BLOCK I 1 V 28 El VDD BLOCK I 1 V 30 IV.»
UBDA I 2 27 u CKA2 UBDA I 2 29 u CKA2
LRS I 3 26 El CKA1 LRS I 3 28 I CKA1
LRCK I 4 25 , LBIT LRCK I 4 27 TLBIT
BCK I 5 24 , FR32 NC ' 5 26 I NC
DATA I 6 23 II CTG3 BCK ' 6 25 I FR32
VLDY I 7 22 u CTG2 DATA I 7 24 u CTG3
EMPH I 8 21 u CTG1 VLDY I 8 23 ICTGZ
COPY I 9 20 u IS2 EMPH I 9 22 ICTG1
FSI I 10 19 El ISI COPY I 10 21 Tls?
F52[11 18TM2 Fs1I11 201151
CKS I 12 17 l M1 F52 [12 191M2
x1: 13 16 11002 c1
vssr 14 15 31301 x1: 14 17 TDO2
Vss ' 15 16 a DO1
BLOCK DIAGRAM
tf N ,- N m
- g P, gl E 2 2
X U m Ll- U U U
r\ f'\ A
v CLOCK GENERATION SERIAL CKA1
SS CIRCUIT INTERFACE
LRS CKA2
CATEGORY CODE
BCK INPUT m
CIRCUIT + REGISTER l EMPH
VLDY COPY
Bl-PHASE MARK
PARITY GENERATION MODULATION FSI
CIRCUIT CIRCUIT
ir, S E E 6 8
2 2001-06-19
TOSHIBA TC9271F/N/FS
PIN FUNCTION
PIN No.
TC9271F (*) SYMBOL I/O FUNCTION REMARKS
TC9271N TC9271FS
1 BLOCK 0 Block top position output pin
UBDA I User bit data input pin
LRS I LRCK polarity selection pin With pulI-up resistor
LRS L H
L level R channel data L channel data
H level L channel data R channel data
4 4 LRCK I LR clock input pin
5 6 BCK I Bit clock input pin
6 7 DATA I 2ch Data input pin 4ch Data input pin1
7 8 VLDY I 2ch Correction flag input pin 4ch Data input pin1
8 9 EMPH I Emphasis flag setting pin With pull-up resistor
9 10 COPY I P |Copy flag setting pin l S |Fixes to high. With pulI-up resistor
10 11 FS1 I Sampling frequency setting pin1 With puII-up resistor
11 12 F52 I Sampling frequency setting pin 2 With pulI-up resistor
12 13 CKS I Clock divider selection pin With puII-up resistor
13 14 XI I Clock input pin
14 15 I/SS - Ground pin
15 16 DOI o Digital data output pin1
16 17 D02 o Digital data output pin 2
17 18 M1 I Channel mode setting pin1 Select 2ch or 4ch With puII-up resistor
18 19 M2 I Channel mode setting pin2 mode. With puII-up resistor
19 20 ISI I Data input mode setting pin1 With pulI-up resistor
20 21 IS2 I Data input mode setting pin 2 With puII-up resistor
21 22 CTG1 I P Category code setting pin1 s Data input pin With pulI-up resistor
22 23 CTG2 I P Category code setting pin 2 S Clock input pin With puII-up resistor
23 24 CTG3 I P Category code setting pin 3 S Latch pulse input With pulI-up resistor
24 25 FR32 O FR32 output pin
25 27 LBIT I P LBIT input pin S 32/192 bit With pull-up resistor
switching pin
26 28 CKA1 I P Clock accuracy setting pin1 S Fixes to high. With pulI-up resistor
27 29 CKA2 I P Clock accuracy setting pin 2 S Prohibits output With pull-up resistor
at high level.
28 30 VDD - Power supply pin
(Note) : In the above pin description, "2 ch" indicates 2 channel mode; "4 ch", 4 channel
mode. "P" indicates parallel mode; "S", serial mode. For mode settings, use FSI
(pin 10) and FS2 (pin11).
(*) Pin 5 and pin 26 of TC9271FS are NC pin.
2001 -06-1 9
TOSHIBA
OPERATIONAL DESCRIPTION
1. Internal mode setting
2ch mode and 4ch mode setting
To switch between 2ch mode and 4ch mode, use both the M1 and M2 pins.
The 4ch mode is further divided into two modes. In one mode, data are output from two
channels from both output pins, DOI and D02. In the other mode, data are output from
four channels from one output pin (D01 output = D02 output).
Two modes are also supported for inputting data. In the first mode, two channels of data
are input from two input pins, DATA and VLDY. In the second mode, four channels of data
are input from one input pin.
Table 1 2 Channel and 4 Channel Mode Setting
TC9271F/N/FS
MODE SETTING INPUT SIGNAL OUTPUT SIGNAL Comment
M2 PIN M1 PIN LRCK PIN BCK PIN DATA PIN VLDY PIN D02 PIN DOI PIN
L L Lrck Bck Din1 Valid Dit1 Dit1 2 ch mode
L H Lrck Bck Din1 Din2 Dit2 Dit1
H L Lrck Bck Din1 Din2 Dit1 + 2 Dit1 + 2
H H Frck Bck Din1 + 2 Wdck Dit1 + 2 Dit1 + 2
(Note) : Adding validity flag
A validity flag can be added in 2 channel mode. However, in 4 channel mode,
the flag is fixed to low, as VLDY (pin 7) functions as a data or clock input pin in
this mode.
The signals in Table 1 are as follows.
Din1, Din2
Din1 + 2
Dit1, Dit2
Dit1 + 2
Left channel and right channel selection clock
Bit clock
Frame clock (4 channel mode)
Validity flag
Word clock (4 channel mode)
2 channel multiplexed input data
4 channel multiplexed input data
2 channel multiplexed output data
4 channel multiplexed output data
2001 -06-1 9
TOSHIBA TC9271F/N/FS
1-2. Data input mode setting
Two data input modes are supported : LSB-first mode and MSB-first mode. Effective data
are assumed to be before the change point of LRCK. However, MSB-first mode supports
three input data bit length settings.
Table 2 shows the data input modes. In modes where up to 24bit can be input, input the
unused bits fixed to 0.
Table 2 Data Input Modes
SELECTION SIGNAL INPUT FORMAT
IS2 PIN ISI PIN INPUT FORMAT 2s/)ir/lo,, Noilt'? OF NUMBER OF BCK
L L LSB first A 24 max. At least 24 clocks/ch
L H B 24 max. 32 clocks/ch
H L MSB first A 20 At least 20 clocks/ch
H H A 16 At least 16 clocks/ch
A : Effective data before the change point of LRCK.
B : Effective data after the change point of LRCK.
(62, ISI) = (L, L) LRCK X X
BCK WWW
DATA WI don't care ILI1I2I3I4I5I6I7I8I9I10I11I12I13I14I15I16I17I18I19I20I21I22|M| don't care
Fix unused bits on LSB side to 0.
Figure 1a Data Input Format Example 1
((IS2, ISI) = (L, L); effective data before the change point of LRCK, 24 bit/ch max.)
(IS2, ISI) = (L, H) LRCK x X
DATA IMl22l21l20l19l18l17l16l15l14l13l12l11l10l9l8l7 I 6 I 5|4I3I2 I1 ILI don't care Mr21rFFlr8lr7l
Fix unused bits on LSB side to 0.
Figure 1b Data Input Format Example 2
((IS2, ISI) = (L, H); effective data after the change point of LRCK, 24 bit/ch max.)
(ISZ, ISI) = (H, L) LRCK x X
DATA m don't care IMl18l17l16l1sl14l13l12l11l101 9 I 8 I 7 I sl 5 I 4 I 3 I 2 I 1 I LI don't care
Figure 1c Data Input Format Example 3
((IS2, ISI) = (H, L); effective data before the change point of LRCK, 20 bit/ch)
(lS2,lS1)=(H,H) LRCK x X
BCK WWW
DATA ITI don'tcare lMl14l13l12l11l10l9l8l7l6lslal3l2l1lLl don'tcare
Figure 1d Data Input Format Example 4
((IS2, ISI) = (H, H); effective data before the change point of LRCK, 16 bit/ch)
5 2001-06-19
TOSHIBA TC9271F/N/FS
User bits and validity flag input format
Synchronize the user bits and validity flag with the audio data. Because the validity input
pin (VLDY) is used as a data or word clock input pin in other than 2 channel mode, the
output data validity flag is fixed to 0.
Figure 2 shows the input timings.
BCK (64 fs)
ir-ta -i.thir- -ithir-
r—z—tb -..'
2ch Input Mode (M2, M1) = (L, L)
DATA I OR I 1L i .:" 1R i' I A
VLDY VL-OR X VL-1L X _.: VL-1R i' X VL-2L
UBDA UB-OR X UB-1L X '... UB-IR i X UB-2L
Internal Latch n ll :." ,
2ch x 2ch Input Mode (M2, M1) = (L, H) (H, L)
DATA(DATA-A) I 1LA I _.: 1RA -..' I 2LA
VLDY (DATA-B) I 1LB I E IRB '.' I 2Li?
UBDA X UB=1LA X UB=1LB X o--is X UB=1F€€B X UB=2LA X UB=2LB
Internal Latch il n n I" , fl
4ch Input Mode (M2, M1) = (H, H) c.: i.'
DATA I 1A I IB I IC 5 I ID i.' I 2A I 23
VLDY(WDCK) M
UBDA X UB 1A X UB IB X UB-1CE X url..:' X UB 2A X UB-2B
Internal Latch il II II II II II
ta = 11.5s1 /(64*fs) tb = 27.5el/(64*fs) th = 3*1/(64*fs)
Figure 2 V and U Bit Input Timing Chart
6 2001-06-19
TOSHIBA
TC9271F/N/FS
LR clock polarity setting
The LRCK input polarity can be switched using the LRS pin. In 4 channel mode, when the
LRCK polarity is reversed, the Frck (frame clock) and Wdck (word clock) polarities are also
reversed, as in Figure 3b.
L-ch R-ch
LRS = L LRCK (Channel Clock) I I I
LRS = H LRCK (Channel Clock) I I I
Figure 3a LRCK Polarity Setting Example in 2ch Mode
I Ist, data I 2nd, dataI 3rd, data I 4th, data I
I" "T" "T" "t" "I
LRCK (Frck) —l—I—l_
VLDY (Wdck) I I I I I
LRCK (Frck) I I I
VLDY (Wdck) I I I I I
Figure 3b LRCK Polarity Setting Example in 4ch Mode
System clock setting
The CKS pin is used to divide the clock input from XI by two is set. It is possible to compare
the phase of the clock input to LRCK with the phase of the internal divided clock to
automatically determine whether the clock input from the XI pin is a 256 fs- or a 384 fs-type
clock.
Table 4 Clock Divider Setting
CKS PIN
CLOCK INPUT FROM XI PIN
256 fs/384 fs
512fs/768fs
(Note) : "fs" is the sampling frequency.
When the 384 fs-type clock is input with CKS = low, the duty cycle must be
controlled.
7 2001-06-19
TOSHIBA TC9271F/N/FS
1-6. Data input/output formats
When LRS = high, the input/output formats depending on mode are as follows.
LRCK I I I I I
DATA I 1L I 1R I 2L I 2R I
VLDY I v.11. I V-1R I V-2L I V-2R I
UBDA I U-IL I U-IR I U-2L I U-2R I
DOI I OL I OR I 1L I 1R I
D02 Same as DOI .." .....-"" .. '.
Figure 4a Data Input/Output Format Example 1 ((M2, M1) = (L, L) ; 2ch input, 2ch output
LRCK I I I I I
DATA I 1 LA I 1 RA I 2LA I 2RA I
(DATA-B) I 1LB I IRB I 2LB I 2RB I
UBDA I U-1LA I U-1LB I U-1RA I U-IRB I U-2LA I U-2LB I U-2RA I U-2RB I
DOI I OLA I ORA I 1LA I 1RA I
D02 I OLB' I ORB I 1LB I 1RB I
_"0"lrr0L/slcbitlparity
Figure 4b Data Input/Output Format Example 2 ((M2, M1) = (L, H) ; 2ch x 2 input, 2ch x 2
output mode)
LRCK I I I I I
DATA I 1 LA I 1 RA I 2LA I 2RA I
(DATA-B) I 1LB I 1RB I 2LB I 2RB I
UBDA I U 1LA I U 1LB I U 1RA I U IRB I U 2LA I U 2LB I U 2RA I U-2RB I
DOI I OLA I ORA I OLB I ORB I 1LA I 1RA I 1LB I 1RB I
D02 Same as DOI _....-"" _.."
''0"V1Ralcbit Parity
Figure 4c Data Input/Output Format Example 3 ((M2, M1) = (H, L) ; 2ch x 2 input, 4ch
output mode)
LRCK I I I I I
(FRCK)
DATA I 1A I IB I IC I ID I 2A I 23 I 2C I 2D I
(WDCK)
UBDA I U-IA I U-1B I U-1C I U-1D I U-2A I U-2B I UK I U-2D I
DOI I oc I 0D I 1A I 13 I IC I 1D I 2A I 213 I
D02 Same as DOI ..." .."' ..." a
Figure 4d Data Input/Output Format Example 4 ((M2, M1) = (H, H) , 4ch input, 4ch output
8 2001-06-19
TOSHIBA TC9271F/N/FS
2. Channel status setting
The channel status can be set by two methods. The first method is parallel DC setting. The second
method is serial setting using a microcontroller. (Table 7)
The EMPH flag in channel status is set to the OR of the parallel data and the serial data in serial
Time Slot
0 1 2 3 4 5 6 7 8 9 1O 11 12 13 14 15
I :; IE I IN I I I I I I I i»;
0!0!?5!E!0!E 0l0"-t- See2-1-2 T-r-ma-:
l l U l LLI I I l l . . . l I I _I
l l l l I l l I I l l l I
= CONTROL BIT -l MODEJ CATEGORY CODE
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
l l l I l l l I I l I
I l I See I I w I N I I T" l N I
0:01010 '32%i0i0eiidii0iogig 0:0
I I I I I I I I I I I
L fdelfil "ilf)vtlit) L SAMPLING ' CLOCK
FREQUENCY ACCURACY
Figure 5 Channel Status Bit Correspondence
2-1. Parallel mode
This mode is used to make parallel DC setting of the channel status.
Figure 5 shows the bits which can be set. In Figure 5, "o'' indicates that the bit is fixed to 0.
Accordingly, in home digital audio equipment, the mode is fixed to 00 and the source
number to 0000.
2-1-1. Control bit setting ;
Fixing three of the six control bits to 0 results in the following limitations.
(a)Time Slot 0 = 0 ; Only for home equipment
(b)Time Slot 1 = 0 ; Only for audio data
(c) Time Slot 4 = 0 ; Only for fixing emphasis to 50/15ps
Bits other than these can be DC-set directly from the pin.
(a)Time Slot 2 = COPY ; When COPY pin = H, no copy protection
When COPY pin = L, copy protection (Copying inhibited)
(b)Time Slot 3 = EMPH ; When EMPH pin = H, emphasis is 50/15
When EMPH pin = L, no emphasis
(c) Time Slot 5 = M2 ; For 2 channel output per output pin, set to two channels
For 4 channel output per output pin, set to four channels
9 2001-06-19
TOSHIBA
TC9271F/N/FS
2-1-2. Category code setting ;
The category code is set using pins CTG1--3.
The category bits shown in Table 5 as "L" can be freely set using the LBIT pin. For details,
refer to the EIA) CP-1201 standards.
Table 5 Category Code Setting
CTG CATEGORY
0 0 General format [000 00000 ]
0 1 Digital mixer [010 0100L ]
1 0 Sample rate converter [010 1100L ]
1 Digital sampler [010 0010L ]
0 ADC (no copy right) [011 0000L ]
1 0 1 ADC (copy right) [011 0100L ]
1 0 Synthesizer [101 OOOOL ]
1 Microphone [101 1000L ]
.Channel number setting ;
In 2 channel mode, the channel number is added automatically. In 4 channel mode, all the
bits are fixed to 0.
Table 6 shows the specific details.
Table 6 Channel Number Addition Correspondence
PIN NAME CHANNEL NUMBER
M2 M1 LRCK LRS = H LRS = L
L L L [1000] [0100]
H [0100] [1000]
L H L [1000] [0100]
H [0100] [1000]
Other combinations [0000l
10 2001-06-19
TOSHIBA TC9271F/N/FS
2-1-4. Sampling frequency setting ;
Pins FSI and FS2 are used for setting the sampling frequency.
Table 7 Sampling Frequency Setting
PIN INPUT SETTING DATA SETTING MODE
FSI F52 SAMPLING FREQUENCY [TS24-271 (PINS CTG1--3, LBIT, CKA1--2)
L L 44.1 kHz [0000]
L H 48 kHz [0100] Parallel mode
H H 32 kHz [1100]
H L Setting by serial data transfer Serial mode
(Note) : When FS1 = high and FS2 = low, serial mode is set. Thus, the mode
becomes momentarily serial mode when the sampling frequency switches,
momentarily disturbing clocks and data.
2-1-5. Clock accuracy bit setting ;
Use the CKA1 and CKA2 pins to set the clock accuracy. The following describes the modes.
(a)Standard mode (level II) ;
When setting to output disable mode, change CKA1 and CKA2 from low to high.
(b)Variable pitch mode (level III) ;
When setting to output disable mode, change CKA1 only from low to high and keep CKA2
(c) Accuracy mode (level I) ;
When setting to output disable mode, change CKA2 only from low to high and keep CKA1
Table 8 Clock Accuracy Setting
PIN INPUT SETTING DATA
CKA1 CKA2 CLOCK ACCURACY [TS28, 29] DOI, D02 OUTPUT STATUS
L L Level II [00]
L H Level III [01] Normal output
H L Level I [10]
H H DOI and D02 output fixed to low (output disable mode)
(Note) .' When (CKA1, CKA2) = (H, H), output disable mode for digital data is
entered, and DOI and D02 output is fixed to low.
11 2001-06-19
TOSHIBA
2-2. Serial mode
TC9271F/N/FS
This mode is used to serially set data for the channel status using a microcontroller.
As Table 9 shows, in serial mode some pin functions differ from those in parallel mode.
Table 9 Pin Functions in Serial Mode
PIN NAME FUNCTION REMARKS
EMPH EMPH flag input The flag is set based on the OR of EMPH and serial data.
COPY - (Fixed to high)
FS1 - (Fixed to high) .
FS2 - (Fixed to low) Set for serial mode
CTG1 Data input
CTG2 Clock input Channel
CTG3 Latch pulse input status .
LBIT 32/192 bit switching Set to low for 192 bit mode pmmsmg
CKA1 - (Fixed to high)
CKA2 DO1/2 output setting Set to high to disable DOI and D02 pin output.
(Note 1) As channel status data, the EMPH flag uses the OR of the parallel data and
serial data.
(Note 2) The channel number (TIME SLOT 20 and 21 in Figure 5) is automatically set.
(Effective only in 2 channel mode. (M2 pin = low))
(Note 3) The serial setting register consists of 32 bit. To reset (clear) this register at
power on, set to parallel mode. That is, fixing FS2 to low, set the FSI pin to
low at power on then to high.
2001 -06-1 9
TOSHIBA TC9271F/N/FS
2-2-1. Channel status input ;
The 32 and 192 bit input modes are supported to serially input the channel status.
(1)32 bit input ; (LBIT = high)
This mode is used to input only 32 bit from the start of the channel status.
The timing of the data is conditioned to make them effective from the next block.
(2)192 bit input , (LBIT = low)
This mode is used to input all 192 channel status bits.
Input 192bit (32 x 6) data in sync with the FR32 and BLOCK signals. Because the internal
register consists of 32 bit, input 32 bit data before the FR32 falling edge.
In this mode, 0~31 frames of input data are input while BLOCK output is high. Figure 6 is an
input timing example.
BLOCK -I-l I"
FR32 m -l_I-l,
input Time slot 0-31 X Time slot 32-63 X X Time slot 160-191 X
(--Actuavy output from here
Figure 6 192 Bit Input Timing Example
2-2-2. Serial Interface
The serial interface processes data, clocks, and latch signals. Figure 7 shows an example of
serial interface timing.
FR32 l-
clock(CTG2) I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 'i'
data(CTG1) (1X2X3X4X5X6X7X8X9) 'c6X27X28X29X30X31X32)
latch(CTG3) I I 5
5 th 5
Data latch timing p- -e
* th > l As
Figure 7 Serial Interface Timing Example
Data are latched at the clock rising edge.
In 192 bit input mode, data are latched to the internal registers at each falling edge of FR32.
Accordingly, input the data between the FR32 falling edge and the next falling edge. An
interval of at least lps is required between the latch signal and the FR32 falling edge.
13 2001-06-19
TOSHIBA TC9271F/N/FS
MAXIMUM RATINGS (Ta = 25°C)
ITEM SYMBOL RATING UNIT
Power Supply Voltage VDD -0.3--6.0 V
Input Voltage Vin -thr-VDD + 0.3 V
TC9271F 600
Power Dissipation TC9271N PD 800 mW
TC9271FS 350
Operating Temperature Topr -35--85 "C
Storage Temperature Tstg - 55~150 "C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = 25°C, VDD = 5V)
DC characteristics
ITEM SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Power Supply V Ta = -35--85oC 4.5 5.0 5.5 V
Voltage DD Ta = -35--60''C (*1) 2.7 3.0 3.3
. XI = 16.9 MHz
Current Consumption IDD - CKS = low level - 5 15 mA
" n - * -
Input H Level VIH ( 2) x 0.8 VDD
Voltage VDD V
" " - * -
L Level VIL ( 2) 0.0 x 0.2
Input "H" Level IIH - (*2), VIN = VDD - - 1.0 A
Current "L" Level IIL - (*3), VIN = OV - 1.0 - - ‘1
Output "H" Level IOH - (*4), VOH = 4.51/ - - -1.6 mA
Current "L" Level IOL - (*4), VOL = 0.5V 3.0 - -
PulI-up Resistance RUP - (*5) - 100 - kn
(*2) : All input pins
(*3) : All input pins other than (*5)
(*4) : All output pins
(*5) : All pins with pull-up resistor
AC characteristics
: At the low-voltage using, normal speed mode is guaranteed.
ITEM SYMBOL 27il" TEST CONDITION MIN. TYP. MAX. UNIT
Operating Frequency fopr - 7.5 16.9 40.0 MHz
Input Frequency fLR - LRCK duty cycle = 50% 30.0 44.1 100.0 kHz
fBCK BCK duty cycle = 50% 0.96 1.41 6.40 MHz
Rising Time tr Pins LRCK, BCK, DATA, and XI - - 15
Falling Time tf - (10--90%) - - 15 ns
. BCK falling edge
Delay Time td - _) LRCK, DATA - - 40
2001 -06-1 9
TOSHIBA TC9271F/N/FS
(1) Clock and data output timings
ITEM SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Output Rising Time tor Pins BLOCK, DOI, D02, and - - 20 ns
Output Falling Time tof FR32 (10--90%) - - 20
(2) Microcontroller interface timing (in serial mode)
ITEM SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Strobe Pulse Width twp - CTG3 0.5 - -
Clock Pulse "H" Level tWH - CTG2 1.0 - -
Width "L" Level tWL - CTG2 1.0 - - ps
Hold Time tHLD - CTG1 -YCTG2 0.5 - -
Delay Time tCL - CTG2 -9CTG3 0.5 - -
(*6) : In 192 bit serial input mode, set th >1ps.
(*7) : Input data in sync with the clock falling edge.
Data are loaded internally at the clock rising edge.
CTG3 A
(Latch Pulse)
55:: W \--- " / \ / Hm th
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(Data)
15 2001-06-19
TOSHIBA
PACKAGE DIMENSIONS
SOP28-P-450-1.27
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1.27 _ _
L 19.0MAX
18.5Hh2
Weight : 0.8g (Typ.)
TC9271F/N/FS
Unit : mm
(450mil)
I I 1.0i0.2
2001 -06-1 9
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TOSHIBA TC9271F/N/FS
PACKAGE DIMENSIONS
SSOP30-P-300-0.65 Unit : mm
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5.6i0.2
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Weight : 0.17g (Typ.)
18 2001-06-19
TOSHIBA TC9271F/N/FS
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
19 2001-06-19
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