TC9263AF ,CD SINGLE-CHIP PROCESSORFEATURES0 Sync pattern detection, sync signal protection andsvnchronization can be made correctlv. ..
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TDA7350A ,22W BRIDGE-STEREO AMPLIFIER FOR CAR RADIOTDA7350A22W BRIDGE-STEREO AMPLIFIER FOR CAR RADIOVERY FEW EXTERNAL COMPONENTSNO BOUCHEROT CELLSNO B ..
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TDA7365 ,2 x 6W CAR RADIO AMPLIFIER PLUS SOLID STATE SWITCHTDA73652 x 6W CAR RADIO AMPLIFIERPLUS SOLID STATE SWITCHADVANCE DATAOUTPUT POWER 2x6W/4Ω @14.4V, 1 ..
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TDA7370 ,QUAD POWER AMPLIFIER FOR CAR RADIOTDA7370QUAD POWER AMPLIFIER FOR CAR RADIOMINIMUM EXTERNAL COMPONENT COUNTHIGH CURRENT CAPABILITYNO ..
TDA7370B ,QUAD POWER AMPLIFIER FOR CAR RADIOTDA7370BQUAD POWER AMPLIFIER FOR CAR RADIOMINIMUM EXTERNAL COMPONENT COUNTHIGH CURRENT CAPABILITYNO ..
TC9263AF
CD SINGLE-CHIP PROCESSOR
TOSHIBA TC9263AF
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9263AF
CD SINGLE-CHIP PROCESSOR
The TC9263AF is a single chip processor for sync
separation protection/synchronization, EFM
demodulation, error correction / interpolation,
microcomputer interface, CLV servo and focus tracking
servo in CD player system.
In combination with the TA8190F/TA8191F/TA2031F/
TA2035F/TA2065F, which are focus tracking servo LSI, a
CD player system can be composed very simply.
FEATURES
. Sync pattern detection, sync signal protection and
synchronization can be made correctly. QFP100-P-1420-0.65
o Built-in EFM demodulation and subcode demodulation circuit. Weight : 1.6g (Typ.)
Has the correction capacity of double and triple correction for
C1 and C2 each correcting units, respectively, using CIRC correction theoretical format.
Jitter absorbing capacity of 16 frames.
Built-in 16K RAM.
Built-in Digital out circuit.
Built-in variable pitch control circuit.
Built-in digital level meter and peak meter circuit.
The output circuit of each channel (Left/Right) has the independent digital attenuation circuit.
Audio-out circuit is apply to bilingual output.
Read timing free subcode Q data.
Built-in the output circuit for CD-ROM (CD-l).
Built-in data slicer and analog PLL (free-adjustment VCO adopted) circuit.
Focus/Tracking loop gain auto adjusting function incorporated.
Built-in AFC and APC circuit for disc motor CLV servo.
Built-in focus tracking servo control circuit.
Tracking search control apply to all modes.
Double speed play is possible.
Built-in microcomputer interface circuit.
In CMOS structure, high speed and low power dissipation.
100 pin flat package.
OOOOOOOOOOOOOOOOOO
98091 OEBA2
O TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing
TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss
of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the
TOSHIBA Semiconductor Reliability Handbook.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the ap Iications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
0 T e information contained herein is subject to change without notice.
1999-03-19 1/16
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TOSHIBA TC9263AF
FUNCTION OF EACH PIN
Em SYMBOLI/O FUNCTIONAL DESCRIPTION REMARK
1 l/SS - Digital ground terminal. -
Phase compare (XI and VXI signal) output terminal for 3-state output
2 VPD O . .
vanable-pitch. NDD, Hi2, V55)
3 CKSE I Internal clock selection terminal. -
4 TESTO I Test terminal. Normally, keep at "H" level or open. With pull-up resistor
5 COFS 0 Correction system frame periodic signal output terminal. -
7.35kHz
6 SPDA 0 Processor status signal output terminal. -
7 SPCK 0 Processor status signal read clock output terminal. 176.4kHz -
8 SBOK O Subcode Q data CRC checking result output terminal. -
The checking result is OK at "H" level.
9 CLCK I Subcode P-W data readout clock input terminal. -
10 DATA 0 Subcode P-W data output terminal. -
11 SFSY O Play-back frame periodic signal output terminal. -
12 SBSY O Subcode block sync signal output terminal. The Subcode sync -
is detect, output "H" level at SI position.
Subcode Q data emphasis status signal output terminal.
13 EMPH O Emphasis ON at "H" level, OFF at "L" level. Output polarity -
can change by command.
Channel clock output terminal. Normally, 44.1kHz.
14 LRCK 0 Output L-channel at "L" level, R-channel at "H" level. -
Output polarity can change by command.
15 VDD - Digital power supply voltage terminal. (+5V) -
16 I/SS - Digital ground terminal. -
17 WDCK 0 Word clock output terminal. Normally, 88.2kHz. -
18 BCK 0 Bit clock output terminal. Normally, 1.4112MHz. -
19 AOUT 0 Audio data output terminal. -
Interpolation status signal output terminal. Output "H" level
20 IPF O . . . -
at C2 correcting unit unable error correction.
21 MU-TEO 0 Audio mute signal output terminal. Mute ON at "L" level. -
22 DOUT 0 Digital data output terminal. -
23 ROUT 0 Digital data for CD-ROM output terminal. -
ROUT signal read clock output terminal. It is possible to select
24 BACK 0 2.8MH2 or 5.6MH2 by command. -
25 FLGA O Internalsjtus monitor terminal. It is possible to select TEZC, -
FOON, FOK, RFZC signal by command.
Internal status monitor terminal. It is possible to select 'rrit5TT,
26 FLGB O -r_r_.r..r_r._ .r_r..r...r...r...r_r..r...r.. . -
FOON, FDON, RFZC signal by command.
1999-03-19 3/16
TOSHIBA TC9263AF
tl) SYMBOLl/O FUNCTIONAL DESCRIPTION REMARK
27 FLGC O 1_r1.ttrre.l_s_taty_t.i monitor terminal. It is possible to select TRON, -
TSSR, FOK, SRCH signal by command.
28 FLGD O 1n_tti.tals_ta_tueonitor terminal. It is possible to select TRON, -
DMON, HYS, SHC signal by command.
Lock status output terminal.
29 m 0 If sync pattern under EFM signal cannot be detector for 17ms
continuously by runway detection information, this terminal is -
put at "H" level.
30 VDD - Digital power supply voltage terminal. (+5V) -
31 Vss - Digital ground terminal. -
32 lOl l/O Command controllable I/O port terminals -
33 IO2 .
Tracking gain adjusting analog switch output terminals. VREF
34 TEL1 or HiZ. -
0 It is possible to select Normally mode or Command control
35 TEL2 -
36 DFCT1 O Defect (drop-out of data) detection signal output terminal. -
VREF when defect is detected. Normally, Hi2.
37 DFCT2 O Black-dot (drop-out of data) detection signal output terminal. -
VREF when defect is detected. Normally, Hi2.
38 TESH I Tracking error signal sample holding analog switch input Analog input
terminal.
Trackin servo o eration ON/OFF analo switch out ut
39 TEOF O (e",',,c7nna1 VREF wphen the tracking servo l OFF. P Analog output
40 AVDD - Analog power supply voltage terminal. (+5V) -
41 AVSS - Analog ground terminal. -
Tracking servo gain up analog switch output terminal. VREF
42 TGUL O or HiZ. It is possible to select Normally mode or Command -
control mode.
43 TGUH1 Tracking fe?"' gain up analog switch output terminals. Hi2
0 when gem IS up. Normally, VREF. . . -
44 TGUH2 TGUH1 IS used at normal play and TGUH2 IS used at high
(Double and Quadruple) speed play.
Tracking actuator kick signal output terminal. It used NKIC,
45 TKIC1 O CKIC and tracking gain adjusting mode. 3-state output
Kicks in the outer direction at "21/REF" level and in the inner (2VREF, HiZ, AVss)
direction at "AVss" level. Normally, HiZ.
Tracking actuator kick signal output terminal. It used FVKIC. It
46 TKIC2 O is possible to polarity change. 3-state output
Output signal form is PWM. (3-state 2VREF, VREFI AVSS at (ZVREF, HiZ, AVSS)
132kHz). Normally, HiZ.
47 TEST1 I Test terminal. Normally, keep at "H" level or open. With pull-up resistor
1999-03-1 9 4/16
TOSHIBA TC9263AF
tl) SYMBOLl/O FUNCTIONAL DESCRIPTION REMARK
48 FMON 0 Feed servo ON/UOfFuanalog switch outpltit terTinal. The feed -
servo IS ON at Hi2 level, and OFF at VREF level.
Feed motor FWD/BWD feeding control signal output
. . . 4-state output
49 FMFB 0 terminal. Output signal form IS PWM. (3-state 2VREF, I/REF, (2VREF VREF AVSS
AVSS at 132kHz) Feed in the outer direction at "2VREF" level HiZ) ' ' '
and in the inner direction at "AVss" level. Normally, HiZ.
Disc motor driving circuit gain change-over analog switch
output terminal. The CLV servo is OFF at "Hi2" level. It is
50 DMON 0 possible to select "Hi2" or "VREF" level, when CLV servo is -
Disc motor CLV servo AFC signal output terminal.
OPERATION COMMAND DMFC OUTPUT
51 DMFC 0 Motor acceleration DMFK "2VREF" 3-state output
CLV servo ON DMSV AFC Signal (PWM) (2VREF, I/REF, AI/SS)
Motor deceleration DMBK "AVss"
CLV servo OFF DMOFF "VREF"
52 DMPC 0 Disc motor CLV servo APC signal output terminal. i1t,Ctl,i,o/fz',"fvss,
53 2VREF - Double times reference voltage input terminal. (VREFXZ) -
54 VREF - Reference voltage input terminal. -
Servo mode indicating signal output terminal. It is possible to
control laser-diode (LD) ON/OFF and focus servo ON/OFF.
SEL LD FOCUS SERVO OPERATION 3-state output
55 SEL O .
"AI/ss" OFF OFF LD OFF (AI/DD, Hi2, Avss)
"HiZ" ON OFF Focus search
"AVDD" ON ON Focus ON
Focus actuator driving signal output terminal in the focus
. . " " 3-state output
56 FCSI O serach adjust mode. Lens gets for away from disc at AVDD ' (AVDD Hi2 AVSS)
Lens gets near disc at "AI/ss". Normally, "Hi2". ' '
Focus actuator driving signal output terminal in the focus
. . . " " 3-state output
57 FKIC 0 gain adjust mode. Lens gets for away from disc at AVDD ' (AVDD HiZ AVSS)
Lens gets near disc at "AVSS". Normally, "Hi2". ' '
58 FEL1 Focus gain adjusting analog switch output terminals. VREF or
0 Hi2. It is possible to select Normally mode or Command -
59 FEL2 control mode.
60 FEI I Focus error signal input terminal. Analog input
61 TEI I Tracking error signal input terminal. Analog input
62 SBAD I Sub-beam adding signal input terminal. Analog input
1999-03-1 9 5/16
TOSHIBA TC9263AF
tl) SYMBOLl/O FUNCTIONAL DESCRIPTION REMARK
63 RFRP I RF ripple signal input terminal. Analog input
64 VDD - Digital power supply voltage terminal. (+5V) -
65 VSS - Digital ground terminal. -
Focusing and tracking signal output terminal. (Internal 5 bits
66 ZCL1 O DAC output) Analog output
Usually use for monitoring of internal signal.
SBAD and RFRP signal output terminal. (Internal 5 bits DAC
out ut)
67 2CL2 O 'll2'l'/; use for monitoring of internal signal. Analog output
(SBAD : sub-beam additional signal, RFRP : RF ripple signal)
68 AVDD - Analog power supply voltage terminal. (+5V) -
69 AVss - Analog ground terminal. -
70 RFI I RF signal input terminal. Analog input
TMAX output control terminal. When input level is "L",
71 TMCNT I TMAX terminal output fixes "Hi2". Normally, input level is -
72 SLCO 0 Data slice level output terminal. (Internal DAC output) Analog output
PDO output control terminal. When input level is "L", PDO
73 PDCNT I . . " . " . . " " -
terminal output fixes Hi2 ' Normally, input level IS H .
74 PDO 0 P.hase, comparator error signal output terminal between EFM 3-state ou-tput
signal and PLCK. (21/REF, Hi2, AVSS)
TMAX signal output terminal. TMAX is frequency information
of RF signal.
75 TMAX O TMAX PERIOD TMAX OUTPUT 3-state ou-tput
Longer than specified period "AVSS" (2VREF, an, AVss)
Shorter than specified period "21/REF"
Specified period "HiZ"
76 LPFN I LPF amplifier negative input terminal for PLL. Analog input
77 LPFO O LPF amplifier output terminal for PLL. Analog output
78 TESIN I Test terminal. Normally, keep at "H" level or open. With puII-up resistor
79 VCOF O VCO noise filter terminal. -
80 TEST2 I Test terminal. Normally, keep at "H" level or open. With puII-up resistor
81 l/SS - Digital ground terminal. -
PLCK signal output terminal. It is possible to select PLCK,
82 PLCK O 17MCK (VCO), EFMS (EFM slice data), fixes "H" level by -
command.
Command and data sending/receiving chip enable signal
83 = I input terminal. Schmitt trigger input
The bus line becomes active at "L" level.
84 BUCK I Command and data sending/receiving clock input terminal. Schmitt trigger input
1999-03-19 6/16
TOSHIBA TC9263AF
tl) SYMBOLl/O FUNCTIONAL DESCRIPTION REMARK
85 BUSO . . .
86 BUS1 Command and data sending/receiving input/output Schmitt trigger input.
I/O . Open drain output,
87 BUS2 terminals. With puII-up resister
88 BUS3
89 FTst5 0 High speed play monitor output terminal. Double and -
Quadruple speed play at "L" level. Normally, "H".
90 VDD - Digital power supply voltage terminal. (+5V) -
91 vss - Digital ground terminal. -
92 XI I Crystal oscillator input terminal. -
93 XO 0 Crystal oscillator output terminal. -
- Reset in ut terminal. . .
94 RST I The intesnal system is reset at "L" level. With pull-up resistor
95 MCK 0 Master clock output terminal. -
96 TEST3 I Test terminal. Normally, keep at "H" level or open. With pull-up resistor
97 TEST4 I Test terminal. Normally, keep at "H" level or open. With puII-up resistor
98 VXI I External VCO clock input terminal for variable-pitch. Alanlog input
99 VXO O Buffer output terminal at VXI signal. -
100 VDD - Digital power supply voltage terminal. (+5V) -
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage VDD -0.3--6.0 V
Input Voltage VIN -0.3-VDD +0.3 V
Power Dissipation PD 1,250 mW
Operating Temperature Top, - 35--85 °C
Storage Temperature Tstg - 55--150 °C
1999-03-1 9 7/16
TOSHIBA TC9263AF
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, VDD=5V, 2VREF=4.2V, VREF=2.IV, Ta =25°C)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply Voltage VDD - Ta= -35--85oc 4.75 5.0 5.25 V
Operating Supply Current IDD - XI=16S344MHz, In normal mode - 40 70 mA
"H" Level VIH (1) Whole input terminals except 3.5 - '32
B -- B K ct-E .
Input "L'' Level vle uso 3, UC and CC 0 - 1.5 v
Volta e _....-.....-..- V
g "H" Level VIH (2) BUSO--3, BUCK, CCE 4.0 - DD+
- . 0.3
" " (Schmitt Input)
L Level VIL(2) 0 - 1.0
Input "H" Level ITH VIH = 5V CMOS input terminals - - 1.0
C - except analog input
urrent "L'' Level ITL VIL=0V terminal. -1.0 - - A
Try State "H" Level ITLH VIH =5v - - 1.0
Leak -
Current L Level ITLL VIL=0V -1.0 - -
" " VPD, COFS, SPDA,
- DATA, SEL, FCSI,
"L'' Level IOL(1) VOL=O.4V FKIC, PDCNT 2.5 - -
VOUT=VDD
"H" Level IOH (2) v0... =4.6V SFSY, SBSY, EMPH - - - 1.0
"L'' Level IQLQ) VOL=0.4V VOUT=VDD 1.5 - -
WDCK, IPF,
MUTEO DOUT
"H" Le el I V =4.6V ' ' - - -2.0
V OH (3) OH DACK, FLGA, FLGB,
Output FLGC, FLGD, LT5tTd,
Current - lol, I02, ROUT, mA
" " - LRCK, BCK, AOUT,
L Level loL(3) VOL=0.4V PLCK 4.0 - -
VOUT=VDD
"H" Level IOH (4) VOH =4.6V MCK, VXO, XO - -2.0
"L" Level |OL(4) VOL=0.4V VOUT=VDD 3.0 - -
TKIC1 TKIC2
"H" L I I V =3.8V ' ' - - -0.4
eve OH (5) OH FMFB, DMFC,
- DMPC
"L'' Level I V =0.4V 2.5 - -
OL(5) OL VOUT=2VREF
"H" Level IOH (6) VOH =3.8V PDO, TMAX - - - 1.5
"L" Level |OL(6) VOL=0.4V VOUT=2VREF 2.5 - -
1999-03-19 8/16
TOSHIBA TC9263AF
CHARACTERISTIC SYMBOL 2i'J TEST CONDITION MIN. TYP. MAX. UNIT
Analog "H" Level IOFH - V|H=5V - - 1.0
Switch OFF PA
Current "L" Level IOFL - VIL=01/ - 1.0 - -
FEL1, FEL2, TEL1, TEL2, FMON,
. TGUL, TGUH1, TGUH2, FMFB,
2,t2dftch ON RON (1) - DFCT1, DFCT2, TEOF, DMON, - - 0.6 kn
RON (2) TESH - - 1.2
RUP(1) fe-rr - 65 -
Pull-Up Resistance RUP(2) - W, TEST-r-s - 45 - kn
RUP(3) BUSO--3 8 - -
Oscillation Amplifier RN (1) - Xl-XO 2.0 3.5 5.0 MG
Feedback Resistance RN (2) VXI-VXO, TESIN 0.25 0.5 1.0
2Cating Frequency fOP - XI 6 - 28 MHz
1999-03-19 9/16
TOSHIBA TC9263AF
AC CHARACTERISTICS
(1) Clock system timing
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Clock Pulse "H" Level tHW 18 - -
Width "L" Level tLW XI in ut 18 - - ns
Input Rising Time tr p - - 10
Input Falling Time tf - - 10
Transfer Time "H" Level tpHL1 - - 60
(1) "L" Level tme Xl-9MCK - - 60
Transfer Time "H" Level tpHL2 - - 60
M K B K
(2) "L" Level tpLH2 C -9 C - - 60 ns
Transfer Time "H" Level tpHLS - - 100
(3) "L" Level tpLH3 MCK-9COFS - - 100
Output Rising Time (1) tor1 MCK BCK - - 15 ns
Output Falling Time (1) tofl ' - - 15
Output Rising Time (2) tor2 COFS - - 40 n
Output Falling Time (2) tof2 - - 40 5
tr tf I tHW I th I
XI / N k i P
tme tor1 tof1
MCK / N, / N
tpHL2, 3 t LH2, 3
BCK, COFS tt
1999-03-1 9 10/16
TOSHIBA TC9263AF
(2) Microcomputer interface timing
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Clock Pulse "H" Level tBHW IO - -
. " " BUCK
Width (1) L Level tBLW 10 - - ps
Clock Pulse Width (2) tCC CCE 6 - -
Delay Time (1) tCB CCE-9BUCK - - 6
Delay Time (2) tWB Command Data-yBUCK 0 - - #5
Delay Time (3) tCS CCE-astatus Output - - 6
Set-Up Time (1) tRD BUCK-aRead Data Output - - 6 s
Set-Up Time (2) tBA BUCK-SACK, Parity Output - - 6 ’u
. BUCK-SACK, Parity,
Hold Time (1) tsz1 Status Output - - 6 S
Hold Time (2) tszz CCE-ystatus Output - - 6 #
Hold Time (3) tWH BUCK-eCommand Data 6 - -
(a)Write command processing mode
(Microcomputer Output)
tCB tBLw tBHw tCC
BUCK - I
suso~3 CM
Command Data
(TC9263AF Output) tCS t521 _ tBA
BUSO-3 1( Status Y ACK
Off Mode Write Command Processing Mode Off
1999-03-19 11/16
TOSHIBA
TC9263AF
(b)Read command processing mode
(Microcomputer Output)
CCE \ I
tca tBLw , tBHw
BUCK N l /
tWB tWH
BUSO-3 SRC
(TC9263AF Output)
tcs t$21 tRD tBA
BUSO-3 1( Status / l RO i Parity
Off Mode Read Command Processing Mode Off
(c) Idle mode
(Microcomputer Output)
CCE \ I
BUSO~3
(TC9263AF Output)
tcs tszz
BUSO-3 1( Status )
Off Idle Mode Off
1999-03-1 9 12/16
TOSHIBA
(3) Data output system timing
TC9263AF
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
"H" L I - -
Transfer Time " " eve tPHL BCK-eAOUT, WDCK, LRCK 30 ns
L Level tpLH - - 30
Output RISlrlg Tlrhe tor AOUT, WDCK, LRCK - - 15 ns
Output Falling Time tof - - 15
BCK -\_/-N_/-N_/-\_/'
AOUT X X
tor, tof
LRCK, WDCK
tof tor
tpHL I tpLH
(4) Output timing for subcode P~W
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
ftl Pulse H Level tHW CLCK 2 - - ns
Width "L" Level tLW 2 - -
Set-Up Time tSUP SFSY-YDATA 0.4 - - n
Read Access Time tRAC CLCK-9DATA 1.2 - - s
SFSY l
DATA T l Q X R
- tsup - tRAC
CLCK \ /-N_/-
tHW tLW
1999-03-19 13/16
TOSHIBA
(5) Output time for subcode Q
TC9263AF
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
. "H" Level tpHL -50 - 200
SFSY-9SBOK, SBSY
Transfer Time "L" Level tpLH -50 - 200 ns
Output RISIhg Turne tor SBOK, SBSY - - 40 ns
Output Falling Time tof - - 40
tpHL tpLH
SFSY I N
DATA, SBOK, I
tof tor
(6) Status signal output timing
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
. "H" Level tHDH - - 200
WDCK-9SPDA
Hold Time "L" Level tHDL - - 200 ns
Output RlSll-Wg Tlf‘ne tor SPDA - - 40 ns
Output Falling Time tof - - 4O
\_/_\_/_\_/_\_/_
SPDA X X
tHDH, tHDL tor, tof
1999-03-19 14/16
TOSHIBA TC9263AF
(7) Digital output timing
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
"H" Le el t - - 60
Transfer Time " " V M MCK-9DOUT ns
L Level tpLH - - 60
Output RISIrIg Tlrhe tor DOUT - - 14 ns
Output Falling Time tof - - 14
MCK -I I N I N I N I
DOUT X
tor. tof
l:e tpLH
1999-03-1 9 15/16
TOSHIBA TC9263AF
OUTLINE DRAWING
QFP100-P-1420-0.65 Unit : mm
0.575TYP
2 710 2
0.15:l:0.1
o .15 93.05
I 1.2:t0.2
Weight : 1.6g (Typ.)
1999-03-19 16/16
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