TC9256P ,PLL FOR DTSTOSHIBA TC9256,57P/FTC9256P, TC9256F, TC9257F, TC9257FTC9256P, TC9256F, TC9257P and TC9257F are pha ..
TC9257AFG ,PLLBlock Diagram Note: There are no pins marked z in the TC9256APG or TC9256AFG. Pin names and numbe ..
TC9257AFG ,PLLBlock Diagram Note: There are no pins marked z in the TC9256APG or TC9256AFG. Pin names and numbe ..
TC9257F ,PLL FOR DTSTOSHIBA TC9256,57P/FTC9256P, TC9256F, TC9257F, TC9257FTC9256P, TC9256F, TC9257P and TC9257F are pha ..
TC9257F ,PLL FOR DTSTOSHIBA TC9256,57P/FTC9256P, TC9256F, TC9257F, TC9257FTC9256P, TC9256F, TC9257P and TC9257F are pha ..
TC9257P ,PLL FOR DTSTOSHIBA TC9256,57P/FTC9256P, TC9256F, TC9257F, TC9257FTC9256P, TC9256F, TC9257P and TC9257F are pha ..
TDA7342NTR ,DIGITALLY CONTROLLED AUDIO PROCESSORELECTRICAL CHARACTERISTICS (V = 9V; R = 10KΩ; R = 50Ω; T = 25°C; all gains = 0dB;S L g ambf = 1KHz. ..
TDA7343D ,DIGITALLY CONTROLLED AUDIO PROCESSORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Operating Supply Voltage 10.5 VST Operating Am ..
TDA7343D ,DIGITALLY CONTROLLED AUDIO PROCESSORTDA7343®DIGITALLY CONTROLLED AUDIO PROCESSORINPUT MULTIPLEXER- TWO STEREO AND ONE MONO INPUTS- SELE ..
TDA7343D ,DIGITALLY CONTROLLED AUDIO PROCESSORELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K ; Rg = 50 ; Tamb = 25 C; all controls flat(G - 0dB); ..
TDA7343D013TR ,DIGITALLY CONTROLLED AUDIO PROCESSORELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K ; Rg = 50 ; Tamb = 25 C; all controls flat(G - 0dB); ..
TDA7344P ,DIGITAL CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIXTDA7344DIGITAL CONTROLLED AUDIO PROCESSORWITH SURROUND SOUND MATRIX1 STEREO INPUTVOLUME CONTROL IN ..
TC9256f-TC9256P-TC9257F-TC9257P
PLL FOR DTS
TOSHIBA
TC9256,57P/F
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9256P, TC9256F, TC9257P, TC9257F
PLL FOR DTS
TC9256P, TC9256F, TC9257P and TC9257F are phase-locked
loop (PLL) LSls for digital tuning systems (DTS) with built-
in 2 modulus prescalers.
All functions are controlled through 3 serial bus lines.
These LSIs are used to configure high-performance digital
tuning systems.
TC9256P
FEATURES
0 Optimal for configuring digital tuning systems in high-fi
tuners and car stereos.
o Built-in prescalers. Operate at input frequency ranging DIP16-P-300-2.54A
from 30~150MH2 during FMIN input (with 2 modulus TC9257P
prescaler) and at 0.5--40MHz during AMIN input (with 2
modulus prescaler or direct dividing).
o 16bit programmable counter, dual parallel output phase
comparator, crystal oscillator and reference counter.
o 3.6MHz, 4.5MHz, 7.2MH2 or 10.8MH2 crystal oscillators can
be used.
0 15 possible reference frequencies. (When using 4.5MHz
crystal) (Ref.=0.5k, 1k, 2.5k, 3k, 3.125k, 3.90625k, 5k,
6.25k, 7.8125k, 9k, 10k, 12.5k, 25k, 50k and 100kHz). DlP20-P-300-2.54A
o Built-in 20bit general-purpose counter for such uses as TC9256F
measuring intermediate frequencies (IFIN1 and IFIN2) and
low-frequency pilot signal cycles (SCIN). (Cycle
measurement function is not available on TC9256P and
TC9256F.)
0 High-precision (i0.55~ $7.15”) PLL phase error detection.
lt Numerous general-purpose I/O pins for such uses as
peripheral circuit control.
0 4 N-channel open-drain output ports (OFF withstanding
voltage : 12V) for such uses as control signal output. SOP16-P-300-1.27
(TC9256P and TC9256F have only 3 ports.) TC9257F
0 Standby mode function (turns off FM, AM and IF amps) to
save current consumption.
0 All functions controlled through 3 serial bus lines.
o CMOS structure with operating power supply range of
1/DD=5.0h0.5V. .
Ct 16pin DIP (TC9256P), 1vt/tur2.54, : 1.0g (Typ.)
20pin DIP (TC9257P), DlP20-P-300-2.54A : 1.24g (Typ.)
16pin SOP (TC9256F) SOP16-P-300-1.27 : 0.16g (Typ.
20pin SOP (TC9257P) SOP20-P-300-1.27 : 0.48g (Typ.)
packages. SOP20-P-300-1.27
1 2001-06-19
TOSHIBA
TC9256,57P/F
PIN CONNECTION
TC9256P, TC9256F
XT[1 V 16 JDO2/OT-4
El: 2 15 EIDo1
PERIOD[ 3 14 Ji/o-s/_
CLOCKI: 4 13 [ll/O-S/IFINZ
DATA[ 5 12 [IGND
OT-lt 6 11 [IFMW
OT-2t 7 10 CIA'VHN
or-at 8 9 UVDD
Top View
DlP-16PlN/SOP-16PIN
BLOCK DIAGRAM
TC9257P, TC9257F
xrt 1 V 20 [11302
'rrt 2 19 [1001
PERIOD[ 3 18 F/o-7/sce:
CLOCKI 4 17EII/o-8/1FIN1
DATA[ 5 16 r/o-9/mN2
OT-l t 6 15 [IGND
or-at 7 14 EIFMIN
or-at 8 13 JAiutN
or-ot 9 12 [Ivan
|/O-5/CLK[10 11 [11/06
Top View
DIP-20PlN ISOP-ZOPIN
Ja? GND
FML PSC T
FM C 2 MODULUS 4bit SWALLOW POWER ON
IN 1/2 PRESCALER COUNTER RESET 1
FMH HF ir RESET
AMIN )-t> 12bit PROGRAMMABLE COUNTER g TRI-STATE y DOI
FM MODE LF w t BUFFER
s, 12 2 n:
- 4 _ I g
XT OSC th. E
REFERENCE COUNTER MAX - 8 TRI-STATE -l) DO2
CIRCUIT BUFFER
XT I 15 , (D02 /OT-4)
lms OSC 4t, l
- 24bit REGISTER UNLOCK
t Ct: -! I/O-S/CLK
DATA 24bit SHIFT REGISTER "sis", ii
- t I/O-6
CLOCK A f a 8 l l? fiizzz: "it
TEST 5 I
ADDRESS 24 22 "" -
DECODER /
PERIOD a)—' 10 s I—
24bit REGISTER l/0-9/lFiN2
\l (IIO-6/IFIN2)
4 "tf 4 tf"A1 AMP
"s, 20bit BINARY COUNTER c >4 l/O-B/lFlm
\l (l/O-5/lFIN1)
OUTPUT PORT N GATE W AMP
UNIVERSAL COUNTER CONTROL
o/c 1/0-7/5C.N
- OT-4 I T
l K XT 1ms
OT-1 OT-3
OT-2 OT-a
(Note)O Mark terminals are not existence in TC9256P, TC9256F.
Terminal name of TC9256P, TC9256F is shown in parentheses.
Others are common terminals.
2 2001 -06-1 9
TOSHIBA
TC9256,57P/F
PIN FUNCTION
KILL“ SYMBOL PIN NAME FUNCTION CIRCUIT DIAGRAM
1 XT Connects 3.6MHz, 4.5MH2, -Nvv-
Crystal oscillator pins "Plz or 10.8MHz crystal --( VDD --
2 W oscillator to supply reference
frequency and internal clock. XTo CW
3 PERIOD Period signal input Serial l/O ports. These pins
transfer data to and from the VDD F
4 CLOCK Cl k . I . t controller to set divisors and " ' O .iit c:
oc Slgna mpu dividing modes, and to control :23“ Schmittinput
5 DATA Serial data input/ the general-purpose counter and DATA CLOCK, PERIOD
output general-purpose I/O ports.
6 OT-l N channel open drain port pins,
for such uses as control signal
7 OT-2 output.
General-purpose These pins are set to the OFF i
8 OT-3 output ports state when power is turned on. N-channel open drain
(On TC9256P and TC9256F, OT-4
9 OT 4 can be used as a CMOS output
(-) - pin by switching it with D02.)
CMOS structure allows free use of
10 l/O-5/ these ports for input or output. Von
(-) CLK General- ur ose I/O Ports are set for input when the F-
orts p p power is turned on. On TC9257P
11 p and TC9257F, I/O-5 can be "
(-) l/O-6 switched for use as a system clock
output pin.
13 AMIN These pins input FM and AM VDD
(10) Programmable band local oscillator signals by o-li -
14 counter input capacitor coupling. FMIN and "
(11) FMIN AMIN operate at low amplitude. E
2001 -06-1 9
TC9256,57P/F
2f SYMBOL PIN NAME FUNCTION CIRCUIT DIAGRAM
General-purpose I/O port input/
output pins. Can be switched for
use as input pins to measure
(16) l/O-9(-6) general-purpose counter
13 /IF .
IN2 General-purpose I/O frequencies. The frequency V
orts measurement function has such DD "
p /General- ur ose uses as measuring intermediate { -
p p frequencies (IF). "
counter frequency . . .
measurement These pins feature built-in amps. .
in ut Data are input by capacitor E.-
17 I/O-8(-5) p coupling. FMIN and AMIN operate
(14) /IFIN1 at low amplitude.
(Note) Pins are set for input
when power is turned
General-purpose I/O port input/
output pin. Can be switched for
t',tral purpose l/O use as signal input pin to VDD
measure Iow-frequency signal F
(1_8) ”0;; ifjgtegralc-pctigpose cycles. (Not available on TC9256P ‘1:
IN rc,','eual",Tuerrdyecr',et and TC9256F.)
in ut (Note) This pin is set for input
p when power is turned
These pins are for phase
DOI comparator tristate output.
(15) :hligitcomparator DOI and D02 are output in VDD "
parallel.
(General-purpose
20 DO2 out ut orts) (On TC9256P and TC9256F, D02 "
(16) (D02 p p can be switched for use as a
/OT-4) general-purpose output port.)
(12) GND
Power supply pins Applies S.OVi 10%. -
(9) DD
(*) Pin numbers 1~8 are common to TC9256P, TC9256P, TC9257P and TC9257F.
(*) Pin names and numbers in parentheses apply to TC9256P and TC9256P.
2001 -06-1 9
TOSHIBA
TC9256,57P/F
FUNCTIONS AND OPERATION
C) Serial I/O ports
As the block diagram shows, the functions of TC9256P, TC9256F, TC9257P and TC9257F are
controlled by setting data in the 48 bits contained in each of the 2 sets of 24bit registers. Each bit
of data in these registers is transferred through the serial ports between the controller and the
DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8 address bits
and 24 data bits.
Since all functions are controlled in units of registers, the explanation in this manual focuses on the
8bit addresses and functions of each register.
These registers consist of 24 bits and are selected by an 8bit address.
A list of the address assignment for each register is given below under Register assignments.
REGISTER ADDRESS CONTENTS OF 24 BITS No. OF BITS
PLL divisor setting 16
Input Reference frequency setting 4
Register 1 DOH PLL input and mode setting 2
Crystal oscillator selection 2
Total 24
General-purpose counter control 4
(including lock detection bit control)
l/O port and general-purpose counter switching bits 3
I/O-5/CLK pin switching bit 1
Input (DO2/OT-4 pin switching bit for TC9256P and TC9256F)
Register 2 D2H DO pin control 1
Test bit 1
I/O port control 5
(also used as general-purpose counter input selection bits)
Output data 9
Total 24
General-purpose counter numeric data 22
Jgueeu,t 1 D1H Not used 2
Total 24
Lock detection data 5
I/O port control data 5
Output D3H Output data 4
Register 2 Input data (undefined during output port selection) 5
Not used 5
Total 24
When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the
function is performed.
When the CLOCK signal falls for the 9 time, the output data are latched in parallel in the output
registers. The data are subsequently output serially from the data pin.
2001 -06-1 9
TOSHIBA
TC9256,57P/F
REGISTER ASSIGNMENTS
Address = DOH
.,, LSB I I I I MSB I
l,", P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R0 R1 R2 R3 FM MODEOSC1OSC2
1. Programmable counter data Reference
Programmable Crystal
t,' Address=D2H frzquzniy counter oscillator
fy co e a a mode selection bits
- (*3) (*5) l— (*3) -] - (*3) -l
SC CLK C5 C6 M7 M8 M9 O5 O6 O7 O8 09
GO G1 (*1) IF1 " (o4c)DOHZRESET5TART TEST (XT) (*1) (*1) (M5) (M6) Ol 02 O3 O4 (*1) (*1) (*1) (05) (06)
l-aaa,-A-ao port ' CLIK RESET TIES: 'ctt,citd as Output port output data
time and general-purpose purpose.
_ _ _ DOHZ START counter In ut
select counter switching bits bit bit selection bats
IIO port control
Address=D1H
t', f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 fll f12 f13 f14 f15 f16 f17 f18 f19 OVER BUSY "0" "O"
, \ General-purpose counter data A- Not _/
+1 used
a Address=D3H
+I * *
3 _ 3% _ Na
ENA- UN " " " " " " " " " " C5 C6 M7 M8 M9 I5 I6 l7 l8 s
BLE LOCK PE1 PE2 PE3 0 0 0 0 0 (*2) (*2) (*2) (M5) (M6) Ol 02 03 O4 (*2) (*2) (*2) (Is) (16)
l-cock detection data -A-vat used-A-, port control data -A-output data -A-nput data _1
When power is turned on, the input registers are set as shown below.
Address=DOH
m LSB I I I I MSB|
13 (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) (*4) 1 1 1 1 1 1 0 0
(i Address=D2H
0 0 0 0 0 0 0 O 0 0 0 0 0 O 0 0 0 0 O 0 0 0 0 0
(Notes) (*1) Cannot be set on TC9256P and TC9256F.
(*2) These data are "o" on TC9256P and TC9256F.
(*3) Bit names in parentheses "( )" refer to TC9256P and TC9256F.
(*4) Data are undefined.
(*5) Set data to "o" for TEST bit.
6 2001-06-19
TOSHIBA TC9256,57P/F
CD Serial transfer format
The serial transfer format consists of 8 address bits and 24 data bits (Fig.1). Addresses DOH~D3H
are used.
Start End
PERIOD t3 t4 t5
9 I k . If II
:/ coc sugna a
CLOCK I l l l
* 0 0 0
) l 1 1
W. I MSB V. 7 --- & y
I-- 8 address bits -I-- 24 data bits -I
(24bit register)
It Serial data transfer
Serial data are transferred in sync with the clock signal. In the idlestate, the PERIOD, CLOCK
and DATA pin lines are all set to "H" level. When the period signal is at "L" level, the falling
of the clock signal initiates serial data transfer. Data transfer ceases when the period signal is
set to "L" level when the clock signal is at "H" level. Once serial data transfer has begun,
however, no more than 8 falls of the clock signal can occur during the time the period signal
is at "L" level.
Since the receiving side receives the serial data as valid data when the clock signal rises, it is
effective for the sending side to produce output in sync with the clock signal fall.
To receive serial data from the output registers (D1H, D3H), set the serial data output to high
impedance after the 8bit address is output but before the next clock signal falls.
Data reception subsequently continues until the period signal becomes "L" level ; data transfer
ends just before the period signal rises. Therefore, the data pin must have an open-drain or
tristate interface.
(Note 1) When power is turned on, some internal circuits have undefined states.
To set internal circuit states, execute a dummy data transfer before performing
regular data transfer.
(Note 2) Times tl--t8 have the following values.
tr21.0ps
t2; 1.0ps
t320.3ps
t4; 0.3ps
tra0.3ps
t6; 1.0ps
t721.0ps
t8; 0.3ps
(Note 3) Asterisks represent numbers taken from addresses, as in D*H.
7 2001-06-19
TOSHIBA TC9256,57P/F
0 Crystal oscillator pins (XT, W)
As Fig.2 shows, the clock necessary for internal operation is produced by connecting a crystal
oscillator between capacitors. Use the crystal oscillator selection bit to select an oscillating
frequency of 3.6MHz, 4.5MHz, 7.2MHz or 10.8MH2 which matches that of the crystal oscillator
LSB MSB
Address DOH OSC1 OSC2
OSCILLATOR
OSC1 OSC2 FREQUENCY
0 0 3.6MH2
1 4.5MHz
0 1 7.2MHz
1 1 10.8MHZ
-ly--lDivi=der]
Cl X'tal J' C=30pFTyp.
(Note) Set to 3.6MHz (OSC1="0" and OSC2="0") when power is turned on.
The crystal is not oscillating at this time because the system is in standby mode.
8 2001-06-19
TOSHIBA TC9256,57P/F
CD Reference counter (Reference frequency divider)
The reference counter section consists of a crystal oscillator and a counter.
A crystal oscillator frequency of 3.6MHz, 4.5MHz, 7.2MH2 or 10.8MHz can be selected. A maximum
of 15 reference frequencies can be generated.
1. Setting reference frequency
The reference frequency is set using bits RO--R3.
Address DOH R0 R1 R2 R3
l l 1 I
R0 R1 R2 R3 FRREEFCEEENEE/ R0 R1 R2 R3 FRREEFCEEENg
o o o o 0.5 kHz 0 o o 1 *7.8125 kHz
1 o o o 1 kHz 1 o o 1 9 kHz
0 1 o 0 2.5 kHz 0 1 o 1 10 kHz
1 1 o o 3 kHz 1 1 o 1 12.5 kHz
0 o 1 o 3.125 kHz 0 o 1 1 25 kHz
1 o 1 0 *3.90625 kHz 1 o 1 1 50 kHz
0 1 1 o 5 kHz 0 1 1 1 100 kHz
1 1 1 0 6.25 kHz 1 1 1 1 Standby mode (*1)
(Note 1)
(Note 2)
(Note 3)
Reference frequencies marked with an asterisk
4.5MH2 crystal oscillator.
can only be generated with a
(*1) Standby mode
Standby mode occurs when bits R0, R1, R2 and R3 are all set to "I". ln standby
mode, the programmable counter stops, and FM, AM and IFIN (when selected
IFIN) are set to "amp off" state (pins at "L" level). This saves current
consumption when the radio is turned off. The DO pins become high impedance
during standby mode.
During standby mode, the HO ports (|/O-5~|/O-9) and output ports (OT1~OT4)
can be controlled and the crystal oscillator can be turned on and off.
The system is set to standby mode when power is turned on. At this time, the
crystal oscillator is not oscillating and the HO ports are set to input mode.
9 2001-06-19
TOSHIBA TC9256,57P/F
C) Programmable counter
The programmable counter section consists of a 1/2 prescaler, a 2 modulus prescaler and a
4bit+ 12bit programmable binary counter.
1. Setting programmable counter
16 bits of divisor data and 2 bits which indicate the dividing mode are set in the
programmable counter.
(1) Setting dividing mode
The FM and MODE bits are used to select the input pin and the dividing mode (pulse
swallow mode or direct dividing mode). There are 4 possible choices, shown in the table
below. Select one based on the frequency band used.
LSB MSB
Address DOH FM MODE
TYPICAL INPUT FREQUENCY INPUT
MODE FM MODE DIVIDING MODE RECEIVING BAND RANGE PIN FREQUENCY
LF 0 0 Direct dividing mode LW, MW, SWL 0.5-- 20 MHz AM
HF o 1 SWH l-- 40MHz IN n
Pulse swallow mode 30--130 MHz
FML 1 0 FM 30~150MH2 FMIN
1/2 +pulse swallow
FMH 1 1 mode FM 30 130MHz 2-n
(2) Setting divisor
The divisor for the programmable counter is set as binary data in bits P0~P15.
It Pulse swallow mode (16 bits)
LSB MSB
Address DOH P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11P12 P13 P14 P15
20 215
Divisor setting range (pulse swallow mode) : n =210H--FFFFH (528--65535)
(Note) With the 1/2 +pulse swallow mode, the actual divisor is twice the programmed
value.
0 Direct dividing mode (12 bits)
LSB MSB
Address DOH P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11P12 P13 P14 P15
N-cron, care ' 20 211
Divisor setting range (direct dividing mode) : n=10H~FFFH (16~4095)
With the direct dividing mode, data P0~P3 are don't-care and bit P4 is the LSB.
10 2001-06-19
TOSHIBA TC9256,57P/F
2. Prescaler and programmable counter circuit configuration
(1) Pulse swallow mode circuit configuration
PSC Fi 3
4bit swallow counter
FMIN 2 modulus
prescaler
To phase
comparator
12bit programmable counter
P4~P15
Prescaler section
This circuit consists of a 2 modulus prescaler, a 4bit swallow counter and a 12bit
programmable counter. During FMIN (FMH mode), a 1/2 prescaler is added to the preceding
(2) Direct dividing method circuit configuration
Preset
AMlN . 12bit programmable counter
" To phase comparator
P4~P15
With the direct dividing mode, the prescaler section is bypassed and the 12bit
programmable counter is used.
(3) Both FMIN and AMIN have built-in amps. Data are input by capacitor coupling. FMIN and
AMIN operate at low amplitude.
11 2001-06-19
TOSHIBA TC9256,57P/F
O General-purpose counter
The general-purpose counter is a 20bit counter. It has such uses as counting AM/FM band
intermediate frequencies (IF) and detecting auto-stop signals during auto-search tuning. It also
features a cycle measurement function for such uses as measuring Iow-frequency pilot signal cycles.
TC9256P and TC9256F do not have the cycle measurement function (SCIN mode). General-purpose
counter pins can also be used as I/O ports.
l. General-purpose counter control bits
(1) Bits GO and G1 ..... Used for selecting the general-purpose counter gate time.
LSB MSB
Address D2H GO G1
CYCLE MEASUREMENT
GO G1 GATE TIME PULSE
0 0 1ms 50 kHz
1 O 4ms 150 kHz
0 1 16ms 900 kHz
1 1 64ms Crystal oscillator frequency
(2) Bits SC, fl and Til ..... I/O port and general-purpose counter switching bits.
(*) The functions of the following pins are switched by data.
LSB MSB
Address D2H (i?) TI |F2
SC |/O-7/SC l/O-8/IFIN1 I/O-9/IFIN2
(*1) (*1) IN IF1 (l/O-5/IFiijj) IF2 (l/O-6/lFii(d)
1 SCIN 1 IFIN1 1 IFINZ
0 I/O-7 0 I/O-8(l/O-5) 0 |/O-9(I/O-6)
(Note 1) Pin names in parentheses "( )" apply to TC9256P and TC9256F.
(Note 2) Bits marked with (*1) cannot be set on TC9256P and TC9256F.
12 2001-06-19
TOSHIBA TC9256,57P/F
(3) Bits M7, M8 and M9-. M7 (*1) sets the state for pin l/O-7/SCIN, M8 (M5) sets the state
for pin l/O-8/IFIN1 ; M9 (M6), for pin l/O-9/IFIN2.
These operations are valid when bits SC, TI and IF2 are all set to 1.
LSB MSB
Address D2H (“1:17) (ml?) Jil
l l i l
M7 M8 M9 PIN STATES (When bits sc, TI and IF2 are all set to "1")
(*1) (M5) (M6) SCIN IFIN1 IFINZ
0 0 0 Input pulled down
(*) (*) 1 Input disabled Input pulled down Input enabled
(*) 1 0 Input enabled
1 0 0 Input enabled Input pulled down Input pulled down
(Note 1) Bits marked with an asterisk "(*)" are don't-care.
(Note 2) Bit names in parentheses "( )" apply to TC9256P and TC9256F.
(Note 3) Bits marked with (*1) cannot be set on TC9256P and TC9256F.
(4) Bits f0--f19-.The general-purpose counter results can be read in binary from bits fo--f19 of
the output register (D1H).
LSB MSB
Address D1H f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 fll f12 f13 f14 f15 f16 f17 f18 f19 OVER BUSY "O" "o"
20 219
General-purpose counter data
(5)0VER and BUSY bits... Detect the operating state of the general-purpose counter.
Address D1H MSB
OVER BUSY "0" "O"
BIT DATA = "1" BIT DATA = "0"
General-purpose counter General-purpose counter General-purpose counter
operation monitor bit busy ended counting
Counted value in general- .
Counted value in general-
General-purpose counter
overflow detection bit
purpose counter; 220
r ose co nters220-1
(Overflow state) pu p u
(Note) When using the general-purpose counter, before referring to the contents of
the general-purpose counter result bits (ftr-f19), confirm that the BUSY bit is
"o" (counting is ended) and the OVER bit is "o" (general-purpose counter data
are normal).
(6) START bit-When the data are set to "I", the general-purpose counter is reset then
counting begins.
LSB MSB
Address D2H START
0 Counting continues uninterrupted.
1 Counting begins after general-purpose counter is reset.
13 2001-06-19
TOSHIBA TC9256,57P/F
2. General-purpose counter circuit configuration
The general-purpose counter section consists of input amps, a gate time control circuit and a
20bit binary counter.
fo-f19 OVER
|FIN1 . ' i I
' T', I 20bit binary counter IOverrow detection I
IFIN2 .
(CMOS input)
START GO G1 BUSY
3. General-purpose counter measurement timing
End End
PERIOD I PERIOD I
T1 - T1 "
START bit set to "l" START bit set to "l"
IFIN1 or SCIN
IFIN2 - - -
BUSY BUSY
bit - bit - ‘—
44-? I
Gate Gate
Binary Binary
counter l counter
input input
Clock pulse to be measured Reference clock pulse
Frequency measurement timing chart Cycle measurement timing chart
0
(Note 1) IFIN1 and IFIN2 input have built-in amps. Data are input by capacitor coupling. FMIN
and AMIN operate at low amplitude.
(Note 2) SCIN is configured for CMOS input, so input signals should be logic level.
14 2001-06-19
TOSHIBA
O General-purpose l/O ports
TC9256,57P/F
These LSIs feature general-purpose output and I/O ports which are controlled through the serial
ports.
INPUT/
OUTPUT FORM TC9256P, TC9256F
TC9257F, TC9257F
INPUT/OUTPUT
CONFIGURATION
Dedicated : 3 ports
Output ports Maximum : 4 ports (1 port for Dedicated : 4 ports
CMOS output)
N channel open-drain
output
I/O ports Maximum : 2 ports
Dedicated : 1 port,
Maximum : 5 ports
CMOS input/output
General-purpose output ports (OT-I-OT-il)
Pins OT-1--OT-4 are general-purpose dedicated output ports. They have such uses as control
signal output. They are configured for N channel open-drain output and have an off
withstanding voltage of 12V.
The data set in bits OI-HM of the input register (D2H) are output in parallel from their
corresponding dedicated output port pins OT-1~OT-4. TC9256P and TC9256F do not have
dedicated output port OT-4, but setting the input register (D2H) CLK (04C) bit to "I" converts
pin D02 into output port OT-4 (configured
for CMOS output).
The data set in bits O1--04 of the input register (D2H) can also be read from the DATA pins
as output register (D3H) serial data O1--04.
(1) TC9257F and TC9257F
Address D2H
PIN OUTPUT STATE
OT-1 --OT-4
High impedance
(N channel open drain output=off)
"L" level
(N channel open drain output=on)
2001 -06-1 9
TOSHIBA TC9256,57P/F
(2) TC9256P and TC9256F
LSB MSB
Address D2H (8:2) Ol 02 03 04
PIN OUTPUT STATE
04C DO2/OT-4PIN O1--04 OT-1--OT-3 OT-4 (*1)
0 D02 0 High impedance "L" level
(phase comparator output) (N channel open drain output=off) (*1)
1 OT-4 1 "L" level "H" level
(general-purpose output port) (N channel open drain output=on) (*1)
(Note 1) Bit names in parentheses "( )" apply to TC9256P and TC9256F.
(Note 2) (*1) indicates the output state when DOZ/OT-4 pin is switched for use as OT-
4 output pin (configured for CMOS output).
(3) Output register-The data set in bits O1--04 of the input register can be read as serial
data O1--04 from the output register (D3H).
LSB MSB
Address D2H O1 02 O3 04 n
register
LSB MSB
Address D3H O1 02 O3 04
Output
register
16 2001-06-19
TOSHIBA TC9256,57P/F
2. General-purpose I/O ports (|/O-5~|/O-9)
Pins |/O-5~|/O-9 are general-purpose I/O ports used for control signal input and output. They
are configured for CMOS input and output.
These I/O ports are set for input or output using bits C5, C6 and M7~M9 of the input register
(D2H).
Setting bits C5, C6 and M7~M9 to "o" sets these ports for input. Data which are input in
parallel from |/O-5~|/0-9 are latched in the internal register on the ninth fall of the serial
clock signal. These data can then be read as serial data lr-l9 from the DATA pins.
Setting bits C5, C6 and M7~M9 to "l" sets these ports for output.
Data which are set in bits 05~09 of the input register (D2H) are output in parallel from their
corresponding general-purpose I/O port pins |/O-5~|/O-9.
These operations are valid when bits SC, fl, IF2 and CLK are all set to "o".
(1) TC9257F and TC9257F
LSB MSB
dd 2 SC IF1 IF2 CLK C5 C6 M7 M8 M9
A ress D H "o" " " "O'' "O'' (XT) Cl) (*1) (M5)(M6)
C5, C6, PIN INPUT/OUTPUT STATE (When SC, IF1 and IF2 are "o'')
M7--M9 |/O-5~|/O-9
0 Input port
1 Output port
0 Setting data for output ports
LSB MSB
SC IF1 IF2 CLK C5 g6 w, M8 M9 05 06 O7 08 O9
Address D2H "0" "0" "0" "0" (ho ("11") (~11) W1?!) (M9 (05) (06)
l l l l l
05 09 PIN OUTPUT STATE (When SC, IF1 and IF2 are "o")
|/O-5~|/O-9
0 "L'' level
1 "H" level
(Note 1) On TC9257F and TC9257F, pins |/O-7~|/O-9 also serve as general-purpose counter
input pins. Therefore, bits SC, IF1 and IF2 of the input register (D2H) must be set
to "0" when pins |/O-7~|/O-9 are used for l/O ports. Since pin l/O-5 also serves
as the CLK pin, the CLK bit of the input register (D2H) must be set to "o" when
pin I/O-5 is used as an I/O port.
(Note 2) Bit names in parentheses "( )" apply to TC9256P and TC9256P.
(Note 3) Bits marked with (*1) cannot be set on TC9256P and TC9256F.
17 2001-06-19
TOSHIBA TC9256,57P/F
(2)TC9256P and TC9256F
LSB MSB
TI IF2 M8 M9
Address D2H "o" "0" "/"f')
M5 M6 PIN INPUT/OUTPUT STATE (When fl and T2 are "o")
' l/O-S, I/O-6
0 Input port
1 Output port
0 Setting data for output ports
LSB MSB
TI IF2 M8 M9 08 09
Address D2H "O" "0" (M?) (Mg) (05) (O6)
O5 O6 PIN OUTPUT STATE (When IF1 and IF2 are "0")
' I/O-S, l/O-6
0 "L'' level
1 "H" level
(3) Output register- Data which are set in bits C5, C6 and M7--M9 of the input register (D2H)
can be read as serial data C5, C6 and M7--M9 from the output register
(D3H).
LSB MSB
C5 C6 M7 M8 M9
(XT) (*1) (*1) (M5)(M6)
LSB l l 1
C5 C6 M7 M8 M9
(*2) (*2) (*2) (M5) (M6)
Address D2H - Input register
Address D3H - Output register
Data which are input in parallel from pins |/O-5~|/O-9 can be read as serial data Ir-l9 from
the output register (D3H).
LSB MSB
IS l6 l7 I8 I9
(*2) (*2) (*2) (I5) (I6)
Address D3H - Input register
/ / 1 N N
d/O-S l/O-6 |/O-7 l/O-il IIO-9,
Input data
INPUT PORTS BIT DATA
(|/O-5~|/O-9) (lr-S)
"L'' level 0
"H" level 1
(Note 1) Bit names in parentheses "( J" apply to TC9256F and TC9256F.
(Note 2) Bits marked with (*1) cannot be set on TC9256F and TC9256F.
Data are "0" for bits marked with (*2) on TC9256P and TC9256F.
2001 -06-1 9
TOSHIBA
TC9256,57P/F
(Note 3) When pins |/O-5~|/O-9 are used for output, the data in l5--19 of the output
register (D3H) are undefined.
(Note 4)
M7~M9 and output data bits 05~09 are set to "o".
(General-purpose I/O ports are set as input ports. Pins which are used both as
general-purpose I/O ports and for general-purpose counter input are set for I/O
port input. The output state of general-purpose output ports is set to high
impedance (N channel open drain output=off).
(Note 5)
When power is turned on, input register (D2H) I/O port control bits C5, C6 and
On TC9256P and TC9256F, pins I/O-5 and l/O-6 also serve as general-purpose
counter input pins. Therefore, bits fl and IF2 of input register 2 must be set to
"o" when these pins are used as I/O ports.
A typical example of data setting for general-purpose counter and I/O port use is shown
below.
0 TC9257P and TC9257F
Address D2H
M7 M8 M
"I" "I" "o
#1? i]
PIN NAME I/O-7/SCIN I/O-8/IFIN1 I/O-9/IFIN2
Pin function I/O-7 IFIN'I IFINZ
Pin input/ Input Input pulled
output state Output port enabled down
As shown above, the pins can be switched as necessary to enable use as an I/O port or
general-purpose counter.
2001 -06-1 9
TOSHIBA
TC9256,57P/F
C) Phase comparator
The phase comparator outputs the phase error after comparing the phase difference of the
reference frequency signal supplied by the reference counter and the divided output from the
programmable counter. The frequencies and phase differences of these two signals are then
equalized by passing them through Iow-pass filters. These signals then control the VCOs.
The filter constants can be customized for FM and AM bands since the signals are output in parallel
from the phase comparator then pass through the two tristate buffer pins, DOI and D02.
Reference frequency signal
Programmable s
counter output
comparator
s irl Fl I I
I I li li
I I II II
Do _.I i-----''---""
"st' Low level Floating
High level
DO Output Timing Chart
-. D02
DOI . u. FM
. T VCO
. = AM
R2 c ' RL
- To VCO varactor diode
Tr2 Typical low-pass filter constants
(FM band reference values)
C--ih33pzF
RI--10kn
Standard R2 = 8.2kQ
Trl , 25C1815 R3=330Q
Tr2 : 2SK246 RL=10k0
Typical Active Low-Pass Filter Circuit
The figures above show the DO output timing chart and a typical active Iow-pass filter circuit
featuring a Darlington connection between the FET and transistor.
The filter circuit shown above is just one example. Actual circuits should be designed based on the
band composition and the properties desired from the system.
(Note) On TC9256P and TC9256F, pin D02 can be switched for use as pin OT-4.
2001 -06-1 9
TOSHIBA TC9256,57P/F
C) Lock detection bits
The lock detection bits detect locked states in the PLL system. These systems have an unlock
detection bit (unlock bit) which is used to detect, using the reference frequency cycle, the phase
difference between the reference frequency and the divided output of the programmable counter.
These systems also have phase error detection bits (bits PE1--PE3), which are capable of more
precise detection "0.55ps-- i7.15,us).
Unlock detection bit (UNLOCK)
This bit detects, using the reference frequency cycle, the phase difference between the reference
frequency and the divided output of the programmable counter. When there is no lock, that is,
when the reference frequency and the divided output of the programmable counter are not the
same, unlock F/F is set.
Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to "I".
After unlock F/F has been reset in this way, locked state can be detected by checking the
unlock detection bit (UNLOCK) of the output register (D3H). After unlock F/F has been reset,
the unlock detection bit must be checked after a time interval exceeding that of the reference
frequency cycle has elapsed. This is because the reference frequency cycle inputs the lock
detection strobe to unlock F/F. If the time interval is short, the correct locked state cannot be
detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is reset
every time the input register (D2H) reset bit is set to "I", and set to "I" through the lock
detection timing. That is, the locked state is correctly detected when the lock enable bit
(ENABLE) is "1".
Reference frequency J I
Programmable I I I I I I I I I I
counter output
I I "H" level
DOoutput ..I I..I I..I i-li'""'""" .. I I ..... -
L" level
Phase comparator I I I i I I I I I
Lock detection strobe th (k I
Unlock is reset l
(RESET) A n A. A
Unlock F/F ,' I
(UNLOCK) . I I
Lock enable I LI LI LI
(ENABLE)
Phase error detection Aer" W AK? W
Counts phase difference.
Fig.10
21 2001-06-19
TOSHIBA TC9256,57P/F
LSB MSB
Address D2H RESET - Input register
I i- Setting data to "I" resets unlock detection bit and lock enable bit.
LSB MSB
ENA- UN - O t t . t
Address D3H BLE LOCK u pu regis er
1 PLL lock detection enabled 1 PLL in unlocked state (*)
0 PLL lock detection in 0 PLL in locked state
waiting state
(Note) The asterisk "(*)" indicates an error state of over 180° phase difference relative to
the reference frequency.
2. Phase error detection bits (PE1--PE3)
The unlock bit detects, using the reference frequency cycle, the phase difference between the
reference frequency and the divided output of the programmable counter. The phase error
detection bits (bits PE1~PE3) are capable of precise phase error detection of 10.55-- i7.15,us
using the reference frequency cycle. (If the UNLOCK bit is set to "I" and the phase difference
relative to the reference frequency is over 180°, bits PE1--PE3 cannot correctly detect the phase
error. Therefore, bits PE1--PE3 are normally used when the UNLOCK bit is set to "0".) Bits
PE1--PE3 detect phase error normally when the phase difference is - 180°~180° relative to the
reference frequency cycle.
LSB MSB
Address D3H PE1 PE? PE3 - Output register
PE1 PE2 PE3 PHASE ERROR (PE)
PE< $055,115
L'th55pss PE< 11.65/15
, 1.65pss PE< $2.75/15
i2.75,us§ PE< 13.85ps
i3.85,us§ PE< $4.95ys
14.95ysé PE< $6.05ys
i6.05/¢S§ PE< $7.15/15
*7.15pss PE
_‘_|_l_|o°oo
_._\oo—I—\OO
AO—‘O—‘O—‘O
The phase error data can be read from the output register (D3H) as serial data PE1--PE3.
22 2001-06-19
TOSHIBA TC9256,57P/F
Following is a typical lock detection operation. It shows the operation flow from locked state to
frequency change with a phase error greater than *4.95ps and less than *6.05ps.
Frequency change
Phase error detection
Reset bite-I
Time interval exceeding that of
reference frequency cycle
NO (UNLOCK)
UNLOCK bit=0 ?
YES (LOCK)
Check phase error
detection bits PE1, PE2
and PE3
PE1=1, PE2=O, PE3=1 ?
Phase error=greater than i4.95;zs and
less than ur6.05ps
Fig.11
23 2001-06-19
TOSHIBA TC9256,57P/F
C) Other control bits
1. CLK(O4C) and C5(XT) bits-. Control bits which switch the function for the I/O-5/CLK pin on
TC9257P and TC9257F and the OT-4/D02 pin on TC9256P and
TC9256F.
(1) On TC9257P and TC9257F, the CLK bit controls switching of the |/O-5 pin and CLK pin.
0 When bits RO--R3 of the input register (DOH) are all set to "I'' (standby mode)
Address D2H (8:?) Ji
- CRYSTAL OSCILLATOR
CLK C5 I/O 5/CLK PIN STATE CIRCUIT STATE
0 0 Input port . . .
0 1 HO port Output port Oscillator circuit off
1 0 System clock off
CLK output (CLK at "L" level) Oscillator circuit on
1 1 System clock output (*)
0 When one of bits R0~R3 of the input register (DOH) is set to "o" (not standby mode)
Address D2H (82:) (ii)
- CRYSTAL OSCILLATOR
CLK C5 I/O 5/CLK PIN STATE CIRCUIT STATE
0 0 Input port
0 1 l/O port Output port . . .
1 0 Oscillator circuit on
1 1 CLK output System clock output (*)
(Note 1) The system clock output marked with an asterisk "(*)" refers to output of the
crystal oscillator frequencies listed below.
CRYSTAL OSCI LLATOR SYSTEM CLOCK DUTY
(MHz) (kHz) (%)
7.2 600
3.6 50
4.5 750
(Note 2) Bit names in parentheses "( J'' apply to TC9256P and TC9256F.
24 2001-06-19
TOSHIBA
TC9256,57P/F
(2) On TC9256P and TC9256F, the 04C bit controls switching of the D02 pin and OT-4 pin.
0 When bits RO~R3 of the input register (DOH) are all set to "I" (standby mode)
LSB MSB
Address D2H g-li, Ji',
CRYSTAL OSCILLATOR
04C XT DO2/OT-4 PIN STATE CIRCUIT STATE
0 0 D02 t t Oscillator circuit off
0 1 ou pu Oscillator circuit on
1 0 OT 4 t t Oscillator circuit off
1 1 - ou pu Oscillator circuit on
c When one of bits RO~R3 of the input register (DOH) is set to "0" (not standby mode)
LSB MSB
Address D2H (821.2) Ji
CRYSTAL OSCILLATOR
04C XT DO2/OT-4 PIN STATE CIRCUIT STATE
0 1 D02 output
1 0 Oscillator circuit on
1 1 OT-4 output
2. DOH2 bit-Controls the D02 pin output state.
LSB MSB
Address D2H DOHZ
0 D02 output in normal operation
(phase comparison error output)
1 D02 output fixed at high impedance
3. TEST bit-Data should normally be set to "o".
LSB MSB
Address D2H TEOSJ
(Note) Bit names in parentheses "( )" apply to TC9256P and TC9256F.
25 2001-06-19
TOSHIBA TC9256,57P/F
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.3--6.0 V
Input Voltage VIN -0.3--VDD+th3 V
N-ch Open-Drain OFF
Withstanding Voltage OFF 3
Power Dissipation PD 300 (200) mW
Operating Temperature Topr -40--85 "C ( ) : Flat Package
Storage Temperature Tstg -65--150 "C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = -40--85oC, 1/DD=4.r-5.5V)
CHARACTERISTIC SYMBOL CUR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Power PLL operation
Supply Voltage VDD1 - (Normal operating) 4.5 5.0 5.5 V
Operating Power VDD=5.0V, XT=10.8MHz,
Supply Current IDD1 - FlVhN=150MHz
- 7 15 mA
(Stand-by mode)
Crystal Oscillation PLL OFF
Frequency Supply VDD2 - (Operating crystal oscillation) 4.0 5.0 5.5 V
Voltage
Operating Power VDD=5.0V, XT=10.8MHz,
Supply Current IDD2 - PLL OFF - 0.8 1.5 mA
Operating Power IDD? - VDD=5.0V, XT stop, PLL OFF - 120 240 pA
Supply Current
(Operating frequency range)
Crystal Oscillation
Connect crystal resonator to
Frequency fXT - XT-WT terminal 3.6 -- 10.8 MHz
FMIN(FMH, FML) fFM - FMH, FML mode, V|N=0.2Vp_p 30 -- 130 MHz
FMIN (FML) fFML - FML mode, VIN = 0.3vp.p 30 ._ 150 MHz
AMIN (HF) fHF - HF mode, VIN =th2Vp-p 1 -- 40 MHz
AMIN (LF) fLF - LF mode, VIN = 0.2Vp_p 0.5 ._ 20 MHz
IFIN1, IFIN2 hi: - VIN=0-2Vp-p 0.1 ' 15 MHz
SCIN fSC - VIH = 0.7VDD, VIL = 0.3VDD, - ' 100 kHz
Square wave input
26 2001-06-19
TOSHIBA TC9256,57P/F
CHARACTERISTIC SYMBOL CUR- TEST CONDITION MIN. TYP. MAX. UNIT
(Operating input amplitude range)
- FMH, FML mode, -- VDD
FMIN(FMH, FML) VFM hN=30--130MHz 0.2 -0.5 Vp-p
FMIN (FML) VFML - FML mode, le =30--150MHz 0.3 ' "e, 5 Vp-p
AM VDD
IN (HF) VHF - HF mode, fIN =1~40MHZ 0.2 '..- - 0 5 Vp-p
AMIN (LF) VLF - LF mode, fIN =0.5--20MHz 0.2 ._ -0 5 Vp-p
IFIN1, IFINZ l/IF - hN=0.1--15MHz 0.2 ._ Ile, 5 Vp-p
(OT1~OT4 N-ch open drain)
Output " " - - -
Current L Level IOU VOL=1.0V 5.0 10.0 mA
OFF-Leak Current IOFF - VOFF = 12V - - 2.0 PA
(I /O-5--l /o-9, SCIN)
Input "H" Level VIH1 - 0.7VDD -- VDD V
Voltage "L" Level Wu 0 ._ 0.3VDD
Input "H" Level IIH VIH = 5V - - 2.0 A
Current "L" Level IIL - VIL=0V - - -2.0 /d
Output "H" Level IOH4 l/OH =4.0V (Expect SCIN) -2.0 -4.0 - mA
Current "L" Level IOL4 VOL= 1.0V (Expect SCIN) 2.0 4.0 -
(PERIOD, CLOCK, DATA)
Input "H" Level VIHZ - 0.8VDD ' VDD V
Voltage "L" Level V|L2 0 ~ 0.2VDD
Input "H" Level IIH VIH = 5V - - 2.0 A
Current "L" Level IIL VIL=01/ - - -2.0 /2
Output "H" Level IOH5 VOH = 4.0V (DATA) - 1.0 - 3.0 - mA
Current "L" Level IOL5 V0L=1.0V (DATA) 1.0 3.0 -
(D01, D02)
Input "H" Level loH3 VOH =4.0V -2.0 -4.0 - mA
Current "L" Level IOL? VOL=1.OV 2.0 4.0 -
Tri-State Lead Current ITL - VTLH = 5V, VTLL=0V - - i 1.0 pA
Output "H" Level IOHZ VOH =4.0V -0.1 -0.3 - mA
Current "L" Level 'OL2 VOL=1.0V 0.1 0.3 -
(Input feedback resistance)
Input Feedback Rf1 FMIN, AMIN, IFIN (Ta=25°C) 350 700 1400 k0
Resistance R12 XT-WT (Ta = 25°C) 500 1000 4000
27 2001-06-19
TOSHIBA
(mVrms)
INPUT LEVEL
(mVrms)
INPUT LEVEL
AMIN (LF) Frequency Characteristics
0.1 0.2 0.5 1 2 5 10 20 50 100
INPUT FREQUENCY (MHz)
(Note) 2fgfgf, Operating Gurantee Range
(VDD =4.5-5.5V, Ta = -40--85''C)
Standard Characteristics (VDD= 5V, Ta = 25°C)
AMIN (H F) Frequency Characteristics
0.1 0.2 0.5 1 2 5 10 20 4050100
INPUT FREQUENCY (MHz)
(Note) 'fdffp2 Operating Gurantee Range
(VDD = 4.5~5.5v, Ta = - 40~85°C)
Standard Characteristics (VDD = 5V, Ta = 25°C)
TC9256,57P/F
FMIN Frequency Characteristics
INPUT LEVEL (mVrms)
N u'I\l
0 20 40 60 80 100 120 140 160 180 200
INPUT FREQUENCY (M Hz)
(Note)
FMIN : FMH , Operating Gurantee Range
bb"ff44 FMIN : FML (VDD=4.5~5.5V, Ta= -40--85't0
Standard Characteristics (VDD = 5V, Ta = 25''C)
IFIN Frequency Characteristics
INPUT LEVEL (mvrms)
0.05 0.1 0.2 0.5 1 2 5
10 15 20 50
INPUT FREQUENCY (MHz)
(Note) (p'2?i4 Operating Gurantee Range
(VDD = 4.5--5.5V, Ta = - 40--85''C)
Standard Characteristics (VDD-- 5V, Ta = 25°C)
28 2001-06-19
TOSHIBA TC9256,57P/F
APPLICATION CIRCUIT
(Example for use TC9257P, TC9257F)
VCC SVtyp. _
. Varactor Diode
C V 1.
Micro- $-s 1 20 _" A. AM
C =, X'tal T VCO
Controller 34%|: 2 19
'wuorr--1 3 18
CLOCK —-—[ 4 17
I SCIN Signal
DATA 5 16 I AMIF Signal
6 15 FM Si I
t 0.001/1F IF 'gna
7 14 H + I 0.0'1',uF
s 13 [I "
9 12 il
_- 4.7PF 0.1pF
TC9257P, TC9257F 2/
IIO Port
12Vmax.
/ - utput Port
29 2001-06-19
TOSHIBA TC9256,57P/F
PACKAGE DIMENSIONS
DIP16-P-300-2.54A Unit : mm
[-1r'-'e1r-nF'--'1i-1l-1ei'-1
6.4:t0.2
V'-''-''''-'''-''
19.75MAX
19.25i0.2
03:51:01
0.735TYP . . i l 0.5i0.1_30'25 (ii)
Weight : 1.0g (Typ.)
30 2001-06-19
TOSHIBA TC9256,57P/F
PACKAGE DIMENSIONS
DlP20-P-300-2.54A Unit : mm
0—01 5°
Y'"---''--'''-'''''',-?
25.1 MAX
24.6:02 d
3.13:0.3
0.87TYP
Weight : 1.24g (Typ.)
31 2001-06-19
TOSHIBA
PACKAGE DIMENS
SOP16-P-300-
HHHHHHHH "
5 31:0 2
7.8i0.3
0.705TYP
10.8MAX
10.3:t0.2
tllllildtlleili,
l1 9MAX
Weight : 0.169 (Typ.)
o 15:02
tiitir'
TC9256,57P/F
Unit : mm
(3 00 mil)
0.15”-1
0.8i0.2
2001 -06-1 9
TOSHIBA
PACKAGE DIMENSIONS
SOP20-P-300-1.27
'ihiiripas/s1r------r--""
: 5.3:02
7 3:0 3
lrlhrlrleljljljrL___.._...a._,
0.685TYP =
13.3MAX
0.4 i0.1 *
Weight : 0.48g (Typ.)
ti?, E
tip-dr."
T"",, 1-
TC9256,57P/F
Unit : mm
(300mil)
(3-15—0255
-. I 0.23:0.2
2001 -06-1 9
TOSHIBA TC9256,57P/F
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
34 2001-06-19
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www.loq.com
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