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TC9246F-TC9246P
PLL IC FOR DIGITAL AUDIO
TOSHIBA TC9246F/P
CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9246F, TC9246P
PLL IC FOR DIGITAL AUDIO
TC9246F, TC9246P are a clock generating IC to generate TC9246F
master clock required for a system.
FEATURES
0 When reference clock is input, master clock required for
a system is generated.
o PLL circuit can be easily constructed by built-in VCO.
. . . . . . SOP16-P-300-1.27
o The built-in amplifier for external oscillator makes it
possible to select the master clock generation in an
external transmitter or that in the built-in VCO by the
operation of the microcomputer.
TC9246P
0 Detects PLL lock.
0 By serially connecting to the TC9245F, TC9245N (Digital
In), this IC is usable as a second PLL.
o CMOS silicon gate construction with low power DlP16-P-300-2.54A
dissipation. Weight
. . . SOP16-P-300-1.27 : 0.17g (Typ.)
0 2 kinds of package, 16pin MFP and 16pm DIP package. DIP16-P-300-2.54A : 1.11g (Typ.)
BLOCK DIAGRAM
LOCK DETECTION MICROCOMPUTER INTERFACE
CIRCUIT
PROGRAMMABLE COUNTER
REF COMPARATOR
1 2001-06-19
TOSHIBA TC9246F/P
PIN FUNCTION
Il). SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS
1 REF I Reference signal input terminal. -
2 PD o Phase error signal output terminal. 3-state output.
3 VDDA - Analog supply voltage terminal. -
4 AMPI I LPF gr oscillator 1 operational amplifier input -
terminal.
5 AMPO O LPF 9r oscillator 1 operational amplifier output -
terminal.
VSSA - Analog ground terminal. -
With feedback resistor.
7 XI I Oscillator 3 operational amplifier input terminal.
8 XO 0 Oscillator 3 operational amplifier output terminal.
9 vss - Digital ground terminal. -
10 CKO O Oscillated clock signal output terminal. -
11 M1 I Mode selection terminal. Schmitt input.
12 M2 I Mode selection terminal. With pulI-up resistor.
Parallel mode : division ratio selection terminal.
13 SI I . . . .
Serial mode : microcomputer data input terminal.
Parallel mode : division ratio selection terminal.
14 S2 I . . . . .
Serial mode : shift clock signal input terminal.
Open drain.
With pulI-up resistor.
15 LOCK o Lock detection signal output terminal.
16 VDD - Digital supply voltage terminal. -
2001 -06-1 9
TOSHIBA
DESCRIPTION OF OUTLINE
TC9246F, TC9246P are an IC developed for simple and second PLLs and for radiation suppression,
and to generate system clock signals for audio DSP.
In particular, the IC is well adapted to audio digital signal processing.
Described
below is the concrete operation of the IC.
l. Set operation modes and basic circuit configuration.
Table.1 Set inner operation modes
TC9246F/P
Table.2 Relation between CKO and REF
PLL mode where LC oscillator is used ;
APD L,,,,
J5)"; J
Fig.1 Sample basic PLL circuit-1
PLL mode where program counter is used ;
--- MCK
Walwligg
M2 M1 INNER OPERATION MODE S2 SI off-fir, J/ir, 1Nl/ER
PLL mode where LC oscillator is L L 768fs
L L fs fs
used L H 512fs
PLL mode where program counter H L 256fs
L H . fs fs
IS used H H 384fs
Mode for crystal oscillation
H L (Except that SI =52 = L)
Mode for simple phase
comparison (SI = S2 = L)
H H PLL mode with built-in VCO used
A varicap diode is connected to pin4 (AMPI) and pin 5 (AMPO) of inverter amplifier 1 to
form an LC oscillator. This allows a very accurate PLL circuit to be built.
Using a microcomputer allows the division ratio of the program counter to be set at your
disposal.
In this mode, the following four types of data can be set. Up to 15bits are needed for this
setting.
Data is caught at the trailing edge of the 16th DCK clock signal. In order that counting
may be started when the level at M1 terminal goes "H" from "L", make the terminal "L"
first in this mode, as shown in Fig.2.
2001 -06-1 9
TOSHIBA TC9246F/P
o Dy-Do ; These bits set a division ratio of the program counter.
10 binary bits cover the MSB first. (Division ratio:1/N=1/5 to 1/1023)
0 M1D, M2D ; These bits an inner operation mode in accordance with set operation
modes covered in Table.1.
With M1D and M2D being "H" and "L", respectively, all oscillators stop
oscillation.
It PS , This bit sets the polarity of phase error output.
H represents positive logic and L negative logic.
0 T1, T2 ; These are testing bits. Both of T1 and T2 are fixed at H.
M1 terminal (CLEAR) _s-
Szterminal (DCK) "-uCuliliCuiCuiCuiliCuiCLliCLl-
$1terminal(DATA) _CDTnCDTsXbFXtEXbTiXbrsXYr3XYr2XYr1XbT)XCusXC2DXP"sXcrrXcrry
Fig.2 Microcomputer data setting timing chart
Crystal oscillation mode
A crystal oscillator is connected to inverter amplifier 2 incorporating the feedback resistor
which inverter exists across pin7 (XI) and pin 8 (XO) in order to form a crystal oscillator
circuit.
PLL mode where incorporated VCO is used
PLL mode where an incorporated VCO oscillator is used. This mode is such that the
polarity of phase error output is inverted. Inverter amplifier 1 is used as the active filter.
Incorporated VCO -1
-o-- MCK
APD LDDA AMPI AMPO VSSA X xo
-NVV-4 ll
Fig.3 Sample basic PLL circuit-il
Simple phase comparison mode
With SI and S2 set at L in the crystal oscillation mode, a VAR signal can be entered
through pin 7 (XI), a signal of phase errors from the REF signal is issued through PD
terminal.
4 2001-06-19
TOSHIBA TC9246F/P
2. Lock detection
When VAR input signals enter the inner window (13 clocks of CKO/2) successively for a certain
period with respect to the REF input signal in the PLL mode, the PLL is considered to be locked.
LOCK output is varied from L to H. PLL lock detection period LD is determined by (1 /fs) *512.
Table.3 shows PLL lock detection periods for typical Ms for your reference.
Table.3 Sample PLL lock detection
Inner fs 32kHz 44.1kHz 48kHz
Lock detection period (LD) 16ms 11.6ms 10.7ms
A window is made by inner VCO clocks. This makes it impossible to detect errors of the VAR
input signal with respect to the REF input signal under 1/32 of divisions.
3. Phase error output
Responding to REF and VAR input shown in the block diagram, a phase error signal is output
through the PD terminal. Shown below is the relation between signals.
REFinput H
VARinput L I I I I l
PD output
-"t-e- Phase lead --I-F- Phase lag
Sample phase error output timing chart (PS bit=H ; PD output is based on positive logic.)
(Note) In the PLL mode where built-in VCO is used, the active filter is utilized. This means that
output is based on negative logic.
5 2001-06-19
TOSHIBA TC9246F/P
MAXIMUM RATINGS (Ta=25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage VDD -0.3-6.0 V
Input Voltage VIN -0.3--VDD+0.3 V
P Di . ti TC9246F P 180 IN
ower Issnpa Ion TC9246F D 300 m
Operating Temperature Top, -35~85 "C
Storage Temperature Tstg - 55~150 "C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta =25°C, VDD= 5V)
DC characteristics
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Power Supply - -- o
Voltage VDD Ta-- 35 85 C 4.5 5.0 5.5 V
Current Consumption IDD - - - - 25.0 mA
VIH REF, AMPI, XI, M1, M2, SI, 4.0 - VDD
Input Voltage VIL Sit 0.0 - 1.0 V
Input Amplitude VIN - XI 0.4 - 5.0 Vp-p
"H" Level IIH (1) VIH =5.0V - - 1.0
Input Current (1) "L'' Level llL (1) - REF, AMPI 1/IL=0.0V -1.0 - -
"H" Level IIH (2) VIH = 5.0V - - 10
Input Current (2) "L" Level 'IL (2) - XI VIL=0.OV -10 - - PA
Trystate Leak "H" Level ITLH P VIH = 5.0V - - 1.0
Current "L" Level ITLL - D VIL= o.ov - 1.0 - -
IOH PD, CKO, VOH =4.5V - - -3.0
Output Current IOL - LOCK (IOL only) VOL=0-5V 4.0 - - mA
PuII-up Resistance (1) RUp (1) - M1, M2, SI, S2 - 20 - k0
PuII-up Resistance (2) RUP (2) - LOCK - 50 -
AC characteristics
(1) Clock and data output timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Output Rising Time tor - CKO - - 10 ns
Output Falling Time tof - CKO - - 10
tof tor
CKO _ / N / \ / N / N
6 2001-06-19
TOSHIBA
(2) Microcontroller interface timing
TC9246F/P
CHARACTERlSTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Clock Pulse Width ”H” Level tWH - SHIFT 1 - - ps
L Level tWL 1 - -
Set Up Time tSUP1 - SHIFT-9DATA 0.2 - - ps
tsupz DATA-9SHIFT 0.5 - -
It Data input mode ((M1, M2)=(H, L))
(S2) tsupz
tWLtWH
\$$/\/\/
EXAMPLES OF APPLICABLE CIRCUITS
1. System clock generation by AV amplifier (DIR=Digital Audio Interface Receiver IC)
This example is such that, in order to adopt digital data from audio DSP, clocks are supplied by the
crystal oscillator and, with the DIR used, PLL clocks are supplied.
converter _
TC9245F Ps DATA
TC9245N
1bit DA converter
DATA TC9280F
BCK TC9280N
TC9246P
2. Generation of multiple system clocks
One system may call for system clocks of 256fs and 384fs.
1 chip processor
TC9246F
MCK (384fs)
Lar-j X'tal
1bit DA converter
TBI 204F
TBI 204N
DATA TC9237BF
BCK TC9237BN
l-as-l
(11.648MHz)
TC9246P
TC9246F JMCK (12.288MHa)
2001 -06-1 9
TOSHIBA TC9246F/P
3. Generation of high-accuracy master clock
The appropriate case is that hihg-accureacy master clocks are supplied to a 1bit DA converter with
the DIR used. (For example, high-accuracy master clocks are supplied for LC oscillation, VCXO,
varimega modules, etc.)
DIR 1bit DA converter
TC9245F DATA Audio DATA TC9280F
TC9245N BCK DSP BCK TC9280N
LRCK LRCK
I-wo; (384fs)
TC9246F P High-
accuracy
TC9246P VCO
4. Actions against radiation not needed
In some cases, a DA converter is connected at an interval from such signal processors as a BS tuner
and a CD player system. In these cases, master clocks should be sent without using complicated
wiring and actions taken against radiation not needed.
CD 1 chip processor
BS tuner processor 1bit DA converter
TC9050AF DATA TC9237BF Tc9236AF DATA Digital DATA DA
TC9050AN BCK TC9237BN BCK filter BCK converter
LRCK LRCK LRCK
LIHIJ , MCK (16.9344MHZ) l-BI-l X't I
' TC9246F MCK (384fs) (16.9344MHZ)
x tal TC9246P TC9246F
(18.432MH2) TC9246P
APPLICATION CIRCUIT
384fs clocks are generated in the parallel mode (using built-in VCO).
fs input
15PF 1.5kQ
0‘01,uF
384fs output
TC9246F, TC9246P
(Note) The PLL configuration and constants are tentative.
8 2001-06-19
TOSHIBA
PACKAGE DIMENS
SOP16-P-300-
HHHHHHHH "
5 31:0 2
7.8i0.3
0.705TYP
10.8MAX
10.3:t0.2
tllllildtlleili,
l1 9MAX
Weight : 0.17g (Typ.)
o 15:02
tiitir'
TC9246F/P
Unit : mm
(3 00 mil)
0.15”-1
0.8i0.2
2001 -06-1 9
TOSHIBA TC9246F/P
PACKAGE DIMENSIONS
DIP16-P-300-2.54A Unit : mm
[-1r'-'e1r-nF'--'1i-1l-1ei'-1
6.4:t0.2
V'-''-''''-'''-''
19.75MAX
19.25i0.2
03:51:01
0.735TYP . . i l 0.5i0.1_30'25 (ii)
Weight : 1.11g (Typ.)
10 2001-06-19
TOSHIBA TC9246F/P
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
11 2001-06-19
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