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TC9192-TC9192F-TC9192P
DOUBLE PLL FOR MOTOR CONTROL
T691! MP/F
DOUBLE PLL FOR MOTOR CONTROL
This is a LSI designed for motor-controlling the
copying machine of which motor-rotation speed is
necessary to be varied freely.
With built-in PLL
and VCO for reference signal generation, reference
frequency can voluntarily be varied externally.
. Through using built-in VCO, PD, phase comparator
and divider reference frequencies can be obtained.
. AFC and APC applied with 8-bit D/A converter
system is incorporated, and transistor of bipolar
type is provided at the output for Buffer Amplifier
. Lock range can be switched.
. Reference voltage output for filiter-amplifier is
provided.
Lock detection output and reverse rotation signal
output are provided.
MAXIMUM RATINGS (Ta=25°C)
Unit in mm
-TaFV-WA-IL-TEarE-Jb-3L.a'
cr. 23MAX E 1621:025
05:015
L4i015
Lead pitch is 2.54 and tolerance is
1025 against theoretical center of
each lead that is obtained on the
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage VDD -0.3-7.0 V
Input Voltage VIN -0.3~VDD+0.3 V
Power Dissipation PD 300 mW
Operating Temperature Topr -30-75 "c
Storage Temperature Tstg -55~125 "c
basis of No.1 and No.18 leads.
JEDEC -
TOSHIBA 3DI8A-P
Unit in mm
13.0MAX ' ci 7.8104 ,-,
1.2 no.1 2 0.5:025
_------
JEDEC -
TOSHIBA F-20GA-P
TOSHIBA CORPORATION
-'--t-t-t-s=--t---ss---, T09192P/F
PIN CONNECT
TC9192P
GNDUI ISDVDD
FrefEZ I‘DDO
''sigir3 16llvc
Trasrrli4 1sl1rtH
LWU5 HDRL
FGINI]6 IBDC
APCr7 1211LD
Arcr8 11rt/S
vroti9 IOURV
TC9192F
-Ns.,/
GNotil ZODVDD
Freiti2 IQDDO
r'sig03 xsnvc
TESTri4 170RH
LW[]5 16ric
NcEis ISURL
FGINU7 14Dc
APCUB JBDLD
Arcli9 IZDR/S
1rroti10 IIDRV
TOSHIBA CORPORATION
T09192P/F
BLOCK DIAGRAM TC9192P
DO VC RH RL C
17 16 15 14 13
Pref 2 PD VCO
PHASE VOLTAGE CONTROLED
COMPARATOR OSCILLATOR
Fsig 3 1/2560 DIVIDER
1/256 DIVIDEB 8-BIT D/A
DIVIDER
CONVERTER L
11 R/S
SPEED MONITOR AFC LOCK RANGE
RV 10 & TIMING DIVIDER DETECTING
REVERSE ROTATION DIVIDEE
DETECTING CIRCUIT (12 BITS J CIRCUIT 12 LD
SCHMITT FG AFC
SYNCHRONIZING 8-BIT D/A
FGIN 6 CIRCUIT
CIRCUIT CONVERTER L
18 1 4
VDD GND TEST
TOSHIBA CORPORATION
-t==--=-=t--=-==H T69192P/F
BLOCK DIAGRAM
FGIV 7
TC9192F
DO VC RH RL
COMPARATOR
1/'2560 Dr
1/256 DIVIDER
DIVIDER
SPEED MONITOR
REVERSE ROTATION
DETECTING CIRCFIT
DIVIDER
SYNCHRONIZING
CIRCUIT
SCHMITT
CIRCUIT
VDD GND TEST
TAGE CONTROLED
ILLATOR
8-BiT IV"A
CONVERTER
TIMING DIVIDER
( 12 BITS )
LOCK RANGE
DETECTING
CIRCUIT
8-BIT D/A
CONVERTER
TOSHIBA CORPORATION
T09192P/F
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta=25°C, VDD=5V)
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Operating Power Supply ' ~
Voltage VDD 4.5 5.5 ll
Power Supply Current IDD * - 7 20 mA
VCO BLOCK
Max. Operating Frequency fvco Max C=33pF, RL=OV * 4.0 6.0 - MHz
Constant of C is
. * .-
VCO Applicable Range fvco varied with fVCO 0 5 4.0 MHz
VCO Deviation AfVCO C=Constant, RL=2.0V * - $50 - 1(
VCO Fsig Frequency Range fCPIN Fsig N=2560 * 0.5 .- 4.0 MHz
FG AMPLIFIER BLOCK
Operating Frequency Range fFG vIN=0.5llp-p * - ._. 10 kHz
Input Operating Voltage VFG ffg=10kHz, Sine wave * 0.5 ~ VDD-O.5 Vp-p
Fref Frequency Range fref * 0.2 - 2.0 kHz
APC, AFC, D/A CONVERTER BLOCK
Max. Deviation Measuring at buffer - 12.5 ic6.5 LSB
output
Resolution ' - VDD/256 -
Ladder Resistance RD 30 50 70 ka
BIPOLAR TRANSFORMER OUTPUT CURRENT (APC, AFC, Vro TERMINAL)
Output Current "H" Level IOHB V0H=3V - -1.6 -0.8 mA
' "L" Level IQLB V0L=2V 3O 50 200 HA
Output Voltage Vro tefltitgce Output 1.6 1.9 2.2 V
PHASE COMPARATOR CHARACTERISTIC (D0 TERMINAL)
" " - _
Output Current H Level IOHDO 1.0 mA
"L" Level IOLDQ 1.0 2.0 ~
Output Leak Current - +
at OFF IOZDO t0.1 PA
Input Leak Current IIH/IIL Fref, vc terminal - - i1.0 uA
Pull-up Resistance RIN LU, R/S terminal 15 30 45 kn
.. " FG , LU, R s t . 1 . ._. V
Input Voltage H Level VIH IN / ermlna O 7XVDD DD V
"L" Level VIL Fref 0 - 0.3xVDD
'' " = - - -
Output Current H Level 10H EV;:0nal VOH 4V 1.0 0.5 mA
"L" Level 10L e 1 VOL=1V 0.5 1.0 -
Nch OPEN DRAIN CURRENT
Nch 0N Current OLD RH terminal VG 5V 1.5 2.5 _mA
Nch OFF Current 101D vc=0v - - 1:1.0 uA
* .. Guaranted within the range of VDD=4.5V~5.5V, Ta=-30-75"C.
TOBH'BA CORPORATION
FUNCTIONAL DISCRIPTION OF EACH PIN
T09192P/F
PIN No.
SYMBOL FUNCTION, OPERATION REMARKS
18 20 VDD . .
Power supply voltage terminal and grounding
terminal.
1 1 CND
f f . .
2 2 Fref Re erence requency Input terminal for phase C-MOS input
comparator.
3 3 Fsig 1/2560 dividing oytput termlnél of VCO frequency, C-MOS output
internally comparlson signal IS made.
5 S LU Switching terminal of lock range. Built-in pull-up
at LW="H", normal range. at LW="L", double range. resistance speed
6 7 FGIN Pulse Input terminal for indicating the rotation Built-in amp.
speed of motor.
7 8 APC Output terminal of APC 8-bit D/A converter Built-in bipolar
output. transistor
8 9 AFC Output terminal of AFC 8-bit D/A converter Built-in bipolar
output. transistor
B . _. . 1
9 10 Vro Output terminal for reference voltage. uilt 1n bipo ar
translstor
10 11 RV Reverse rotation signal for output driver. C-MOS output
11 12 R/S RUN/STOP switching terminal of motor Built-in pull-up
at R/S="L", RUN. at R/S="H", STOP resistance
Lock detecting terminal.
12 13 LB When the rotation frequency is within lock range, C-MOS output
"H" level, and in other cases, "L" level.
Terminal attached with capacitor for adjusting
13 14 C frequency.
Internal control signal is made.
14 15 RL Current control terminal for contro 1ng VCO
frequency.
. vc RH
15 17 RH Current control output terminal for VCO
16 18 VC Voltage control input terminal for VCO
l7 19 DO Output terminal of phase comparator C-MOS input
4 4 Tset Input terminal of internal test. C-MOS input
Generally ground.
- 6,16 NC No connect
TOSHIBA CORPORATION
T69192P/F
EXPLANATION OF OPERATION
TC9192P/F has double PLL which is consist of AFC/APC loop for motor-controlling and
phase feedback loop for reference signal. In the following operation of respective
block is explained.
I. Phase Feedback Loop
RESISTANCE FOR CAPACITOR FOR
CONTROLLING CURRENT OSCILLATION
REFERENCE L. P. F
SIGNAL (y,",v,,c,,l,'Ass)
SOURCE FILTER
Fsig Frefé D0 vc RH RL cg
OSCILLATOR
. ' COMPARATOR
CURRENT
VOLTAGE CONTROLLED OSCILLATOR
L/2560 DIVIDER
AFC/APC
LOOP CONTROL
SIGNAL (CP)
(1) Voltage controlled oscillator terminal (C,RL,RH,VC)
. Voltage controlled oscillator (VCO) is consist of the Nch open drain
FET (VC,RH, terminal) and current controlled oscillator (RL,C terminal)
combinated.
VCO is an oscillator of which oscillation frequency is controlled by given
control voltage. The control voltage and oscillation frequency are
proportional.
. The operation frequency range of VCO is 0.5~4MH2.
. Frequency which is obtained by VCO becomes control signal (CP) of AFC,
APC loop in next step.
TOSHIBA CORPORATION
W T09192P/F
(2) Phase comparator output terminal (Fsig, Fref, DO)
. Phase comparator detects the input pulse difference, and outputs at D0
the positive and the negative pulses proportioned with the phase difference.
PHASE COMPARATOR TIMING CHART
HIGH IMPEDANCE I l I
DO I I
Fref terminal is reference signal input terminal of APC/AFC loop control signal (CP),
the motor speed (the number of FG pulses of motor) is decided by it.
The relations between FC, Fref and FC is as follows;
fx(cP)=2560xFref[Hz] l Relation between Fref and control signal (CP)
fx(cP)=20x 128xFG[Hz] ' Relation between PG and control signal (CP)
J.This relation becomes "FG=Fref[Hz]"
. Fref input terminal is a C-MOS structure.
Fsi output terminal is output comparison sicnal of base com arator.
g o p p
2. APC/AFC Loop
(1) FG pulse input terminal (FGIN)
This is the input terminal of FC pulse for indicating the motor speed,
and this signal becomes the comparison frequency of internal PLL.
Since the amplifier and the Schmitt circuit are incorporated, operation
is made with the small amplitude through the coupling capacitor.
TOSHIBA CORPORATION
TCQ192P/F m
(2) Output terminals (APC, AFC) of phase control system (APC) and speed control
system.
. AFC is F-ll converter against FGIN frequency and is fabricated with 8-bit
D/A converter.
. APC is the phase comparator (4-N converter) for comparing the phase
difference é between -l-rc signal and the reference signal FS', and is also
fabricated with 8-bit D/A converter.
(Note) FS'= % FS
. Both APC and AFC perform three kinds of operations described below.
a) When FGIN frequency is within the lock range, both APC and AFC perform
the normal operation against FGIN.
Against the reference synchronization FS, the lock range is
at LW="L", +9.3%, -10.6% (about $101)
at LW="H", +4.62, -5.3r, (about iSZ)
(the) Reference frequency FS = faérfgg [Hz]
b) When FGIN frequency is under the lock range (under speed), the outputs
of APC and AFC are fixed at "H" level.
c) When FGIN frequency is over the lock range (over speed), the outputs of
APC and AFC are fixed at "L" level.
. When the motor is in STOP state (R/S=H or Open), both the outputs of AFC
and APC are fixed at "L" level.
. Bipolar transformer is incorporated at the output stage of both APC and
TOSHIBA CORPORATION
CHANGE OF APC OUTPUT
AGAINST FGIN FREQUENCY
FIXED AT 'H'
94 I I
‘5 I IVA OUTPUT
I I FIXED AT 'L'
L , l /
UNDER SPEED
LOCK RANGE OVER SPEED
mm FREQUENCY
. Timing charts of AFC and APC within lock range
a. AFC (speed control system)
FG PULSE
T09192P/F
CHANGE OF APC OUTPUT
AGAINST PHASE DIFFERENCE 4
8 H D/A OUTPUT
G, A I
PHASE DIFFERENCE gf
CLOCK ,
LOAD PULSE
AFC OUTPUT
REFERENCE
FREQUENCY
FS PULSE
% FG PULSE
APC OUTPUT ,
TOSHIBA CORPORATION
T09192P/F
(3) Output terminal for reference voltage generation (Vro)
. Vro is the transistor output terminal for the reference voltage of the
operational amplifier which controls the motor by means of synthesizing
the outputs of APC and AFC.
. Vro is fixed at -l-vmo -VF internally through dividing the resistance, and
the output is fabricated into bipolar transistor construction.
(h) Lock range switching input terminal (LH)
. This is the terminal for switching the lock range of APC and AFC, and two
kinds of lock ranges can be selected through operating this terminal.
at LW="H", normal lock range ($52)
at LW="L", double lock range ($102)
(5) RUN/STOP input terminal (R/S)
. RON/STOP signals of motor are input. RUN="L", STOP="H" or open
During RUN(R/S=L), APC, AFC and LD perform the normal operation against
FGIN frequency. During STOP(R/S=H or Open), APC, AFC and LD are all fixed
at "L" level.
Pull-up resistance and chattering prevention circuit are incorporated.
(6) Lock detection terminal (LD)
This is the output terminal for lock detection. When FGIN frequency is
within lock range, the terminal is at "H" level, and in other cases, at "L"
level.
(7) Reverse rotation signal output terminal (RV)
. RV is the reverse rotation signal output for applying the brake to the
motor when the motor is changed to STOP state.
. When STOP state is turned out, RV becomes "H" level, and when the frequency
of FGIN becomes below é-FS, "L" level. In other cases, RV is fixed at "L"
level.
TOSHIBA CORPORATION
'=-==-ltti=-t-=l+==-==t-t==-l_gt-t=l=t-l_l. T09192P/F
EXAMPLE OF APPLICATION CIRCUIT (Pin connect is TC9192P)
LOW-PASS
FILTER LOCK
DETECTION
a, g []
d BUN/STOP KEY
VDD o f? J,
MICROCOMPUTER etc
REFERENCE SIGNAL
GENERATION CIRCUIT FILTER DIFFERENTIAL
pc, AMP.
REVERSE
MOTOR ROTATION SIGNAL
9 COTROLLING
CIRCUIT
FREQUENCY
GENERATOR
TOSHIBA CORPORATION
TCQ192P/F
CHARACTERISTIC TEST CIRCUIT (Pin connect is TC9192P)
VCO Operating Frequency Range
(fvco)
C---5- 2200PF
é@a@mnm®®
(i1x2x3i)(?e)("i)(exi)
Nch Open Drain Current
OSC I LLOS COPE &
FREQUENCY COUNTER
(1) Operating Supply Current (IDD) (2)
fvco ADJUST VALUE OF
CAPACITOR T0 4MHz
IDD VDD=45~55V
o----- cr-
VDD=5V
w n w u @900
G.'-"" ) Ci) "V"
f=lkHz _ Vrtrc= 0.5Vp- p
f=1kHz
. ' . (4)
(3) FGIN Input Sensitivity
C=33pF
VDD=45~55V F7;
MONITOR VDD=5V
@m@@ oSFilii)
= ) S:
(,r'i)'i)(i)i-,i-_)f7,')(_)?
--- OSCILLOSCOPE
VDD=5V
"i,)(ryyai)(sii'''i'-i-r-i)
—K———xD
énm:é@aoa
CiX2Xi)C0(De)C7XisXi)
VCO Operating Frequency Range (2) (fvco)
TOBHIBA CORPORATION
ILOSCILLOSCOPE & FREQUENCY COUNTER
-5i54-
VCO OPERATING FREQUENCY VCO OPERATING FREQUENCY
OPERATING SUPPLY CURRENT
fVCO (MHz)
fVCO (MHz)
IDD (mA)
C - fvco
100 TEST CIRCUITQ)
w Ta=25C
30 VDD = 5 V
Ri, = 0 V
1 3 10 30 100 300 1000 3000 10000
VCO LOAD CAPACITY c (pF)
IDs - fvco
TEST CIRCUIT(5)
Ta == 25'C
VDD= 5V
== 33pF
0 0.5 1.0 1.5 2.0 2.5 3.0
R1 CURRENT OF INPUT TERMINAL VDD (V)
VDD - IDD
TEST CIRCUIT (1)
Ta: 25''C
0 1 2 3 4 5 6 7 8
OPERATING SUPPLY VOLTAGE VDD (V)
VCO OPERATING FREQUENCY
fvco (MHz)
VCO OPERATING FREQUENCY
f VCO (MHz)
1]) (mA)
Nch DRAIN CURRENT
T09192P/F
VDD - fvco
TEST CIRCUITQ}
Ta=25'C
RL=0 V
c=33 pF
2 3 4 5 6 7 8
OPERATING SUPPLY VOLTAGE VDD (V)
Ta - fvco
TEST CIRCUITQ)
VDD =5V
VRL = 0V
C: 33pF
-40 -20 0 20 40 6O 80
AMBIENT TEMPERATURE Ta ('C)
"G - ID
TEST CIRCUIT
Ta=25T
1 2 3 4 5 6 7
Nch GATE VOLTAGE VG (v)
TOSHIBA CORPORATION
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