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TC90101FG
Comb Filter Front-End Processors
TOSHIBA TC90101FG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
. . TCQO10‘IFG
TC90101FG is a 1chip LSI of multi 3line comb and multi color decoder.
TC90101FG has 10bit ADC and 2channels 8bit ADC for analog Video signal interface
and also include Y/C separation, color decode, and signal processing circuit.
The output interface of TC90101FG is a selectable for ITUR-601 & 656.
Featurs
q Multi color system
. Input I/F: CVBS, Y/C, chCr(1 H & 525p/625p)
. Multi 3 line comb (SECAM: BPF)
q Component signal frequency detection (525i/525p/625i/625p)
o AGC circuit
q Output format : 656/601
. Picture improvement LQFP100-P-1414-0.5C
Y: Vertical enhance/LTI/Contrast/Setup adjust
C: TOF/ACC/Color decode/color gain/CTI/offset adjust Weight : 0.65g(Typ)
0 Noise level detection/IDi(5251 & 525p) data slice/
CCD data slice/WSS data slice/ Macrovision detection
. 120 bus control
0 Read data superposition on ITUR-656 output
. Package: LQFP 100 (0.5mm pitch)
0 Power supply: 3.3 V, 2.5V, 1.5V
Version 4.2
(notel jThese devices are easy to be dam aged by high voltage or electric fietis.
In regards to this, please handle with care.
O TOSHIBA is continually working to improve the quality and the reliability of its product.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a
malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used
within specified operating ranges as set forth in the most recent products specifications. Also,
please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor
Reliability Handbook.
Feb. / 2005 1
TOSH I BA TC90101FG
1. Block Diagram
HD/VD X'tal
reference
Gene. clock
Sync Sep. Timing X 8
S/N detection
macrovision
CCD slice
Y I 27M
10bit ADC
CVBS _ enhance
contrast adust
delay adjust 656/601
encode
C _ 27M Format
8bit ADC
Cb -I color decord
TINT adju st
Color adjust
Bbit ADC
IIC-BUS
SCL SDA
2. Pin Layout
Ollfnnf I/F
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ammo >- * g cp 1 5 3.3 1 5 rEmslErl-
Analoglnput l/F 'i, 2.5 T090101FG Chitraiit l/F
Top view
L 5 CSYNC IN
- DVDDZ
TESTM4
TESTMS
TESTM2
TESTM1
Feb. / 2005 2
TOSHIBA
TC90101FG
3. Terminals discription
Pin Pin Function Durable I/O Circuit DC at Analog signal
No Name ( ) :Condition at normal operation voltage (Analog or Digital) normal Amplitude
(V) Oparation (Vp-p)
1 VREFDA The reference voltage terminal of DAC 2.5 Bypass 1.5 -
2 VDDPLL Power supply for X8 PLL circuit 2.5 VDD 2.5 -
3 PLLIN Input terminal of X8 PLL circuit 2.5 iN Analog 1.25 0.5~
VDDPLL*0.8
4 VCOFlL Filter terminal for X8 PLL circuit 2.5 Bypass 1.2 -
5 VSSPLL GND for X8 PLL circuit 0 GND 0 -
6 VDDXO Power supply for X' tal OSC circuit 3.3 VDD 3.3 -
7 XOIN X' tal OSC circuit input terminal 3.3 IN - -
8 XOOUT X' tal OSC circuit output terminal 3.3 OUT - -
9 VSSXO GND for X' tal OSC circuit 0 GND 0 -
10 TDIO9 3.3 1/0 - -
11 TDIOB 3.3 I/O - -
12 TDIO'I Terminal for Test mode 3.3 1/0 - -
13 TD106 (Normaly Open) 3.3 1/0 - -
14 TD105 3.3 1/0 - -
15 DVDD1 Power supply for Logic circuit 1.5 VDD 1.5 -
16 TDIO4 3.3 1/0 - -
17 TDIO3 Terminal for Test mode 3.3 1/0 - -
18 TDIOZ (Normaly Open) 3.3 1/0 - -
19 DVSS1 GND for Logic circuit 0 GND 0 -
20 TDIO1 3.3 1/0 - -
21 TDIOO Terminal for Test mode 3.3 1/0 Digital - -
22 TDCLK (Normaly Open) 3.3 IN - -
23 VDDIO3 Power supply for i/O 3.3 VDD 3.3 -
24 BUSSEL IICBUS slave address selection(L:B0, Hi:B2) 3.3 IN - -
25 RESET Reset terminal (Low :Reset Hi :normal) 3.3 IN 3.3 -
26 SDA IIC SDA terminal (5Vinput possible) 5 I/O - -
27 SCL IIC SCL terminal (5V input possible) 5 IN -
28 TESTM1 3.3 IN 0 -
29 TESTM2 Terminal for Test mode 3.3 IN 0 -
30 TESTM3 (Normaly connect to GND) 3.3 IN 0 -
31 TESTM4 3.3 IN 0 -
32 DVDD2 Power supply for Logic circuit 1.5 VDD 1.5 -
33 CSYNCIN External composite Sync signal input 5 IN 0 -
(In case not use external CSYNC, conect to GND)
34 DVSS2 GND for Logic circuit 0 GND 0 -
35 YOUT9 Digital video port output 9 (MSB) 3.3 OUT - -
(656/ 601 mode:YCbCr, 601 :Y)
M YOUT8 Digital video port output 8 3.3 OUT - -
37 YOUT7 Digital video port output 7 3.3 OUT - -
38 YOUT6 Digital video port output 6 3.3 OUT - -
39 DVDD3 Power supply for Logic circuit 1.5 VDD 1.5 -
40 YOUT5 Digital video port output 5 3.3 OUT - -
41 YOUT4 Digital video port output 4 3.3 OUT - -
42 DVSSS GND for Logic circuit 0 GND 0 -
43 YOUT3 Digital video port output 3 3.3 OUT - -
44 YOUT2 Digital video port output 2 3.3 OUT - -
45 VSSIOI GND for I/O 0 GND 0 -
46 YOUT1 Digital video port output 1 3.3 OUT - -
(In case 8bit output mode : fixed to Low)
47 YOUTO Digital video port output 0 3.3 OUT - -
(In case 8bit output mode : fixed to Low)
48 CKOUT System Clock output terminal for digital video signal output. 3.3 OUT - -
656 : 27MHz 601 : 13.5MHz
49 VDDlO1 Power supply for i/O 3.3 VDD 3.3 -
50 TESTM5 Terminal for Test mode(Normaly connect to GND) 3.3 IN 0 -
Feb. / 2005 3
TOSHIBA TC90101FG
Pin Pin Function Durable I/O Circuit DC at Analog signal
No Name ( ) :Condition at normal operation voltage (Analog or Digital) normal Amplitude
(V) Oparation (Vp-p)
51 TESTM6 Terminal for Test mode(Normaly connect to GND) 3.3 IN 0 -
52 COUTO CbCr digital video signal output (LSB) 3.3 OUT - -
(656:00UTO-9 are fixed Low 601 :CbCr)
(In case 16bit mode: This terminal is faed Low)
53 COUT1 CbCr digital video signal output (2 nd LSB) 3.3 OUT - -
(In case 16bit mode: This terminal is fixed Low)
54 DVDD4 Power supply for Logic circuit 1.5 VDD 1.5 -
55 COUT2 CbCr digital video signal output 2 3.3 OUT - -
56 COUT3 CbCr digital video signal output 3 3.3 OUT - -
57 DVSS4 GND for Logic circuit 0 GND 0 -
58 COUT4 CbCr digital video signal output 4 3.3 OUT Digital - -
59 COUT5 CbCr digital video signal output 5 3.3 OUT - -
60 VDDIO2 Power supply for i/O 3.3 VDD 3.3 -
61 COUT6 CbCr digital video signal output 6 3.3 OUT - -
62 COUT7 CbCr digital video signal output 7 3.3 OUT - -
63 VSSIOZ GND for I/O 0 GND 0 -
64 COUT8 CbCr digital video signal output 8 3.3 OUT - -
65 COUT9 CbCr digital video signal output 9 (MSB) 3.3 OUT - -
66 DVDD5 Power supply for Logic circuit 1.5 VDD 1.5 -
67 UVFLAG Reference timing pulse for multiplexed Cb/Cr signal 3.3 OUT - -
68 HDOUT Horizontal reference timing pulse 3.3 OUT - -
69 DVSS5 GND for Logic circuit 0 GND 0 -
70 VDOUT Vertical reference timing pulse 3.3 OUT - -
71 ODD/EVEN Field index output 3.3 OUT - -
72 VBIREADY Reference timing pulse of IIC read for VBl data slice 3.3 OUT - -
Function (Hi level at 23 line and 286 line)
73 GOP Clamp gate timing pulse 3.3 OUT - -
74 YCLAMPP1 Clamp signal output for CVBSIN 3.3 OUT - -
75 YCLAMPP2 Clamp signal output for YIN 3.3 OUT - -
76 BIASYAD Bias terminal for internal 10bit ADC 2.5 Bypass 0.8 -
77 VRTYAD Reference top voltage terminal for internal 10bit ADC 2.5 Bypass 1.75 -
78 YIN Analog Y signal input terminal (1 Obit ADC) 2.5 IN - VDDYADXO.4
79 VSSYAD GND for internal 10bit ADC 0 GND 0 -
80 VRMYAD The reference middle voltage terminal for 2.5 Bypass 1.25 -
Internal 10bit ADC
81 CVBSIN Analog CVBS signal input terminal (10bit ADC) 2.5 iN - 1/DDYADx0.4
82 VDDYAD Power supply for internal 10bit ADC 2.5 VDD 2.5 -
83 VRBYAD Reference bottom voltage terminal for internal 10bit ADC 2.5 Bypass 0.75 -
84 BIASCAD Bias terminal for internal 8bit C/Cb-ADC 2.5 Bypass Analog 0.8 -
85 VRTCAD Reference top voltage terminal for internal 8bit C/Cb-ADC 2.5 Bypass 1.75
86 CIN Analog C signal input terminal (8bit ADC) 2.5 IN 1.25 VDDCADXO.4
87 VSSCAD GND for internal 8bit C/Cb-ADC 0 GND 0 -
88 Ohm Analog Cb signal input terminal (8bit ADC) 2.5 iN - 1/DDCADx0.4
89 VDDCAD Power supply for internal 8bit C/Cb-ADC 2.5 VDD 2.5 -
90 VRBCAD Reference bottom voltage terminal for 8bit C/Cb-ADC 2.5 Bypass 0.75
91 BIASRAD Bias terminal for internal 8bit Cr-ADC 2.5 Bypass 0.8 -
92 VRTRAD Reference top voltage terminal for 8bit Cr-ADC 2.5 Bypass 1.75 -
93 VSSRAD GND for internal 8bit Cr-ADC 0 GND 0 -
94 CrIN Analog Cb signal input terminal (8bit ADC) 2.5 IN - VDDRADx0.4
95 VDDRAD Power supply for internal 8bit Cr-ADC 2.5 VDD 2.5 -
96 VRBRAD Reference bottom voltage terminal 8bit Cr-ADC 2.5 Bypass 0.75 -
97 VDDDA Power supply for internal DAC of NCO 2.5 VDD 2.5 -
98 DAOUT Output terminal of DAC of NCO 2.5 OUT 2 VDDDA-VDDD
99 VSSDA GND for internal DAC of NCO 0 GND 0 -
100 BIASDA Bias terminal for internal DAC 2.5 Bypass 0.9 -
(Note) Please place the capacitor at near the terminal.
Please take care Surge for the HO l/F terminals.
Feb. / 2005 4
TOSHIBA TC90101FG
4.FunctionalDescription
4.1 General Description
TC90101FG is a Video decoder device for multi color system (525i. 625i).
TC90101FG also has a through mode and sync processing for 525p & 625p component signal.
1.TC90101FG has input interface for CVBS, S-Video, YC b Cr. For RGB signal it needs some
external circuit as below.
SCART G RGB YCbC AMP/LPF TC90101FG
RB r AMP/LPF c-ro..
AMP/LPF "-"t
2. Automatic clamp control circuit.
3. Multi 3line comb fllter.
4. Multi color decoder and sync processing.
5. Color system detection circuit. (Selectable auto detection and manual setting.)
Result of color system dtection can be read via IIC.
. Frequncy detection circuit for 525i/525p/625i/625p for component signal.
. AGC circuit circuit at after stage of ADC.
. Picture processing circuit for CVBS, S-Video, 525i/625I component signal.
. Selectable ITUR-601, |TUR-656 output interface.
10. VBI data slice function (525i |D-1/525p lD-1/ CCD/ WSS). It can be read via IIC.
11. Macrovision detection circuit.
12. Noise level detection circuit.
13. Superposition function for IIC read data on ITUR-656 ouitput.
COCONO)
4.2 Fanctional Discription
1. Clock System
TC90101FG has a digital VCO circuit which uses 42MHz free run X'tal OSC.
Digital VCO circuit generates 27MHz fH clock for input stage, 4fsc clock for internal comb block
And 13.5MHz for output stage.
2.0 Input interface
Input signal Pin name Terminal
CVBS CVBS IN 81
Y(S-Video & Component) YIN 78
C(S-Video & Component) CIN 86
Cb Cb IN 88
Cr Cr IN 94
2.1 Selection input signal
Input signal can be set via INSEL at sub address 00hex.
INSEL : 00 : CVBS 01: S-Video 10: YCbCr 11: SCART( **)
( *) : it's not available to input RGB signal dilectlly.
It's needs RGB to YCbCr conversion circuit at the before stage of TC90101FG.
In this mode CVBS must be inputted to CVBIN for sync processing, noise dtection and
VBI data slice.
Feb. / 2005 5
TOSH I BA TC90101FG
2.2 Input signal amplitude
TC90101FG has a 10bit ADC for CVBS & Y signal and 2ch 8bit ADC for C & Cb/Cr.
The Dynamic range of ADC is desgned as AVDD *0.4 (Normally 1Vpp at AVDD = 2 5V)
The recomemdatlon amplitude of the input signal : 0.7Vpp at 140IRE (CVBS/Y) . refer t6 fig-l.
In case of AGC ON, recommendation input signal amplitude is 0.6Vpp (140IRE).
(AGC control range is from - 6dB to +3dB.)
7 77777777777777777777777777777777777 7 1023
100 - -....__..._...__...e_. 2 2 767
so fliiiiii
60 - iiiiiii _ AVDDx0.4V
20 - iii 0.7Vp-p
o - 256
-20 - ii l
-40 51
____________________________________ - 0
Fig 1 Amlitude of CVBS input
- _ - 255
20 - 2 iillllit - mL
0 ll” NI - iiiiii (iiiiiiiiiiiii ___________ 128 0.2Vp-p
-20 - ''''1--iiiiiiiii iiiiiiiiiiiii? 103
Fig-2. Amlitude of C input
’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’ 7 255
128 07pr
- ----------------- 0
Fig-3. Amlitude of base band C signal input
Feb. / 2005
TOSHIBA TC90101FG
The amplitude of input signal for 10bit ADC is 0.7Vp-p as 140lRE. in case of C signal for S-video.
The amplitude of input signal for C ADC is 0.2Vp-p as 40lRE. (Refer to Fig-2.)
The amplitude of input signal for Cb/Cr is 0.7Vp-p as 100% level. (Refer to Fig-3.) (VDD = 2.5V)
Input signal vs output signal level
Input signal Input signal amplitude: Ouput signal level(LSB)
Vp-p(->I<)
CVBS 0.7Vp-p(500mVp-p) 16-235(pedestal to white 100%) (8bit mode)
Y 0.7Vp-p(500mVp-p) 16-235(pedestal to white 100%) (8bit mode)
C 0.2Vp-p(Burst) 16-240(8bit mode)
Cb 0.7Vp-p (100% color) 16-240(8bit mode)
Cr 0.7Vp-p (100% color) 16-240(8bit mode)
>'< Input signal amplitude: For CVBS and Y, it means 100% level (140lRE).
(500mVp-p: pedestal to white 100%.)
Cb/Cr, it means 100% color bar Signal.
Notice: These amplitude of output signal have done by initial value of IIC registers related with gain.
3. Clamping
The clam control circuit controls the corect clamping for input signals.
TC90101FG has a feed back clamp for H-Sync portion of CVBS/Y input signal to clamp 256LSB(10bit unit).
It is selectable to use the 2 types of the feed back clamp (internal circuit or external circuit) via
IIC bus. (FBCLMPEX at sub address 03 hex.)
In case use external, the clamp signal from YCLAMP1,YCLAMP2(pin 74,75) to be connected with input
Terminals. (refer to application circuit.)
For C signal, it is biased to 128 LSB. For Cb and Cr signal, it is used keed clamping control to 128 LSB.
Input mode Input signal t',li,u,, ADC Clamping function Comment
CVBS CVBS 81 10bit Time constant is selectable for
. internalClamping mode via BUS
. Y 78 10bit Feed back clamp FBCLMOD atSub address 32hex.
S- Video/ C 86 8bit - Biased to 128LSB
YCbCr Cb/Cr 88/94 8bit Keed clamp
CVBS+ CVBS 81 8bit Sync chip clamp
YCbCr Y 78 10bit Feed back clamp
(1H) Cb/Cr 88/94 8bit(MPX) Keed clamp
4. TV system detection for CVBS and S- Video input
TC90101FG has 4 types of detection mode and it is selectable via AUTDET at sub address 00hex.
AUTODET Mode Fsc detection Commemt
00 Manual setting - TV system is set via TVO - TV3 at sub address 00hex.
01 EU 4.4336MHz Priority : 4.43MHz PAL-r NTSC-' SECAM
3.57954MHZ (it's not available to detect 3.58MHz PAL signal.)
10 . Sjgggmiz P_riority : 3.08MH2 PAL- 3.58MHz NTSC
South America 3.5820MHZ (it's not available to detect 4.43MHz fsc signal.)
4.4336MH2
3.57954MHz
11 Full multi 3.5756MHZ Priority : PAL-r NTSC-r SECAM
3.5820MHz
There is not priority for 50Hz/60Hz(Vertical frequency) detection.
VD output (pin 70) is controled via VD.DET at sub address 23hex.
[00] : free run.
[01] : fixed mode when it detects no signal (The frequency of VDOUT is depends on TVM2.)
[10]: Fixed Frequency at Manual setting mode.
[11]: VDOUT is depends on TVM2 at all of TV system detection mode.
Feb. / 2005 7
TOSHIBA TC90101FG
5. HIV Sync processing
TC90101FG has H/V sync separation circuit and regenrates HDND pulse.
The phase and width of HDND pulse are controled via THRHV at sub address 22hex.
[0] : 656 format.
[1] : Syncronized with input signal.
6. D2 signal (525p/525p component) processing
TC90101FG has D1 and D2 detection circuit and Sync processing for D2 signal.
D2 signal is converted as 4:2:2 digital signal by internal ADC. (Sampling rate on ADC is 27MHz.)
ID-l data slice for 525p is available but It's not available to use picture implrovement function and
Noise level detection, (The sliced data of ID-l can be read via IIC.)
7. T.O.F (Take Off filter)
TC90101FG has Take Off filiter which is in front of color decoder.
Characteristic of T.O.F is set via TOF at sub address 0C hex.
[000] : Off [001] : type 1- [111] : type 7
(Type 1 : BPF.)
8. Y process
a) Vertical enhancement : adjustable coring, gain, and non-Iinear performance
b) LTI function
The performance of this function is controlled via lregisters at 04 and 05 hex.
f0 : 3.3MHz / 2.2MHz
Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE
Gain : Off/ 1/8 / 1/4/ 1/2
c) Sharpness
The performance of this function is controlled via lregisters at 02 and O3 hex.
f0 : 4.2MHz / 3.3MHz
Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE
Gain:-1/4 -Off -112
LTI fie
Sharpness/
t1ise_cancel
fO/Gain/Coring
fO/Gain/Coring
d) Noise canceller
The performance of this function is controlled via lregisters at 04 hex.
f0 : 4.2MHz / 3.3MHz ( It uses same register with f0 of sharpness control.)
Coring : 0.8IRE/1.6IRE/3.2|RE/6.4IRE
Gain : -1/4 - Off -1/2
e) Contrast
Control range : x (1/2) - x 2.4
f) Brightness
it's effective at the periode of picture signal portion.
Control range : -128LSB - 128LSB ( 10bit unit)
9. C process
a) ACC control : A reference level is set up by register ACC LEVEL.
b) Killer control : sensitivity of killer is set via [BUS KILLV] at sub address 37 hex.
In case Killer detection, comb filter for Y becomes off.
c) HUE control : Hue control is available for CVBS and C signal of NTSC system.
Hue bias : 0 - +45degree
Hue range : -45 degree --- +43.6degree
d) Sub color gain control
Amplitude of Cb and Cr signals are controlled via IIC.
Control range is -6dB - +2.8dB
Feb. / 2005 8
TOSHIBA TC90101FG
e) CTI function
f0 is selectable (1 .7MHz/ 3.3MHz).
Coring level is selectable (0.4IRE/ 0.8IRE/ 1.6IRE/ 3.2lRE).
Gain is selectable (OFF/ x1/8 / x1/4 / x1/2).
f) Offset control of the period of picture area
The DC level of the Cb and Cr signals are controlled via IIC independently.
Control range : -8LSB ---- +7LSB (10bit unit)
10. Output format
Output format (data format/clock/phase) is controlled via IIC Bus.
Y:The Pedestal level is 16LSB at 8bit output format and 64LSB at 10bit output format.
C:The signal level is 128LSB except for picture periode at 8bit output mode. (10bit mode: 512LSB)
The output format (656/601) is set via FORMATO (01h,D3) and the Dynamic range is set via OUTBlTS(01h, D2)
Picture periode of Y output can be controlled by CLP (20h,D0).
CLP = [1] : the signal of under 16LSB (8bit mode) is sliced at 16LSB. (standard mode.)
CLP = [0] : It's available to output the signal of under 16LSB.
Normaly it must be set [1].
Output Terminals Bit Data rate Comment
YOUT [0-9] (note) 10 13i'ltiii/si2"iz WYCbCr(601/656)
COUT [0-9] (note) 10 6.75MHz Cb/Cr(CLK:13.5MHZ)
Reference timin ulse for Cb/Cr
UVFLAG 1 (13.5/2)MHz Polarity : Cr = HggEUnitial value)
1 864fH/1728fH : 625Iine source
CKOUT (note) 13.5MHz/27MHz(/54M 858fH/1716fH : 525line source
Hz) Polarity : Reversal(lnitial value)
HDOUT 1 fH Re-generated HD
VDOUT 1 f\/ Re- generated VD
ODDEVEN 1 N Field indication
VBIREADY 1 N Flag after VBI data slicing
Note : YOUT, COUT, CKOUT has Hi impeadance mode. (01h,D1)
a) 525i/60Hz CVBS inputmode
CVBS ‘525E‘1 2’3 4 sl617ls 9 10---|19‘2o
iii 1 iJUJLiIJUiiHi Iilil-je''-i2l-'/l-
Sync Through
ODD/EVEN FIELD 1 _ f
656 VDOUT
ODD/EVEN FIELD 1
( Selectable Sync through mode and 656 mode via THRHV at sub address 22hex.
656: Field1 : Line 4 EAV
Field Blanking ; Start-r Line 1 EAV, Finish-r Line 10 EAV
VBI READY: High level output - from Line 23 SAV to Line 24 EAV
Feb. / 2005 q
TOSHIBA
(2nd Field)
263 264 265 $266 267 268 269 270 271
eves l l Iii., l l l l
TC90101FG
272 273
WNW nfliMmimi n
HDOUT Jlj] En nn fl]
] 6m L
VDOUT 'i, 'i, I 4
Sync Through i.' i.' i "..' /
Mode i' i' i ,4
ODD/EVEN FIELD 2
656 VDOUT
Mode f
ODD/EVEN FIELD 2
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex.
656: Field 2: Line 266 EAV
Field Blanking ; Start-y Line 264 EAV, Finish-, Line 273 EAV
VBI READY: High level output - from Line 286 SAV to Line 287 EAV
b) 625i/50Hz CVBS input mode
(1st, 3rd Field)
CVBS 621‘622l623 624 625 1 2 ls 4'5 ‘6’ |22|23
-i?l--i''l-r.:-; HJiiMFHHH
HDOUT J n _,). -l. . i'
VDOUT a;
Sync Through I
ODD/EVEN FIELD 1 f
656 VDOUT
Mode i.."
ODD/EVEN FIE§LD 1 f
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex.
656: Field1 : Line 1 EAV
Field Blanking ; Start-r Line 624 EAV, Finish-r Line 23 EAV
VBI READY: High level output _ from Line 64 SAV to Line 65 EAV
Feb. / 2005
TOSHIBA
(2nd Ath Field)
310 311| 312 313 314 I 315
HDOUT j
[lil ii!
TC90101FG
316 I 317 I318 I 319 I
IVDOUT
Sync Through
IODD/EVEN
i"'-)rb1--iso-oo- W
\E\ \3\
Mode VDOUT
ODD/EVEN
FIELD 2
FIELD 2
Selectable Sync through mode and 656 mode via THRHV at sub address 22hex.
656: Field 2: Line 313 EAV
Field Blanking ; Start-y Line 311 EAV, Finish-r Line 336 EAV
VBI READY: High level output - from Line 377 SAV to Line 378 EAV
The pulse width of HD/VD output at Sync through mode
525i l 625i
HD pulse width 4.74p s
(128 cycle (unit: 27MHz clock)
VD pulse width 3H l 2.5H
Notice: 656 output mode
The width of HD pulse is same as the period of between EAV and SAV.
In case of input non standard signal, it may not be above value.
Feb. / 2005
TOSHIBA TC90101FG
11. Feature function
a) S/N detection (noise level detection)
Noise level detection is performed in the vertical blanking period. The result of noise level detection is
stored to IIC read register and it is performed at every field.
The related write registers are as follows.
EN NOISEV s (sub address IB hex) : Setup of start line for noise detection.
EN NOISEV IN (sub address IA hex) : Setup of the numbers of lines for noise detection .
EN NOISEH S (sub address 1A hex) .' Setup of start position for noise detection at selected line.
EN NOISEH W(sub address 1A hex) .' Setup of the period for noise detection at selected line.
Reference position
EN NOISEH W
EN NOISEH S
b-1) Video ID (ID-l) data slice function for NTSC 525i signal (CVBS/S-video/Component)
ID-l data slicing is performed at line 20 and 283 in the vertical blanking period.
The sliced data is stored to IIC read register and it is performed at every field.
b-2) Video ID (ID-l) data slice function for NTSC 525p signal (Component)
ID-l data slicing is performed at line 41 in the vertical blanking period for NTSC 525p signal.
The sliced data is stored to IIC read register and it is performed at every vertical blanking periode.
c) CCD data slice function for US area(NTSC 525i signal (CVBS))
CCD data slicing is performed at line 21 and 284 in the vertical blanking period.
The sliced data is stored to IIC read register and it is performed at every field.
CRI detection, start bit detection and sliced data can be read via IIC bus.
d) WSS data slice function for EU area (PAL 625i signal (CVBS))
WSS data slicing is performed at line 23 and 336 in the vertical blanking period.
The sliced data is stored to IIC read register and it is performed at every field.
RUN-IN detection, start code detection and sliced data can be read via IIC bus.
e) Macrovision detection
TC90101FG can detect a pseudo sync, AGC pulse and color stripe.
The result of Macrovision detection can be read via IIC bus.
f) AGC function
TC90101FG has an AGC function for CVBS and Y signal (S-video).
The related write registers are as follows.
PAGCON (sub address 2B hex) : Setup for PEAK AGC function.
PKLIM (sub address 2B hex) : Setup for limit level for PEAK AGC function.
SAGCON (sub address 2B hex) : Setup for SYNC AGC function.
(Through mode : Both registers (PAGCON & SAGCON) must be set [0]. )
Feb. / 2005 12
TOSHIBA
TC90101FG
Insertion of IIC read data for output
TC90101FG has IIC read data insert mode for ITU-656 out put format.
It's also available for ITU-601 mode.
Selection of the line for IIC read data insertion is set via register at sub address 25hex and 26hex .
CID25H D7 : Insertion ON / OFF control for Horisontal blanking periode.
©25H D6 : Insertion ON / OFF control for Vertical blanking periode.
©25H D5 : Selection ofinsertion for |TU-601 mode
@25H D4-DO : Line selection of insertion for Horizontal blanking periode.
©26H D7-D4 : Line selection of insertion for Vertical blanking periode.
TC90101FG uses "the 2nd form of ARIB "
These functions are based on ARIB STD-B6.
ADF :Auxiliary signal flag word (Fixation) 3 word
ADF DID SDID DC UDW CS DID :For discernment (set by register)
SDID :For discernment 2nd data(set by register)
- DC :Data count code(the numbers of UDW word)
UDW :User data word (main data)
CS :Check sum (DID-UDW)
ADF uses fixed value.
1) at the 10bit mode
OOOh 3FFh 3FFh
2) at the 8 bit mode
DID has 4bit control registers (26H : D3-D0).
1) For 10bit mode.
D9(MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB)
D_8 Dl7:0ltDiitlNeivls o 1 o o DID3 DID2 DID1 DIDO
2) For 8bit mode.
D7(MSB) D6 D5 D4 D3 D2 D1 DO(LSB)
o o o o DID3 DID2 o 0 E
(Notice) D|D[3:2]=00 is not available when use 8bit mode.
SDID has 4bit control registers (27H).
1) For 10bit mode.
D9(MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB)
- DT0ltDilrm'i'li-ee'vF SDID? some SDID5 SDID4 SDID3 SDID2 SDID1 SDIDO
2) For 8bit mode.
D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB)
$0107 SDIDG SDIDS SDID4 SDID3 SDID2 o 0
(Notice) DlD7a=0000 00 is not available when use 8bit mode.
DC uses Fixed value.
1) For 10bit mode.
D9(MSB) D8 D7 D6 D5 D4 D3 D2 D1 DO(LSB)
o 1 o o 1 o o o o o
2) For 8bit mode.
D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB)
o 1 o o 1 o o o
Feb. / 2005
TOSHIBA TC90101FG
In case of 1byte Read register (RD[7:0]), it is superposed as below
-Read register1 byte.
RD7 I RD6 I RD5 I RD4Q)R03 I RD2 I RD1 I RDO I
-656 insertion: lst word. //'''''''"
D7 D6 D5 D4 D3 D2 D1 D0 D(-1) I D(-2)
o 1 RD? RD6 RD5 RD4 o o 0.0
(10bit 'mode)
.656 insertion: 2nd word
D7 D6 D5 D4 D3 D2 D1 D0 D(-1) I Did)
o o RD3 RD2 RD1 RDO 1 o 0.0
(10bit 'mode)
Check sum means total value of DID to UWD as below.
1 ) 10bit mode
It calculates totalyalue of the 9bits low ranks of DID, SDID, DC and all of UDW.
MSB(D9) means D8 of calculated valu. (it ignores the over flow.)
D9 D8 I D7 I D6 I D5 I D4 I D3 I D2 I D1 I DO
- Total value of the 9bits low ranks of DID, SDID, DC and all of UDW.
D8 (it ignores the over flow.)
2) 8bit mode
It calculates tottlyalue of the 7bits low ranks of DID, SDID, DC and all of UDW.
MSB(D7) means D6 of calculated valu. (it ignores the over flow.)
D7 D6ID5|D4ID3ID2lD1IDO
- Total value of the 9bits low ranks of DID, SDID, DC
D6 and all of UDW.(it ignores the over flow.)
Feb. / 2005 14
TOSHIBA TC90101FG
4. IIC BUS
TC90101FG has two slave address (B2 hexand BOhex). A slave address is chosen by BUSSEL
Terminal which is pin 24. (BUSSEL=L : BOhex , BUSSEL=H : B2hex) a
A6 A5 A4 A3 A2 A1 A0 W
. Data transmission format
Isl SlaveAddress IoIAI SubAddress IAI Data IAIPI
l 7bit l 8bit T 8bit .-.
MSB MSB MSB S: Start condition
P: Stop condition
A: Acknowledgement
(1) Start condition, Stop condition (2) Bit transmission
SDA '=N(''' Turs, c- SDA / X l
SCL s \ CTI / P SCL T / t -
Stop conditions SDA is not changed. SDA is changed.
Start conditions
(3) Acknowledgement
SDA from \ E igh impedance
Master
High impedance
SCLfrom \ (1 -iv/rL//rl,
Master s
Start conditions
Purchase of TOSHIBA ft components conveys a I icense under the Phi I ips ft Patent Rights to use these
components in an ft system, provided that the system conforms to the ft Standard Spec i f i cat i on as def i ned
by Phi I ips.
Feb. / 2005 15
TOSHIBA TC90101FG
I IO BUS MAP
Sub D7 I D6 D5 D4 D3 D2 D1 I DO
00H INSEL TVM3 TVM2 TVM1 TVMO AUTODET
Input signal selection FSC selection FV selection PAL selection SECAM selection Color system detection mode
00:CVBS 0:3.58MH2 0:60Hz 0:Not PAL 0: Not SECAM 00:Manual (00h-D5. .D2 : Active)
01 :Y/C(S-Video) 1 :4.43MHz 1 :50Hz 1 :PAL 1 :SECAM 01 :EU mode
10:YCbCr(D1or D2 Component) 0000: NT358 0100:NT50 1000 : NT443 1100:don't use 10: South America
11 :CVBS+YCbCr(for SCART) 0001 :don't use 0101 :don't use 1001 :SECGO 1101 :SECAM 11 :Full detection mode
0010:PAL-M 0110:PAL-N 1010:PAL60 1110:PAL
INIT:03H 0011 :don't use 0111:don't use 1011 :don't use 1111 :don't use
01H YCS Mode SELCK FORMATO OUTBITS HIZMODE ADPWD
3LYCS selection Fixed to [0] Frequency of CKOUT(pin48) selectio/ setting of output Stand by mode
0 : 3line 1O : 54MHz 00: 13.5MH2 0 : Rec601 0 : 8bit 0 : Normal 0 : ADO-OFF
[NIT:33H 1:BPF 11 : 13.5MHz 01 :27MHz 1 :Rec656 1:10bit 1:0pen 1:Norma|
02H V ENH GAIN V ENH MAX POINT V ENH SLICE LEVEL FENH PRENH
V Enhance Gain V Enhance Non-linear V Enhance Caring Sharpness fo Pre Enhance
00:0FF 10: X 1/4 00: BIRE 10:13IRE 00:0FF 10:1.61RE 0:4.2MHz 0:0FF
INIT:34H 01: x1/8 11 : X 1/2 01: QIRE 11 :161RE 01:0.81RE 11 :2.3IRE 1:3.3MHz 1:0N
03H SHARPNESS GAIN SHARPNESS SLICE LEVEL FBCLAMP FBCLMPEX
Sharpness Gain Adjustment Shrpness coring F/B CLAMP FB CLAMP mode
1000:(don't use) 1100:-3/16 0000:1/16 0100:5/16 0:Auto mode 0: External
1001:(don't use) 1101:-2/16 0001:2/16 0101:6/16 00:0.81RE 10:3.21RE 1 :Always ON l: Internal
1010:(don't use) 1110:-1/16 0010:3/16 0110:7/16 01 :1.61RE 11 :6.4IRE
INIT:FOH 1011z-4/16 1111:0FF 0011:4/16 0111:8/16
04H NOISE CANCEL GAIN FLTI FCTI SET DELAY
Gain Adjustment LTI fo CTl fo Cb and Cr Delay Adjustment
00:0FF 10: x1/2 0:3.3MHz 0:1.7MHz 0000:-296ns _ 1000: Center _ 1111 :259ns(37ns unit)
INIT:08H 01: X 1/4 11 : X 1 1:2.2MHz 1:3.4MHz
05H LTI GAIN LTI SLICE LEVEL CTI GAIN CTI SLICE LEVEL
LTI Gain Adjustment LTI Goring CTI Gain CTI Goring
00:0FF 10: X 1/4 00:0.81RE 10:3.21RE 00:0FF IO: X 1/2 00:0.4IRE IO: 1.6IRE
INlT:OOH 01:X1/8 11: X1/2 01:1.6lRE 11:6.4IRE O1: x1/4 11:X3/4 01:0.81RE 11:3.21RE
06H CONTRAST
Contrast Adjustment
INlT:40H 00h:x1/2 _ 40h:x1 _ FFh:x2.4
07H BRIGHTNESS
Brightness Control
INlT:00H 10000000:-128LSB _ 00000000:0LSB _ 01111111 :+128LSB(10bit)
08H CR OUTPUT GAIN CB OUTPUT GAIN
Cr Gain Adjustment Cb Gain Adjustment
INlT:00H 1000:X1/2 _ 0000:xl _ 0111:x1.4 1000:X1/2 _ 0000:xl _ 0111:x1.4
09H CR OUTPUT OFFSET CB OUTPUT OFFSET
Cr Output Offset Adjustment Cb Output Offset Adjustment
INlT:00H 1000:-8LSB _ 0000:O _ 0111:+7LSB (10bit) 1000:-8LSB _ 0000:O _ 0111 :+7LSB (1 Obit)
OAH HUE FP_FIL
HUE adjustment ( for NTSC signal) It; for Feed
1000000:-45" _ 0000000:0" _ 0111111:+43. 6° 0:0FF
INIT:01H 1 :ON
OBH HUE BIAS CLPFOF DCLAMP_VMASK
HUE bias adjustment (Adjustment for the demodulation phase of R-Y ( NTSC only) C Trap (burst ) V mask of digital
00000010° _ 111111 : +45° (for degital clamp) clamp
0 : OFF 0 : OFF
INIT:03H 1 :ON 1 :ON
OCH Y INPUT OFFSET BUS_DCOMTRP2 TOF
Offset adjustment for clamp Y input "flrepout Take off filter selection
1000:-31mV _ 0000:0mV _ 0111:+27mV 0:0FF 000:0FF,001:BPF,
INIT:00H 1:0N 010:MIN - 111 :MAX
[NIT:00H
OEH Y ClampPulse_F Y ClampPulse_W DIGITALY CLAMP
Phase adjustment of digital clamp for Y Adjustment of Clamp widthfor Y digital clamp Time constant of Y digital clamp
000:1.19ps - 111:3.26ps 000:0Sps _ 111:2.96ps 00:0FF 10:mediam
INIT:00H 01 :small 11 :Iarge
OFH CR INPUT OFFSET CB INPUT OFFSET
Offset adjustment for Cr input Offset adjustment for Cb input
INIT:00H 1000:-31mV - 0000:0mV _ 0111:+27mV 1000:-31mV _ 0000:0mV _ 0111:+27mV
* : Every blank register must be set 'O'.
Feb. / 2005
TOSHIBA TC90101FG
Sub D7 I D6 I D5 l D4 D3 I D2 I D1 I DO
10H CICLMPP_S CICLMPP_W
Adjustment of input clamp phase for analog Cb/Cr Adjustment of input clamp width for analog Cb/Cr
INIT:00H 1000:-1.185ps _ 0000zi0 _ 0111:+1.04/rs 1000:-1.185ps _ 0000:i0 _ 0111:+1.04ps
11H C CIampPulse_F C ClampPulseeW DIGITAL C CLAMP
Adjustment of digital clamp phase for Cb/Cr Adjustment of digital clamp width for Cb/Cr Time constant of Cb/Cr digital clamp
000:1.19ps _ 111:3.26115 000:0Sps _ 111:2.96/15 00:0FF 10:mediam
INlT:00H 01 :small 11 :Iarge
12H CONFIX COLOR KILLER LEVEL ACC LEVEL
Killer function Adjustment the sensitivity of the killer detection Adjustment ACC reference level
0: normal 000:Max _ 111:Min 0000: Min _ 1111 :Max CInitial:1000)
INIT:08H 1 :killer off
13H DOT DIST COMB+ 1LINE DOT COM443N CGAIN
Reduse dot ( Horizontal) Comb selection SECAME Y trap performance
00:0FF 10:x0.17 0:0FF 0:0FF for 443NTSC 000:0FF _ 111 : X 0.875(Intia|:011)
01:x0.16 11:x0.18 1:ON 1:ON 0:1HComb
[NIT:SBH 1:2H Comb
14H EXTERNAL SYNC SEPA LVL SYNC TIP CLAMP1 VSEPLVL VLMT HHKIL
Mode selection for external sync Sync sepa. Level Sync tip clamp mode for CVBS V sepa mode V sepa limit AFC V mask
00:OFF(internal) 10: CsyncL 0:30% 00:0N 10:AUTO1 0: 1/8 0:0FF
01:CsyncH 11:VsyncH 1:40% 01:0FF 11:AUTO2 0:5/16 l: 1/16 1:0N
INIT:1CH 1:1/2
15H SHCTRL MUTE C MUTE
Adjustment Horizontal phase reference picture mute Cb/Cr out mute
100000:-4.74/rs _ 000000: iOus _ 011111:+4.4ijs(1/6.75MHzAryp0 0:0FF 0:0FF
INIT200H 1 :ON 1 :ON
16H HDAMP1 HD GAIN1
Time constant 1 fpr H PLL(Phase difference: big) Loop gain 1 for H PLL(Phase difference: big)
[NlT:4EH 000: large _ 111 :small 00000:small _ 11111 :Iarge
17H HDAMP2 HDGAIN2
Time constant 2 fpr H PLL(Phase difference: middle) Loop gain 1 for H PLL(Phase difference: middle)
INIT:85H 000: large _ 111 :small 00000:small _ 11111 :Iarge
18H HDAMP3 HDGAIN3
Time constant 3 fpr H PLL(Phase difference: small) Loop gain 1 for H PLL(Phase difference: small)
iNIT:A6H 000: large _ 111:small 00000: small _ 11111 :large
19H HGCON12 HGCON21
Threshold level at the phase diffrence large to middle Threshold level at the phase diffrence middle to big
INlT:48H 0000:0FF _ 1111:High 0000:0FF _ 1111:High
1AH E N_NOISEH_S EN_NOISEH_W EN_NOISEV_W
Adjustment start phase for noise detection Adjustment the width for noise detection Noise detection line numbers
000:32.2uS _ 100:36.9uS _ 111:40.5uS 000:9.4uS _ 100: 14.1uS _ 111:17.7uS 00: 1H 10:3H
INIT:90H 01 22H 11 :4H
1BH EN_NOISEV_S FLOCK VSRACH
Adjustment start line for noise detection HPLL Gain at lock fsc lock period
000:0H _ 111:+15H 0:1/2 00:3V 01:4V
60Hz: line 7 is as 0H 1:no change 10: 5V 11 :6V
iNIT:00H 50Hz: line 4 is as OH
1CH HDPH VDPH
Adjustment horizontal phase for digital output Adjustment Vertical phase for digital output
INIT:00H 1000:-1.185uS _ 0000:0uS _ 1111 :+1.04uS 0000:0H _ 1111 :+15H
1DH EN_PlXH_S EN_PlXH_W
Adjustment start phase of horizontal signal processing Adjustment width of horizontal signal processing
INIT:00H 1000:-1.185ps _ 0000:cemter _ 0111:+1.04us 1000:-1.185us _ 0000:centee 0111:+1.04us
1EH EN_PlXV_S EN_PlXV_A COMB KILL
Adjustment start phase of vertical signal processing 000:0FF 011 :1--23H 110: 1~26H
0000:line 10 _ 1111: line 25 0:Manual 001:1-21H 100:1-24H 111:Auto
[NIT:07H 1:Auto 010: 1 -22H 101 :1-25H (60:22H,50:23H)
1FH HBLK_S HBLK_W
Adjustment start phase of horizontal BLK Adjustment width of horizontal BLK
iNIT:00H 1000:-2.37ps _ 0000::0 _ 0111:+2.27us 1000:-2.37tts - 0000:i0 _ 0111:+2.27us
* : Every blank register must be set T''.
Feb. / 2005
TOSHIBA
TC90101FG
Sub D7 I D6 I D5 I D4 D3 I D2 I D1 D0
20H BFP_S VBlVAD[220] CLP
Adjustment start phase of burst gate Adjustment the pase of l/BI data slice 16LSB limit
0000:center _ 1111 :+4.44y s 100:-4H-000:center ~11123H 0:0FF
INIT-OOH (0.296 u s step) 1-ON
21 H VPHS HDST BYFOFF BCFOFF
Adjustment start phase of V at THRHV=1 Delay adjustment of HDOUT BSRY filter BSRC filter
110:384W 011:192W 000:0W 10:40w 00:32w
111:don't use 100:256W 001:64W 11:44w 01:36w 0:ON 0:0N
INIT:03H (1W:27MHz) 101:320W 010:128W (1W:27MHz) 12OFF 120FF
22H PHPOLE PVPOLE PFPOLE THRHV INVCK SEL_BLK YOLEVEL
HDOUT polarity VDOUT polarity Field polarity H,V-OUT through CKOUT polarity V.BLK processing 1/1.71875
Y output amplitude
Ozactive 0:active 02active 0: 656 Ozactive 0: normal 0: 1.71875
INIT218H 1:negative 1:neeative 1:neeative l: through 1:nezative 1:through 121.0
23H RBCHG VD_DET FIELD_DET EXVDF
Cb/Cr phase Control VDOUT Field Det. Adjustment Ext VD phase
0:normal 00: Free run at no -sig. 000:center 011:+5.96us 110:-3.97us
l:change 01:Fixed mode 50/60 ( on TVM2) 02AUTO 001 :+1.99us 100:-7.94us 111 :-1.99us
102Fixed mode at MANUAL mode 1:Fixed Low 010:+3.97us 101:-5.96us
11 :Fixed mode for MANUAL mode &
INIT:00H no sig at AUTO mode
24H FLDTMSEL VCTOLE VCRESET AFC_Cont SEL_RDATA
Adjustment horizontal phase for field detection V count V count reset AFC control Start phase of 110 read registers
000:-5.7ps 011:-13.2ps 110:-20Sps
001:-8.2trs 100:-15.7trs 1112-23.2us 0:-H/8 _ +H/4 02OFF 02OFF 00:CDEC 01:CCD
INIT:80H 010:-10.7tts 101:-18.4tts 1::H/8 1:ON 120N 10:IDI 112WSS
25H AXD_HON AXD_VON AXD_SSEL AXD_HSEL[4:0]
data insert of H data insert of V data incert Line number for incert data
for 601 format NTSC 2 21/284 line + AXD_HSEL
0:0FF 0: OFF Ozincert to CbCr PAL8t 2 24/337 line + AXD_HSEL
INIT:00H 1:0N 1:ON 1:incert to Y
26H AXD_VSEL[320] DID[320]
Line number for insert data to Field BLK For DID code
NTSC 2 1|ine+AXD_VSEL
INIT200H PAL : 1|ine+AXD_VSEL
27H SDID[720]
For DID code
INIT200H
28H CSONTIM CSOFTIM strp_idg_wd[1] I strp_idg_wd[0] strp_idg_|v[1] I strp_idg_|v[0]
Adjustment histerisis for Adjustment histerisis for Adjustment mask periode Sensitivity of
Color stripe detect ON Color stripe detect ON for color stripe detection color stripe detection
002OFF 1022.05 00:0FF 1021.05 00:100lk 10:20clk 00: Low _ 11: High
INIT:00H 01:1.0s 11:3.0s 01:0.5s 1121.45 01 :1 5clk 11:30clk
29H CPSON AGCWID PSEWID PSEMOD PSLICEL
Color syripe Adjustment AGC Adjustment Pseudo Pseudo H sync; Slice level for pseudo H sync
detection detection periode periodeof H detect detection
0:0FF 0:2.3~3.2/.l S(D1) 0:1 .3~2.7u S(D1) 00:20% 01:25%
1:ON l: 2.0-3.5 u S(D1) l: 1.0~3.0u S(D1) 0:0FF 10:40% 11:60h
0:1.1~1.7Ll S(D2) 0:0.9--1.3tsS(D2) 1:0N
INIT:3AH 1: 1.0-1.8 u S(D2) l: 0.8-1.4u S(D2)
2AH PALPFON PASEL AGCMOD ASLICEL AGCHYS
LPF for AGC AGC AGC ulse . ' Adjustment of histerisis time
pulse & pseudo Hsync detection detecption Adjustment of slice level for AGC Puls for AGC pulse detection
H sync detection
02OFF O: after AGC 02OFF 00260% 01270% 002OFF 01:0.4s
INIT:DAH 12ON l:befor AGLC 12ON 10:80% 11:90h 1020.75 11:1.0s
2BH PAGCON PKLlM AGCLPFON PATTK PSLP
Peak AGC Peak AGC limit level fsc Trap Filter Adjustment Peak AGC Atack time Sesitivity for Peak detection
0:0FF 00:105% 10:115% 0:0FF 00: fast-ll :slow 002big~112 small
INIT:1AH 1:0N 01:110% 11;120% 1:ON 0121/4 1121/8
20H SAGCON SATTK SSLP
Sync AGC Adjustment Sync AGC Atack time Adjustment Sync AGC recovery time
0 : OFF 00: fast-ll :slow 00:fast-11:slow
INIT:0FH 1 :ON
2DH CLPFON CSLICES CSLICEL IRTIMS CSTMOD CCDMOD
LPF for CCD CCD slice Adjustment fixed slice level Phase for ID1 sensitivity of COD Field selection for CCD data slice
function mode detection start bit
0:0FF 0:Auto slice 00:416LSB 01:496LSB O:i0.6,u s 02big 00:0DD 01:EVEN
[NIT280H 1:ON 1:Fixed slice level 10:296£B 11:336ULB, 1:1;211 s 1:small 1&th Field 11 :Both Field
2EH ILPFON ISLICES ISLICEL IRWIDON IEDGES lPHASES
LPF for ID1 ID1data slice Adjustment fixed slice level for ID1 Det. for amplitude Phase adjustment Adjustment the sampling pase
data slice function mode of IDlsignal forID1det. for ID1
0:0FF 02Auto slice 00:480LSB 01:592LSB 0:80LSB 0:Adaptive mode 020 12-1
INIT280H 1:0N 1:Fixed slice level 10:312LiB, 11 :368LSB 1:0FF 1:Fixed mode 22+2 32+1
2FH WLPFON WSLICES WSLICEL WSTMOD WSSMOD
LPF for WSSI WSS data Adjustment of the slice level WSS SC Field selection for
data slice slice mode for WSSdata det. Mode WSS data slice
0 ." OFF 0:Adaptive 00:512LSB 01:640LSB 0:sensive 00:0DD 012EVEN
INIT:88H 1:0N 1:Fixed mode 10:320LSB 11:384LSB 1:Slow 10:Both Field 11 :Both Field
*:Everyblankregistermustbeset"0".
Feb. / 2005
TOSHIBA TC90101FG
D7 I D6 I D5 l D4 D3 I D2 I D1 I DO
30H CCDDLY ID1DLY
Phase adjustment for CCD data slice Phase adjustment for IDI data slice
0000:min _ 1000:center _ 1111:max 0000:min _ 1000:center _ 1111:max
INIT288H ISTEP = 128fh ISTEP = 128fh
31 H WSSDLY CDECEV1[4] YADFILON FILON1 FILONO
Phase adjustment for WSS data slice fsc pull in 13.5M trap [IR FILTER IIR FILTER
0000:min _ 1000:center _ 1111:max performance for ADC selection ON/OFF
ISTEP = 128fh 0:Nornal 0: OFF 0:FIL1 0:0FF
INIT:84H 1:Wide 1 :ON 1:FIL2 1:0N
32H PROG BUS_FBCLMOD
D1/D2 Time constant of thelnternal
detection Manual set feed back clamping
0 : Manual 0 : D1 00 : Reference 01 :Large
INIT:80H 1 :Auto det. 1 :D2 10:Small 11 :Mid
33H MGAINSL MGAIN
tinit 33': Adjustment for GCA Gain
0: OFF
INIT:00H 1 :ON
34H CGP_S CGP_W
Adjustment start phase of output pulse of CGP Adjustment pulse width of CGP
1000:-1.185p s _ 0000: to _ 0111:+1.04/1 s 1000:-1.185/1 s _ 0000: :0 _ 0111 :+1.04/1 s
INlT:00H 0000: Sync center + 3.7 11 s 0000 : center( 2 11 s)
35H DET4VAL SYNC TIP CLAMP2
Clamp control
Threshold level for DET. 443 00:ON 10:AUTO1
[1000:MlN0000:CEN0111:MAX) 0 1 01 OFF 11:AUTO2
INlT:07H
36H CGPOUTM BUS_DCOMTRP1 BUS_ENPIXOFF
CGP OUT DCOMB OUT Mute
control C Trap
O:auto 0:0FF 0:ON
INIT:00H 1:forced ON 1 :ON 1 :OFF
37H BUS_YNCCK BUS_YNCLV BUS_YNCGA BUS_YNCON BUS_CKILLLV BUS_CNCLV BUS_CNCGA BUS_CNCON
Y NOISE Y NOISE LIM Y NOISE GAIN Y NOISE CKILL Gain C NOISE LIM C NOISE GAIN C NOISE
0:4LSB 0: X 1/2 0:0FF 0:Center 0:4LSB O: X 1/2 0:0FF
INIT:00H 1:8LSB 1:X1 1:0N 1:+3dB 1:8LSB l: X 1 1:ON
Feb. / 2005
: Every blank register must be set "O".
TOSHIBA TC90101FG
IIC BUS Read Data
Sub D7 D6 D5 D4 D3 D2 D1 DO
DET50 NOSIG NOVP FIELD UNLOCK H/VSTD progressive
Field Frequency Signal det. V-Sync Sep Field indication HPLL for inpit sig H-V std. det. DI/D2 det.
A-1 0:60Hz 0:Signal det. 0:V sig det 0:ODD OZLOCK Ozstd. 0 O:D1
1:50Hz 1:no signal 1:no V sig 1:EVEN 1:UNLOCK 1:non-std. 1:D2
DET443 PALDET SECAMDET FSC_SEL CKILL FSCLOCK
4.43MHz det. PAL det. SECAM det. fsc detection Killer det. fsc lock det.
A-2 Oznon 0:non 0:non 00:3.579545MHz 01:3.575611MHz 0:Color 0 0:unlock
1:Det. 1:Det. 1:Det. 10:3.582056MHz 11:4.433MHz 1:White&black 1:lock
NOISE_0UT7 NOISE_0UT6 NOISE_0UT5 NOISE_0UT4 I NOISE_0UT3 NOISE_0UT2 NOISE_0UT1 NOISE_0UTO
S/N detection
A-3 0000_0000:Strong signal - 1111_1111:Weak signal
(MSB) (LSB)
H_Cont[7] I H_Cont[6] I H_Cont[5] I H_Cont[4] l H_Cont[3] I H_Cont[2] I H_Cont[1] I H_Cont[0]
information of H counter numbers for IV periode
A-4 10000000:Min 00000000 Typ 01111111 Max
COLSTYPE COLSDET Color, S_DET AGC DET
Color stripe Color stripe det. Psuedo Sync det. AGC Pulse det.
A-5 OEIIE 0:TYPE2 0:non O:non 0:non 0 0 0
1:TYPE3 12det. 1:det. 1:det.
[IR CCD[7] [IR CCD% IIR CCD[5] IIR CCD[4] IIR CCD[3] 11R CCDC2) IIR CCD[I] IIR CCD[O]
CCD CR1 det. Start bit det. CCD sliced data
B-1 0:under 3ck 0:NG
1 :upper then 3ck 1 :OK (LSB)
IIR CCD[15] IIR CCD[14] IIR CCD[13] I IIR CCD[12] I HR CCD[I 1] I HR CCD[10] I HR CCD[9] I HR CCD[B]
CCD sliced data
[IR CCD[23] I 11R CCDr22) IlR CCD[21] IIR CCDr20) I lIR CCD[19] I "R CCD[18] I IIR CCD[17] IIR CCD[16]
CCD sliced data Field information Numbers of CR1
B-3 0:ODD 0
(MSB) 1:EVEN (MSB) (LSB)
HRCCDBH I nRCCDBm HRCCDBM "Rocomw l nRCCDmn I nRCoDmm l chcoma HRCCDRH
information of COD slice level
(MSB) (LSB)
IIR ID1[7] IIR ID1 [6] [IR ID1 [5] I IIR ID1[4] IIR ID1[3] I 11R ID1 [2] I HR ID1 [1] I 11R lD1[0]
Reference sig. det. CRC code det. WORDO(sliced data) WORD1(sliced data)
C-I 0:NG 0:NG
1:OK 1:OK (ESB)
IIR lD1[15] [IR lD1[14] IIR ID1[13] I IIR ID1[12] IIR ID1[11] I IIR ID1r10) I IIR ID1[9] I IIR lD1[8]
WORD2(sliced data)
IIR ID1 [23] I HR lD1[22] I HR ID1[21] I HR ID1 [20] l HR ID1 [19] I HR IDI [18] HR lD1[17] 11R ID1 [1 s]
CRCC(sliced data) Field information
C-3 0 0:ODD
HRID1[31] l HRID1[30] I HRID1[29] l HRID1[28] l HRID1[27] I nR101[26] HRID1[25] uRID1[24]
information of IDI slice level
(MSB) (LSB)
IIR_WSS[7] IIR_WSS[6] IIR_WSS[5] I IIR_WSS[4] I IIR_WSS[3] I 11R_wss[2] I 11R_wss[1] I HR wss[o]
RUN-IN det. START CODE det. WSS(sliced data)
D-1 0:NG 0:NG
1:OK 1:OK (LSB)
llR wss[15] lIR_WSS[14] 11R_wss[13] I IlR_WSS[12] l IIR_WSS[11] l lIR_WSS[10] I |[R_WSS[9] I ][R_WSS[B]
WSS(sliced data)
HRJNSSDS] nijssmz] nR]~ssn1] I HRJNSSDO] l HRJNSSUQJ l IHLWSSUB] I HRJNSSD7] l Iwzwssne]
Bi phase det. Field information information of WSS slice level
D-3 0:NG 0:ODD
1:0K 1:EVEN (MSB) (LSB)
Feb./2005
SEL RDATA
IIC read data
TOSHIBA TC90101FG
OAdditional information about il0 registers.
BUS address Function Contents
00H: D7-06 Inputsignalselection. An input signal is chosen
00H: D5-02 Select TVM. The TV-system is fixed forcibly.
it uses when it is worked in the manual.
00H :01-00 Color systenldetection Setup Color system detection mode
mode. Manual / Europeian / South American / Full auto detection
01H :07 Setup for TOS. 3-IineComb or BPF is chosen
0: 3-line-0omb 1: B.P.F
01H: D5-04 Select clock Setup for an output clock frequency
Select "601 :13.5MHz” or "656: 27griz''.
01H: 03 Select OUTPUT FORMAT Setup for an output format (601or656).
01H: 02 Select OUTBITS Setup for an output bits range (8bit or 10bit)
01H :01 Digital-Output Control Each digital output terminals are controlled.
0: Active l: OPEN (Because it becomes Hi Impedance,
coexistence with other 10's is possible.)
01H :D0 AOC-power Control The control of the power supply for hoo
0: The power supply of A00 is turned off.
l: Normal (It usually uses by this setup.)
02H: D7-06 Set V Enhance Gain Gain (off, 1/8, 1/4 and 1/2) is set up.
02H: D5-04 Set V Enhance non- Setup the characteristic of M-enhance gain for non- correlation
liner point. Component. Choose it from 4 point
02H: D3-02 Set V Enhance coring Choose Coring(No response level).
02H :01 Set "fo'' of sharpness Set f0 of Sharpness
It works with f0 of Noise-canceler as well together
02H: D0 Select Pre-Enhance Pre-Enhance makes it control the part Edgy of Sharpness.
03H: D7-04 Adjustment Sharpness Control the Gain of Sharpness
Gain. 1011: -1/4 ' 1111: OFF ' 0111: 8/16
1000, 1001 and 1010 can't be used.
03H: D3-02 Set Sharpness-coring Choose C0ring(No response level).
-Level.
03H :01 Set the Feed-Back Set the Feed-Back CLAMR
CLAMP o: Auto. It becomes a diode clamp when T090101FG detects a
non-signal. l: Feed-Back Clamp is active
03H: DO Change the Feed-Back Select Internal-Feed-Back or ExternaI-Feed-Back
CLAMP 0: External mode (Pin74, 75 outputs clamp signal).
1: Internal mode (Pin74, 75 2 Open). The time-constant for
internal feedback clamp is set via BUS_FBCLMOD at sub address 32 hex.
04H: D7-06 Set Noise canceler Set the Gain of NOISE-CANCEL.
04H: 05 Set LTI f0 Set the to of LTI.
04H: 04 Set CTI f0 Set the fi) of CTI.
04H: D3-DO Cb & Cr delay adjust. Fine tune for delay of (lb (l Cr.
Step is 37[ns] between -296ns-259ns.
But step is 74[ns] at YCbCr input mode.
05H: D7-06 LTI Gain adjustment it set the Gain of LTI.
05H: D5-04 LTI coring Level It set the Coring(No response level) of LTI.
Use after you confirm a picture.
05H: D3-02 CTI Gain adjustment It set the Gain of CTL
05H: DI-OO CTI coring Level It set the Coring(No response level) of CTI.
Feb./2005
TOSHIBA
TC90101FG
BUS address
Function
Contents
06H: 07-00 Contrast Adjustment It set the Contrast. (Reference value: [01000000])
Mariabilityis x0.r-x2.4.
(When use big value and inputs big amplitude signal,
It takes place over range of internal circuit.)
07H: D7-DO Brightness Adjustment It set the Brightness.
Variability is -128LSB - +128LSB.
08H: D7-D4 Cr Gain Adjustment It set Gain of Cr. (Refrence value [0000])
Mariabilityis x0.5-x1.4.
(When use big value and inputs big amplitude signal,
It takes place over range of internal circuit.)
08H: D3-D0 Cb Gain Adjustment It set Gain of Cb. (Refrence value [0000])
Variability is x0.5-x1.4.
(When use big value and inputs big amplitude signal,
It takes place over range of internal circuit.)
09H: D7-D4 Cr Output OFFSET adjust. Fine tune for offset of the Cr at output stage.
09H: D3-D0 Cb Output OFFSET adjust. Fine tune for offset of the Cr at output stage.
OAH: D7-D1 HUE adjustment HUE adjustment at the NTSC input mode.
Variable is -4!P-r43.6 o.
OAH: D0 Filter for feed-back Setup BPF for feed-back-clamp. [1] ON © OFF
Normaly It must be set "
OBH :07-02 HUE Bias adjustment Fine tune hilE-Bias at the NTSC input mode
Variable is 0°~v+45°
OBH: D1 C Trap for dirital clamp. It is C-Trap for DigitaI-clamp of Y. [1] ON [0] OFF
Use [1] at the digital-clamp-mode.
OBH: D0 M-mask of digital clamp Setup of the digital clamping at M-Blk period.
[1]: Clamp OFF [0]: Clamp 0N. It usually uses on "
OCH: D7-D4 Offset adjustment for Offset adjustment for T signal at Analog-input.
clamp Y-input Use with 0[mV] when you use with digita-clamp.
OCH: D3 C-trap of D-001& Setup C-trap for T at Digital-COW-block
(I): ON [0]: OFF. This setup can reduce Cross-color and beat.
OCH: D2-DO Take off Filter select Setup fake-off-Filter
Take-off-Filter is put in front of Decoder. 000: OFF, 001:
ITF, 010~111 : TOF (TOF1~TOF6)
When BPF is set up, it can't get the effect of TOF.
0EH: D7-05 Phase adjustment of Digital-clamp is put by input-Y-signal
Digital-clamp for Y. Adjustment of the phase of Digital-clamp-pulse for T.
Reference value [011].The variable is about 0.3rps) step
0EH: D4-D2 Adjustment of clamp- Adjustment of the width of DigitaI-clamp-pulse for Y.
width for T-digital Reference value: [011].Variab|e is about 0.3rps) step
-clamp
0EH :01-00 Time constant of T- It can select 0N/0FF of 0igital-clanp-T. And adjustment of
DigitaI-clamp time constant of DigitaI-clamp-Y.
OFH: D7-D4 Offset adjustment for Adjust the offset of the Cr at input by YCbCr signal.
Cr-input Use with 0[mV] at the time of Digital-clamp.
Variable is -310nV] ' +27[mV].
OFH: [)3-00 Offset adjustment for Adjust the offset of the Cb at input by YCbCr signal.
Cb-Input Use [0000] at the DigitaI-clamp mode.
Variable is -31rn)l] _ +27[mV].
10H: D7-04 Adjustment of input Adjust the clamp-phase of Cb/Cr at YCbCr signals.
clamp phase for Cb/Cr
It usually uses on BUS [0000].
Feb./2005
TOSHIBA TC90101FG
BUS address Function Contents
10H: D3-DO Adjustment of input Adjust the clamp pulse width of Cb/Cr at YCbCr signals.
clamp width for Cb/Cr
It usually uses on BUS [0000].
11H :07-05 Adjustment of digital Adjust the digital-clamp-phase for C/ob/or.
-c|amp-Pu|se-phase for (S-Video/YCbCr inputs.)
C/Cb/Cr It usually uses on BUS [011].
11H ..04-02 Adjustment of digital Fine tune the digital-clamp-pulse-width for C/ob/or.
Clamp-pulse-width for (S-Video/Yah inputs.)
C/Cb/Cr It usually uses on BUS [011].
11H :D1-DO Time constant of C- This is adjustment of time constant of 0igital-clap-0
DigitaI-clamp It can set ON/OFF and three-kinds
12H: D7 Setup killer function Setup color killer function
[0]: Active (normal) [1]: Killer become OFF always
12H: D6-04 Level of color-killer Level of color-killer-ON is set up. [000] killer sensitivityis
max.[111]1 killer sensitivity is minimum.
12H :03-00 A00 reference Level Reference-Ievel of ACC(auto color control) is set up
Level by ACC becomes smallest when it is set up in 000.
13H: D7-06 Reduce fi-dot Setup of dot-reducer at the horizontal edge
When it is turned on, dot of the part of H is reduced.
13H :D5 Setup Comb+ It has an effect as below for PAL system.
When the horizontal lines of the front and the rear have color
and edge element,and the horizontal line of center has no color,
it drops Y signal level for calculated result. Therefore it
occurs dots of black in spite of white and gray picture When
COMB+ is on, it can decrease this noise.
It usually uses ON, when PAL signal.
13H :D4 1 LINE DOT Setup of 1LlrlE-DOT-improver in the TOS block. [1] ON [0]:0FF
It can reduce the dot,when only I-line has a color signal.
13H :D3 443NTSC Comb control Comb control in 443NTSC is changed. [1] 2h comb [0] lh comb
Cross-color will reduce when 2H-Comb is selected.
13H: D2-00 SECAM Y trap setup Setup Y-trap performance for SECAM
TC90101FG SECAM Trap Freauencv Response
Feb./2005 23
TOSHIBA TC90101FG
BUS address Function Contents
14H: 07-06 Selection for lt select the input signal of Composite-SOO-in of Pin-33
externaI-sync
[00]: OFF(lnternal) Pin33 must be connect to GND.
[01]: External composite Sync mode (polarity: High)
[10]: External composite Sync mode (polarity: Low)
[11]: External ll-Sync mode (polarity: high)
14H: D5 Sync Separation level Level of Sync-sepa is set up
Initial value is [0]:30%.
14H: D4-03 Sync-tip-clamp-mode for it set the control of clamp.
(h/BS [00]: Sync tip clamp ON [01]: Sync tip clamp OFF
[10]: MjT01(Sync-tip-clanping becomes activity, When it
detect non-signal or pedestal has a big difference.
[11]: AUT02 (Sync-tip-clamping becomes activity, When it
detect non-signal.
14H :D2 Setup for 1/-sepa Setup for 1/-sepa
0: Type 1
1: Type 2 (Type 2 is more effective than Type1 )
14H :D1 1/-sepa limit Limit of 1/-sepa is set up
1/-sepa becomes easy, when it is set up in 1/16.
But,0sually use with 0(1/8)
14H: D0 Setup of Half-h-killer It count HaIf-H at the V period.
[0]: OFF (Initial value)
[1]: ON (It is effective for top-curl problem of non-standard
signa|.(VCR trick mode etc--)
15H: D7-D2 horizontal phase Reference-Horizontal-counter of internal is set up
reference This register is reference timing for all of internal
function. Usually, it uses with 0[pS].
15H :D1 Picture MUTE [0]: Normal [1]: Picture Mute 0N
15H :D0 Cb and Cr MUTE [0]: Normal [1]: Color signal Mute 0N
16H: D7-05 Time constant 1 for HPLL it is tine-constant of PLL.
(Phase difference:big) It becomes active when the phase difference has big value.
Reference value: [010]
16H :04-DO Loop Gain 1 for HPLL it is Loop-tlain of PLL
(Phase difference big) it becomes active when the phase difference has big value.
Reference value: [01110]
17H: D7-D5 Time constant 2 for HPLL It is time-constant of PLL.
(Phase difference middle) It becomes active when the phase difference has middle value.
Reference value: [100]
17H: M-DO Loop Gain 2 for HPLL it is Loop-(lain of PLL
(Phase difference middle) It becomes active when the phase difference has middle value.
Reference value: [01101]
18H: D7-05 Time constant 3 for HPLL lt is tine-constant of PLL.
(Phase difference:small) It becomes active when the phase difference has small value.
(it means under stable.)
Reference value: [101]
18H: D4-D0 Loop Gain 3 for HPLL It is Loop-Gain of PLL
(Phase difference small) It becomes active when the phase difference has small value.
Reference value: [00110]
Feb./2005 24
TOSHIBA TC90101FG
BUS address Function Contents
19H: 07-04 Threshold level at the Threshold level that Phase-diffrent changes from Big to middle
phase difference big is set up.
to middle Recommendation value: [0100]
19H: D3-DO Threshold level at the Threshold level that Phase-diffrent changes from middle to
phase difference middle Big is set up.
to big Recommendation value: [01000]
1AH: D7-D5 Start phase for noise The horizontaI-start-phase of the detection of Noise is set up.
detection "Point of 5.3pS from sync" is center
1AH: D4-02 Width for noise The horizontal-width of the detection of Noise is set up
detection The amount of noise-detection changes by Width.
When width is widened, detection sensitivity rises
1AH: D1-D0 The number of horizontal It is the numbers of lines which Noise is detected in.
lines which Noise is The number of line's can be set up from Ill to 4H.
detected in
1BH: D7-04 Start line for Noise The vertical start line of the Noise detection is set up.
detection 60Hz: 7-Iines as Oh It is set up in 1 line unit
50Hz: 4-Iines as 0H.It is set up in 1 line unit.
1BH :D2 l-PLL-Lock-tlain The fsc Lock-tlain is set up
Usually used with 1/2.
1BH :01-00 fsc lock period Lock-period of fsc is set up
Search-time becomes long, when it is set up ~6V.
But, it is easy to pull in
1CH: D7-04 Horizontal phase for The position of EAV&SAV is set up
digital format Usually, it uses with initial-value:0rus]
10h :03-00 Vertical phase for M-phase of VD is set up when "H/V OUT through"
digital format Variability of M-phase is the lh unit
1DH: D7-D4 Start phase of The horizontal start phase of the picture-processing-period is
Horizontal signal set up. The picture-processing is set up with COMBKILL
processing (1EH D2--00).
1DH :03-00 Width of Horizontal The horizontal width of the picture-processing-period is
signal processing set up. The start reference is a horizontal start phase
Make adjustment after start-setup
1EH: D7-04 Start phase of vertical Thevertical start lineof thepicture-processing-period isset
signal processing up.It becomes MUTE to the setup from the vertical start line.
1EH :D3 The setup of the vertical AUTO or MANUAL is selected.
picture processing MANUAL 2 It becomes the value that it is set up with 1EH(D7-D4).
AUTO: 60Hz= from 10th line / 50Hz= from 23th line
Picture-processing is started from each line.
1EH :02-00 Setup of COMBKILL period The period of COMBKILL is set up
This period doesn't do picture processing.
A0T0:60hz--1--22h, 50hz--1-23H
But, it is a mask period to 21H by the Y/C input of 60Hz and
the YCbCr input of 60Hz.
1FH: D7-04 Start phase of The start phase of hi-BLANK-PIC} is set up
horizontal BLK Usually, it uses with initiaI-value 0[us]
1FH: D3-D0 Width of Horizontal BLK The width of H-BLANK-PULSE is set up.
Usually, it uses with initial-value:0rusl.
20H: D7-04 Start phase of burst gate The start phase of BljRST-(lhTE-POLSE is set up.
Feb./2005
TOSHIBA
TC90101FG
BUS address
Function
Contents
20H: DO-DI Set line of VBI data The line of MBI-data-slice is set up.
slice Usually used with center.
When it uses at the outside synchronism, it uses for the
adjustment,whenthephaseoftheoutsidel/0-pulseandtheinput
signal are shifted. VBI and Macrovision detection line move at
the same time, too.
20H: D0 16LSB limit It limit less than 16LSB at the Digital output.
Use by ON, when you use with 601/656 output.
21H: D7-05 Start phase of ll at The phase of VD is set up.
THR-V Bus 111 can't be set up.
21H: D4-D3 Delay adjustment of When Thru of V, Set the delay of HD-Pulse The variability is
HD-OUT 32W~v44W (1W=27MHz).
21H: D1 BSRY filter It usually uses on ON.
21H: D0 BSRC filter It usually uses on ON.
22H: D7 HD-OO of polarity The polarity of the HI) output is chosen
22H: D6 I/D-OO of polarity The polarity of the Ill) output is chosen
22H: D5 Polatity of Field The polarity of the Field output is chosen
22H: D4 hi/v-OO} through ri/l/Ah" in 601 output is chosen
656: H/V-pulse equal to 656.
Through: hi/v-pulse equal to the input signal.
22H: D3 Polarity of CKOUT The polarity of the CKOUT is chosen
22H: D2 V.BLK processing Processing of 1/-Blanking is chosen
it usually uses on OZNORMAL.
The period of blanking in NORMAL are Y=16LSB (8bit) and
C=128LSB (8bit). Through is for the test.
22H :D1 Y output Amplitude The amplitude of the Digital output is changed.
it usually uses on 0 1.71875. "I'' is for the test.
23H: D6 Cb/Cr phase The output of Cb and Cr can change.
0: Digital Format Normal
l: change
23H: D5-04 50/60Hz MO cotrol Ill) output is controlled. (It becomes effective when it is set
up in 601 output.)
00 :Free run
01: It is fixed on 50 or 60 on non-signal
Frequency to fix depends on TVM2.
IO: imenvideo-system islWl0hLcontrol, asetup isalwaysfixed
on TVM2.
ll :It is always fixed on TVM2 at MANUAL.
It is fixed on TVM2 at non-signals
23H: D3 Field Det on non-signal The detection of Field is set up on non-signals
23H: D2-00 Ext vo phase It is A phase in the external-MD-input.
Variable is -7.94[Lts] - 5.96[izs]
24H: D7-D5 horizontal phase for It is H-phase of FieId-detection
field detection it is the phase margin. Use with Bus 100.
24H: D4 V count it is the allowable range of Il-counter.
It can set margin of "V-Sep phase and h-counter"
It usually uses on 0.
24H: D3 V count reset it is the specifications of reset of M-counter
When ON, It can reduce field-miss-detection.
It usually uses on ON.
Feb./2005
TOSHIBA TC90101FG
BUS address Function Contents
24H: D2 AFC leak control It is Leak-control in the AFC circuit
It usually uses on OFF
24H: 01-00 The order of read Data It can change order that Read-data.
00: ABCD
A: Detection, B: COO, C: lol, D: BSS
BUS: 01--B0AD, BUS: 10--0AB0, BUS: 11=DABC
25H: D7 Data insert of H It insert Read-data to the H period of the output
Data is inserted after EAV at 656
Data is inserted same place with 656 at 601.
25H: D6 Data insert of ll it insert Read-data to the V period of the output
Data is inserted after EAV at 656
Data is inserted same place with 656 at 601.
25H: D5 Data insert for 601 Data can insert on either of Y or CbCr at 601 output.
Data cannot insert both line
25H: M-DO Line number for insert Set line which Read-Data insert.
Data. lt can set each 1-Iine for Ibit.
26H: D7-D4 Line number for insert Set |ine(in Field-Blanking) which Read-Data insert.
Data in field blank. it can set each I-line for Ibit.
26H: D3-DO For DID code This setup is DID code
27H: D7-DO For DID code This setup is Dll) code
28H: D7-6 Histerisis for color It is Histerisis of the Color-stripe-detection.
stripe detection If takes the long time, detection-time increase
But, miss-detection decreases.
28H: D5-04 Histerisis for color it is Histerisis of the Color stripe detection-OFF.
stripe detection if takes the long time, detection-OFF-tine increase
But, miss-detection decreases.
28H: D3-D2 Mask period for color It is the detection period of color-stripe.
stripe detection It is judged in more than the setup period
28H: DI-OO Sensitivity for color It is the detection sensitivity of color-stripe.
stripe detection it is judged in more than the setup
29H: D7 Color stripe detection it set ON/OFF of color stripe detection
29H: D5 MO detection periode it is the Pulse width of the Mi) detection.
29H: D4 Pulse width of Pseudo lt is the Pulse width of the pseudo-sync pulse.
29H: D2 Pseudo H sync detection It set ON/OFF of pseudo H sync detection.
29H :01-00 Slice level for pseudo H It set slice level of pseudo H sync
2AH: D7 LPF for hilt) pulse & it set ON/OFF of LPF for MO pulse (l pseudo H sync detection
pseudo H sync detection
2AH :06 Route change of AGC pulse It is Route of “AGC pulse & pseudo H sync"
& pseudo H sync Switching of Route is before and after the AGC circuit
2AH: D4 Mo Pulse detection it set ON/OFF of MO Pulse detection.
2AH: D3-02 Slicelevel forAGCpulse it set slice level of AGC pulse.
2AH: DI-DO Histerisis time for AGC it set histerisis-time of MO pulse detection.
pulse detection
28H: D7 Peak MO ON/OFF It set ON/OFF of peak AGC
28H: DG-D5 Limit level of Peak AGC It set Limit level of Peak Mo.
28H: D4 fsc Trap Filter It set ON/OFF of fee Trap Filter.
2BH: D3-D2 Peak MO attack time It set Peak MO attack time.
Feb./2005 27
TOSHIBA
TC90101FG
BUS address
Function
Contents
2Bh: DI-OO An integral coefficient lt is the integral-coefficient of Peak hilt) detection.
of Peak AGC detection
20H: D7 Sync MO It set ON/OFF of Sync AGC.
20H: 03-02 Sync MO attack time It set Sync MO attack time.
2CH: DI-DO Peak/Sync MO recovery it set recovery time of Peak MO and Sync MIC.
2DH: D7 LPF for COO it set ON/OFF of LPF for COO
2DH: 06 COO slice function mode it set mode of COO slice function
Level changes by the input amplitude,when Auto mode.
20h: D5 CCD slice level It set COO slice level.
it is effective when 2DH D6 is set a fix.
2DH: D3 Phase width of iOl it set phase width of 101 detection
detection
20h: D2 COO Start bit detection It is the detection sensitivity of the start bit of COD.
2DH: Dl-DO Select CCD field It set field that detect CCD
2EH: D7 LPF for lol It set ON/OFF of LPF(Input stage of ID1-detection circuit)
2EH: D6 ID1 data slice function It set lol data slice function
When Auto slice,s|ice level changes by the input amplitude.
2EH: D5-04 IDI slice level It set ID1 slice level.
lt is effective when 2EH 06
2EH: D3 Detection for amplitude It is the reference amplitude of the detection.
of ID1 signal When it is off, Amplitude detection becomes AUTO.
2EH: Dfl Phase of lol detection It is the reference phase of the lol detection.
When Adaptive , it can search in the range of 1:1.1113
at the DI.
2EH :DI-DO Sampling phase of lol It is the phase of the detection of lol.
"1" changes in 0.12ys unit at Ol, 0.28us unit at D2.
It usually uses on "O''
2FH: D7 LPF for W881 it set ON/OFF of LPF(Input stage of MIS-detection circuit)
2FH: D6 WSS data slice function It set WSS data slice function
When Adaptive slice,s|ice level changes by the input
amplitude.
2FH: D5-04 WSS slice level It set WSS slice level.
it is effective when 2FH D6
2FH: D2 WSS SC Det mode It set detection sensitivity of start-code of WSS
2FH :01-00 Select BSS field it set field that detect WSS
30H: 07-04 Adjust linetimingof000 lt is Delay-adjust of LINE-timing for the COO detection
It uses when detection start deviates in weak electric density
30H: D3-DO Adjust linetirningofl01 It is Delay-adjust of LINE-timing for the IDI detection
It uses when detection start deviates in weak electric density
31H :07-04 Adjust linetimingofhSS it is Delay-adjust of LINE-timing for the WSS detection
it uses when detection start deviates in weak electric density
31H: D3 fsc pull in It set sensitivity of Pulled-in of fsc.
high: Sensitivity is up.
31H :02 13.5MHz trap lt set ON/OFF of 13.5MHz Trap at ADC.
It usually uses on "0N"
31H :D1 IlR Filter selection Characteristic selecting of C-filter of SECAM.
31H: D0 IlR Filter ON/OFF it set ON/OFF of C-filter of SECAM.
A color beat can be reduced.
It usually uses on "Always ON" in SECAM.
Feb./2005
TOSHIBA TC90101FG
BUS address Function Contents
32H: D7 D1/D2 Det lt is the distinction of 01/02
It is effective 32h D6 when manual set.
32H: D6 OI/O? Manual set Internal control is fixed with Dlor02
32H: 05-04 Internal feed-back- When clamp set internal, it can set time constant.
33H: D7 Manual Gain Mi) it set ON/OFF of peak-MO Gain
It is effective when it is ON.
It gives priority to Manual when this bit is ON. Therefore,
it can't get the effect of Mo.
33H: M-DO Manual Gain it is effective when 33H(D7).
Gain becomes a fix.
34H: D7-D4 CGP start phase It set start phase of CGP(0utput of TerminaI-73)
34H: DS-DO Width of (YT It set width of CGP(0utput of TerminaI-73).
35H: D7-D4 Threshold for DET.443 It set threshold for DET.443.
lt is easy to distinguish when a MAX side is chosen.
35H: DI-DO Sync-tip-clamp-mode for it is the control of limit-clamp to add under the input signal
T-input at Y input.
Four kinds of switchings are possible
0N Always,limitter-clamp to add to Low-Ievel of input is ON.
OFF hlways,limitter-clamp to add to Low-level of input is off.
AUT01: It is ON in the no-signal and 'Wen Pedestal-Level
deviated greatly.
AUT02: It is ON on no-signal.
36H: D7 CGP OUT control It set action of (YT
AUTO: It is output only when an input signal is set 11(D7 and
M on 00H).
Forced on: It is output to all the input.
36H: D6 C Trap of DCOMB lt is ON, when you want reduce Cross-color and beat.
36H: DO Mute The Blanking period becomes mute
37H: D7 Y Noise it set f0 of Y-Noise-Cancels,
it usually uses on "0"
37H: D6 Y Noise Lim It set Limitter of Y-Noise-Canceleh
37H: D5 Y Noise Gain lt set Gain of Y-Noise-Canceleh
37H: D4 Y Noise canceler It set ON/OFF of Y-Noise-Canceleh
37H: D3 CKILL Gain It set the condition of CKILL Gain.
When it is set up in +6dB, Level which color disappears to
grows big. It uses "O" when weak electric density.
37H: D2 C Noise Iim it set Limitter of C-Noise-canker.
37H: DI C Noise Gain It set Gain of C-Noise-cancel
37H: DO C Noise canceler It set ON/OFF of C-Noise-Cancelen
Feb./2005
TOSHIBA
TC90101FG
MAXIMUN RATINGS (Vss=0V, Ta=25°C)
Each item of the maximum rating shows the marginal value of this product. Since a product is sometimes
damaged when rating is exceeded also one item or for a moment again, be sure to use it within rating.
CHARACTERISTIC SYNBOL RATING UNIT
Power Supply Voltage) (1.5V System) VDD1 -0.3 ' VSS+2.0 V
Power Supply Voltage2(2.5V System) VDD2 -0.3 - VSS+3.5 V
Power Supply VoItage3(3.3V System) VDD3 -0.3 - VSS+3.9 V
VlN -0.3 - VDDIO +0.3 V
Input Voltage SDA/SCL(Note1) -0.3 -- VSS + 5.5 V
AIN -0.3-- 1/DDAD+0.3 V
Potential difference between power supply terminals VDG1 (Note2) 0.3 V
(1.5V System)
Potential difference between power supply terminals VDG2(Note2) 0.3 V
(2.5V System)
Potential difference between power supply terminals VDG3(Note2) 0.3 V
(3.3V System)
Potential difference between power supply terminals VDG4(Note2) 0.3 V
(1.5V System>2.5V System)
Potential difference between power supply terminals VDG5(Note2) 0.3 V
(2.5V System >3.3V System)
Power Dissipation PD(Note3) 1900 mW
Storage Temperature Tstg -40 - 125 t
(N0te1) SOA, SOL: 5V tolerance
(N0te2) 1.5V system power supply terminal is made into the same voltage, 2.5V system power
supply terminal is made into the same voltage, and 3.3V system power supply terminal
is made into the same voltage.
The maximum potential difference should not exceed rating for all power supply
terminals then.
(Note3) Derated above Ta--25oc in the proportion
Operation conditions (Vss=OV)
of 19mW/%3
Cannot guarantee operation of T090A92F, when the recommendation power supply voltage
range (1.4tW-1.65)/, 2.3l/-2.7l/, 3AW-3 (W) is exceeded.
Once, when it returns from the over range,
it differs from a front condition
CHARACTERISTIC Terminal No. SYNBOL MIN TYP MAX UNIT
Supply Voltage for digital block 15,32,39,54,66 DVDD1-5 1.40 1.5 1.65 V
Supply Voltage for l/O block 23,49,60 VDDIO1-3 3.0 3.3 3.6 V
Supply Voltage for X0 block 6 VDDXO 3.0 3.3 3.6 V
Supply Voltage for PLL block 2 VDDPLL 2.3 2.5 2.7 V
Supply Voltage for Analog block 82,89,95,97 VDDAD/VDDDA 2.3 2.5 2.7 V
Ambient operating temperature - Topr -10 - 75 "C
Feb. / 2005 30
TOSHIBA TC90101FG
The condition of power (VDD=3.3V, 2.5V, 1.5V) rising and falling
(1)Power Supply rising
These contents are the important items which influence the reliability guarantee of the IC.
It is necessary to satisfy the following condition.
(1) Power rising condition
3.3V (power range : 3.0--3.6V)
-more than 3.0V
*note1
VDD=3.3V 2.5V (power range : 2.3--2.7V)
more than 0.4V - -
more than 2.3V
*note1
VDD=2.5V
more than 0.4V A
1.5V (power range : 1.4--1.65V)
*note1 more than 1.4V
VDD=1.5V
more than 0.4V
It needs to rise less than 40ms from starting to rise the power of 2.5V.
(reset release)
Terminal 30: RESET
After all powers rising, it is necessary to keep resetting more
than 0.5ms.
. _ And it must not keep the reset conditions more than one
minute.
IIC-Bus IN
Terminal31 : SDA
Terminal 32 : SCL
. After reset release, it is necessary to be more than 100ns for
IIC BUS control starting.
*note1 3.3V power
Such the power terminal are embedded the protective diode. terminal
It must not send a penetration electric current.
Condition:
Power level of 3.3V line a Power level of 2.5V line a Power level of 1.5V line
When the power level of 1.5V line is more than 0.4V, 3.3V line and 2.5V line must
A 2.5V power
terminal
reach the level of power more than 0.4V.
And when the power level of 2.5V line is more than 0.4V, 3.3V line must reach A
the level of power more than 0.4V. 1.5V power
terminal
It is necessary to fall the power of 1.5V line before 3.3V line and 2.5V line are fallen, and to fall the power of
2.5V line before 3.3V line is fallen.
It must not send a penetration electric current too.
(2) Power falling condition
Feb. / 2005 31
TOSHIBA
TC90101FG
ELECTRICAL CHARACTERRISTICS
(1) DO CHARACTERRISTICS
(Ta=25°C, VDD1=1. 50:0. IV, VDD2=2. 50-_+-0. 2V, VDD3=3. 30-_+-0. (W)
ITEM Terminal No. Symbol Min. Typ. Bax. Unit Note
Power 15,32,39,54,66 liDI 30 45 70 mA Sun total current of 1.5V
Supply system power supply terminal
Current NTSC Y/C Ill, Color Bar Signal
2,82,89,95,97 l002 80 105 135 mA Sun total current of 2.5V
system power supply terminal
NTSC Y/C IN, Color Bar Signal
6,23,49,60 IDD3 15 30 60 mA Sum total current of 3.3V
system power supply terminal
Changes with the loads of I/O.
Input 10,11,12,13,14,16,17, VIH VDD3x0.8 VDD3 V I/O input terminal of
Voltage 18,20,21,22,24,25,28, 3.3V system
29,30,31,50,51
26,27,33 I/O input terminal of
5.0V system
10,11,12,13,14,16,17, VIL VSS VDD3x0.2 ll I/O input terminal of
18,20,21,22,24,25,28, 3.3V system
29,30,31,50,51
26,27,33 VDD3x0 2 I/O input terminal of
5.0V system
5.0V Pull up use
0.3 I/O input terminal of
5.0V system
3.3V Pull up use
Input 10,11,12,13,14,16,17, llH -10 10 ph 3 I/o input terminal of
Current 18,20,21,22,24,25,28, 3.3V system
29,30,31,50,51
26,27,33 I/O input terminal of
5.0V system
10,11,12,13,14,16,17, llL -10 10 ph I/O input terminal of
18,20,21,22,24,25,28, 3.3V system
29,30,31,50,51
26,27,33 I/O input terminal of
5.0V system
Output 35,36,37,38,40,41,43, VOH 1/003-0 6 VDD3 V I/O output terminal of
Voltage 44,46,47,48,52,53,55, 3.3V system
56,58,59,61,62,64,65, Load of 4mA outflow
67,68,70,71,72,73,74,
35,36,37,38,40,41,43, VOL VSS 0.4 ll I/O output terminal of
44,46,47,48,52,53,55, 3.3V system
56,58,59,61,62,64,65, Load of 4mA inflow
67,68,70,71,72,73,74,
26 I/O output terminal of
5.0V system
Load of 4mA inflow
Notice: The specifications of VIL is difference in the Pull-up voltage.
When it specially uses for 3.3V with puII-up, do the design which is less than 0.3V securely.
Feb. / 2005
TOSHIBA TC90101FG
(2) AC CHARACTERRISTICS
(Ta--25i/001--1.5(W,v0lXl--2.5(W,vlE3--3.3(W)
ITEM Symbol Min. Typ. Max. Unit Note
AD input level for Y VYIN 0.7 0.8 l/p-p White 100% Signal
AD input level for C VCIN 0.5 0.8 l/p-p Cb/Cr input
ADO d i fferent i at i on error DLEa i4 LSB
ADC integration error ILEa -t-4 LSB
Output impedance 2y 160 200 240 Q
(3) PLL CHARACTERRISTICS
(Ta--25oC,W01--1.5(h/,l/002--2.5(W,l/003--3.3(W)
ITEM Symbol Bin. Typ. Max. Unit Note
Drawing-infrequencyrange Afka -50 50 kHz Clock Amplitude 0.5Vp-p
Operation input amplitude Vck 0.3 0.5 2.0 Vp-p Standard clock frequency input
Feb./2005 33
TOSHIBA
TC90101FG
Application
NPO.47u
I F--O---
-yir-sHjtyt,,-s-,
NP OA7 "
-xzzo-?iy-:h-
0.01 tt
NP OA7p
LPF ji:: ‘ (f)
NP 0.47 u
2.5V 2211': 0.1 u
--tr--
0.0111 2,
Feb./2005
18k 18k
73’; st
mmmlmmwe l nfsamm:
UVFLAG u
TC90101FG
Top view
m 1 5V
y 4 ttt ©
l. 5 csmc IN " -
- IMD? m -
(holy ldN
TESTM4 II - _
TESTM3 sir
TESTMZ "
TESTMI "
SOL ' .-
"r,:',: 15
C)Analog GND
3.3V 2) ©Digital GND
TOSHIBA TC90101FG
O PACKAGE OUTLINE
LQFP100-P-1414-0.50C UNIT:mm
16.0:0.8
14.0:0.e
tL 75 51
i'-- Illlllllllllilllllllllllllllllilllllllllllllililll
C) - "
0.125i&6s
Weight : 0.65g (center)
Feb. / 2005 35
TOSHIBA TC90101FG
About soloderability, following conditions were confirmed.
o Solderability
(I) Use of Sn-63Pb solder Bath
-so|der bath temperature--2300C
-dipping time=58econds
-the number of times=once
-use of R-type flex
(2)Use of Sn- 3. Ohg- A). 50u solder Bath
-so|der bath temperature-- 245° C
-dipping time--5seconds
-the number of time=once
-use of R-type flex
RESTRICTIONS ON PRODUCT USE 030619EBA
. The information contained herein is subject to change without notice.
. The information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.
. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility ofthe buyer, when utilizing TOSHIBA products, to comply with the standards of safety
in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability
Handbook" etc..
. The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, trafhc signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer's own risk.
. The products described in this document are subject to the foreign exchange and foreign trade laws.
q TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and
sold, under any law and regulations.
Feb./2005 36
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