TC8569AF ,FLOPPY DISK CONTROLLERGENERAL DESCRIPTIONTC8569AF is a single chip LSI for Floppy DiskController, which has VFO and other ..
TC8569AF ,FLOPPY DISK CONTROLLERW src-i) I Huavaua unagvén £7 i/Gia'FLOPPY DISK CONTROLLER llTOSHIBA (UC/UP)TC8569AFFloppy Disk Con ..
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TC8569AF
FLOPPY DISK CONTROLLER
TOSHIBA (UC/UP)
TC8569AF
Floppy Disk Controller
GENERAL DESCRIPTION
TC8569AF is a single chip LSI for Floppy Disk
Controller, which has VFO and other circuits with
FDC chip for interfacing a processor to floppy disk
drive and supports data rates up to leps.
FEATURES
Si-gate CMOS single chip LSI
Single + 5V power supply
80pin plastic flat package
Compatible with 8080 system data and control
Built-in VFO circuit
L Standby function for battery operation.
CLI" MFM recording formats ( 1M/ 500K / 250Kbps )
HL'ICJ
FM recording formats ( 250k/ 125Kbps )
Built-in write pre-compensation circuit
Motor enable control for 2 drives
Built-in address decorder
Multi-sector data transfer
Multi-track data transfer
Direct interface to FDD with CMOS type
interface system
Programmable step rate time
Compatible with IBM diskette 1 and 2
Including CRC check function
(Xtii + X12 +X5 + 1)
DMA / Non-DMA( interrupt) data transfer
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U TC8569AF is an improvement on the TC8569F. The differences between them are as follows.
. DMAC interface
T08569F has the bug that DMA data transfer hangs up at using the DMA controller in verify
mode [only -DACK2 is applied to FDC without -IOR and -IOW replying DRQ2], because DRQ2 is
not reset.
DRQ2 is reset only by being applied -DACK2 and -IOR or -IOW at the same time. At using
DAM controller in verify mode DMA controller applied only -DACK2 to FDC and therefore this
trouble occurs.
TC8569AF resolves this problem, The verify mode of DMA controller is available.
. VFO part
TC8569F's built-in VFO has the bug to decrease compatibility with IBM PCs FDC circuit.
TC8569F can hardly read the first sector when the all of the following conditions are satisfied.
(D Adopting a record format which doesn't include a certain data pattern to re-detect Sync
within, from Index position to the first sector.
© Using FDC VFO in 2-filter mode
© The first half of the sector data just before Index of the track is FF16 pattern,
TC8569AF improves this problem. Using TCB569AF in 2-filter mode, such a problem doesn't
occur. T08569AF has the same speeifieation as TC8569F except the above two points.
Tt38569AF-2
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3. FDC APPLICATION SYSTEM
3.1 FDC BLOCK DIAGRAM
XIN - , 16MHz -RDT
XOUT F-- CLOCK GENERATOR -SRSEL
L jr A -VFOEN
XRATEO,1 LMSEL
STAND BY TDW
STNBY O
LOGIC DW
-TEST1-3 H VCO
-cs _ -RW/SK
CS2 - tE-l $3
AEN H a n: CLKWCK t) A CONT
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..DACK2 a - TC VFORST DRQ2
A0-A2 H Cy o r-DAC SYNC - INTRQ
-TGATE H < "x r-cs MFM ; ENID
RD7EN ttr: - - RS DRQ bw IDSEL
FDC INT ,
DO-D? K DO-7 IDX _ ADX
RDY -_ -RDY
WP/2S _ ANP
- FLT/TRO < m ..TKO
C6 _ u: -RW/SK ' U -DSKCHG
U.l FR/STP = <
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- PS1 DSO
a WDT MEN1
8 -WE MENo s-ea-i--------:
-SHEN H WRITE ,
SHB H PRE-COMPENSATION , llOlNTERFACE
SHA - CIRCUIT
TCB569AF-3
TOSHIBA (UC/UP)
3.2 APPLICATION SYSTEM 1
TCS569AF corresponds with each floppy by changing value of D0 and D1 (XRATEO, XRATEI) on
control register 2. TABLE 3.2 shows the correlation between XRATEO, XRATEl and these floppys.
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FLOPPY DISK CONTROLLER
TABLE 3.2
CLOCK FREQ. OF TRANSFER
XRATE1 XRATEO FLOPPY TYPE INTERNAL FDC RATE
0 0 Standard floppy 8MHz 500Kbps
0 1 - - -
1 0 Mini floppy 4MHz 250Kbps
Perpendicular
1 1 magnetized 16MH2 1 Mbps
floppy
This technical data is only described feature of floppys (Standard floppy, Mini floppy and
1. Standard floppy
2. Mini floppy
3. Perpendicular Magnetized floppy
TC8569AF-4
Perpendicular Magnetized floppy). It's no mention of these floppy size.
2HD type or 8 inch floppy
MFM recording formats (8MHz/500Kbps)
FM recording formats (8MHz/125Kbps)
2D or 2DD type floppy
MFM recording formats (4MHz/250Kbps)
FM recording formats (4MHz/125Kbps)
2ED type floppy
MFM recording formats (leps)
FM recording formats (not supported)
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3.3 APPLICATION SYSTEM 2
3.3.1 ALTERNATIVE FILTER MODE
MPU fFb:r
VDD MODE LA vss I FDD
030-037 F-----) DO-D? ADX 4 -lNDEX
ABO-AB7 4 ' AO-AZ ..RDY 4 ~READY
4 INTRQ -WP 4 -WRITE PROTECTED
-TKO 4 -TRACK00
STP 7 -STEP
DBO-DB7 4 TC8569AF DR Y-DIRECTION
AB0-AB7 4 ENID HS t -HEADSELECT
AEN ' AEN MDSL1 ' -DRIVE TYPE1
-DACK2 , -DACK2 MDSLO ' -DRIVE TYPEO
Ditt12 4 DRQ2 DSI , -DRNESELECT2
TC ' DMATC DSO , -DRIVESELECT1
CTL F CS2 WE r -WRITE ENABLE
DB-DB? 4 , -cs1 won -----' -WRITE DATA
ABO-AB7 - fi‘ -IOR -RDT 4 -READ DATA
t -IOW -MOTOR ENABLE
, RESET MENI "
ca MENO "
TQC-228A-8R
C/a-ro-ct::----- XIN CDS -.,.,.,.C]
10pF 16MH2 10pF
:/ -tc, -TEST1-3 -SHEN
= VCO SHB Setup in puts
-RW/SK SHA
'M LPFI -SRSEL
t TRDT
Far-----] LPF2 TDW f
CONT FVFO 3
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DBO-DB7
ABO-AB7
DBO-DB7
ABO-AB7
..DACK2
DB-DB7
ABO-AB7
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VDD MODE LA VSS
DO-D7 -IDX
AO-AZ -RDY
INTRQ -wp
TC8569AF DR
ENID HS
AEN MDSL1
-DACK2 MDSLO
DRQ2 DSI
DMATC DSO
CS2 WE
-CSI WDT1
AOR -RDT
RESET MEN1
C4 MENO
XIN CDS
-TEST1-3 -SHEN
VCO SHB
-RW/SK SHA
LPF1 -SRSEL
LPF2 TDW
CONT FVFO
-READY
-WR|TE PROTECTED
-TRACK00
DIRECTION
-HEAD SELECT
-DRIVE TYPE 1
..DRIVE TYPE 0
-DRIVE SELECT 2
..DRIVE SELECT1
-WRITE ENABLE
-WRITE DATA
-READ DATA
..MOTOR ENABLE
) Setup inputs
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3.4 APPLICATION for lNTERFACING to IBM PC/AT
TC8569AF has the compatible registers in the floppy controller board of the PC/AT that are
CONTROL REGISTER 0 for the Digital Output Register (DOB) and CONTROL REGISTER 2 for the
Data Rate Register (DRR) and Digital Input Register (DIR). Signals SA8 through SA9 and AEN in the
slot of the PC/A'Ps system board are decoded and the decoded signal is applied to -CSl input to be chosen
3FOH-3F7H address space to T08569AF.
T08569AF can support 300Kbps data transfer rate by 24MHz system clock and setting MODE input to
"High". The content of CONTROL REGISTER 2 is as following table when the system clock is 24MHz
and "High Level" is applied to MODE input.
TABLE 3.4 CONTENT of CONTROL REGISTER 2 (XIN = 24MHz ' MODE = "High Level")
TE T F
XRATE1 XRATEO FLOPPY 5:: FulawcfahoriciK R321?“
0 0 Standard Floppy 8MHz 500Kbps
0 1 Mini Floppy 4.8MH2 300Kbps *
1 0 Mini Floppy 4MHz 250Kbps
1 1 - - -
* I FMformatis notsupported at300Kbps.
The typical application circuit of the floppy disk controller board for the PC/AT is shown in FIG.3.4b.
In this application circuit, 1Mbps, 500Kbps, 300Kbps and 250Kbps can be supported. The extra reset
routine is necessary to expect a correct operation when XRATEl and XRATEO are changed. This is
because that some glitches are generated when the system clock or MODE input level is changed. The
extra reset is not necessary to use TC8569AF in a fixed mode (MODE input and the system clock are not
changed during the operation).
..RDY input is connected to "Low level" in this application circuit when you should pay attention to the
flowing item. The ready flag in the FDC block is set to not-ready after the FDC reset is released. Then
four interrupt factors occur when FDC completes the drive scanning one cycle to detect the change of
ready line against the four drives. Therefore, SENSE INTERRUPT STATUS COMMAND should be
issued four times to reset the interrupt factors.
As commenting in the chapter 3.5, you should pay attention to the difference between the internal
FDC ofT08569AF and the conventional type of FDC in programing the application software. If you use
the standby mode, the control program for FDC should be modified as follow.
The state of the CONTROL REGISTER 0 has no relation to fulfill the standby condition. Therefore,
you should insert the additional procedure to set SMB bit in the CONTROL REGISTER 1 after the motor-
off routine and to reset SMB bit before the motor-on routine (Cf. FIG.3.4a)
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FlG.3.4a FLOW CHART for STANDBY CONTROL
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A22 WDT1 f-''-'------)-----:)) C,.?,: Cis22_? we
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( A30 l 26 A1 MDSU 79 fil>c >
CED 3 A0 MDSLO 8() >o----tw AMMDD
<3 6) 2 11 ENID
LS126 DRQ2 ---czCr------,
( B13 ) 31 -IOW R1 M c2
( B14 ) M) -10R LPF1 -3-8----l'v'v--//v'v--1
( B22 ) {1i 12 INTRQ CONT 40
(a s) mm 33 -DACK2 AG 41
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FIG.3.4b TYPICAL APPLICATION for IBM PC/AT
TC8569AF-9
TOSHIBA (UC/UP)
1lllFi-or'''1f DISK CONTROLLER
TC8569AF CAUTION IN PROGRAMING
3.5.1 FDC COMMAND
TCS569AF has a construction of commands which is almost compatible with that of TC8565P
(compatible with pPD765A), but some commands are different from that of TC8565P. At programming,
you should pay attention to the difference between T08569AF and the conventional type of FDC as
follows.
Commands which is not supported with TC8569AF
TC8569AF does not have three commands that are SCAN EQUAL, SCAN LOW or EQUAL and
SCAN HIGH or EQUAL.
Command which has different function
SPECIFY COMMAND defines the time interval betweenytep pulses, the head loading time and
the head unloading time. But TC8569AF does not have the function of head load, then the head
loading time and head unloading time have no meaning in the SPECIFY COMMAND of
TC8569AF. It is necessary to find another method if the head loading time is used as the
settling time for READ/WRITE operation.
New Command
CONFIG COMMAND should be executed at initializing FDC.
3.5.2 CAUTION AT INITIALIZING
At initializing FDC and changing the type of floppy you should pay attention to the several points as
follows.
Reset operation for FDC block
TC8569AF can reset FDC block by writing 0 (zero) to bit D2 in CONTROL REGISTER o. After
T08569AF is released from the reset state, this bit is set to 0 (zero). This bit need to be set to 1
when the FDC operation begins.
Setting up the type of floppy
The standard floppy mode is set up after TC8569AF is released from the reset state. You should
set up the correct floppy mode by writing to the CONTROL REGISTER 2 (XRATEl, XRATEO).
Execution of CONFIG COMMAND
At initializing FDC, CONFIG COMMAND should be executed for the correct operation.
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4.2 DESCRIPTION OF PIN FUNCTION
NO. PIN NAME IIO PIN FUNCTION
1 C6 0 Output port of C6 bitin a CONTROLREGISTER 1.
2 C4 0 Output port of C4 bitin a CONTROLREGISTER 1.
3 VDD V + SV powersupply
4 TWD 0 These terminals for test. Use in non-connect.
5 TRDT O
RESET CONTROL REGISTERS. The [-FRST] bit on the CONTROL
6 RESET I REGISTER 0 is also reset, and consequently the internal FDC block is
reset.
Output control signal for DISK CHANGED. When DISK CHANGE which
7 RD7EN O is output to [R07] is connected to the system bus via LS126, use this
outputforthe gate signalfor LS126.
8 -TGATE o When the data bus IS connected to the system bus vua LS245, use this
signal for the gate signal for LS245.
[DRQ2] and [INTRQ] become three state output when "Low Level" is
applied to this input. When ENID in the CONTROL REGISTER 0 is set
9 IDSEL I to 0 (zero), [DRQ2] and [INTRQ] output become high-impedance
state. When "High Level" is applied to this input, [DRQ2] and [INTRQ]
become totem-pole output.
10 ENID 0 Side output of ENID bit in a CONTROL REGISTER 0.
Request signal for DMA transfer. This signal is the delayed [DRQ]
11 DRQ2 0 from internal FDC chip. This signal is disabled to "Low level" with
setting 0 (zero) on the ENID bit in the CONTROL REGISTER 0.
Interrupt request signal for system from internal FDC chip. This signal
12 iNTRQ O is disabled to "Low level" with setting 0 (zero) on the ENID bit in the
..e.eAmrv CONTROLREGISTER 0.
13 VSS G Chips ground for digital circuits.
14 D0 1/0
15 D1 I/O
_1fi D2 I/O
17 D3 vo Bidirectional 8 bit data bus.
18 D4 "
19 D5 I/O
20 D6 1/0
21 D7 HQ
22 I/SS G Chips ground for digital circuits.
T08569AF-12
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FLOPPY DISK CONTROLLER Ill]
NO. PIN NAME I/O PIN FUNCTION
DISK CHANGE output. When the address (A2 =1, A1 = 1, A0 =1)is
23 RD7 O accessed ih the read operation _ , Low), this output signal shows
the inverting logic level which Is applied to the [-DSKCHG] input. This
output signal become high-impedance state in another condition.
24 CS2 I Chip select input. High active control signal.
25 A2 I Address 2 input
26 A1 I Address 1 input.
27 A0 I Address 0 input.
28 -CS1 I Chip select input. Low active control signal.
Address enable input. "Low level" on f-CSI] and [AEN] and "High
29 AEN I level" on [C52] select the FDC-III, and allows {-IOR] and HOW] to be
effective.
30 -IOR I Low active control signal to transfer data from the FDC to the Data-
Low active control signal to transfer data from the Data-bus to the
31 ..IOW I FDC-lII.
32 DMATC I High active DMA transfer terminating signal. When the FDC works
DMA MODE, this signal terminates the DMA transfer.
33 -DACK2 I Low active DMA cycle executing signal. When the FDC works DMA
MODE, this signal controls DMA IIO.
34 -TEST1 I
35 -TEST2 I These input terminals for LSI test. "High level" should be applied.
36 -TEST3 l
37 l/SS G Chips ground for digital circuits.
38 LPF1 O The charge pump output for external low pass filter. This output will
activate when PLL circuit force to lock the read signal (Pull-in mode).
The charge pump output for external low pass filter. This output will
39 LPF2 0 be selected after PLL has pulled in the read signal and use low gain
filter.
40 CONT I Analog voltage input for VCO.
41 AVSS AG Analog ground for VCO and PLL circuits.
42 VDD V f 5V power supply.
43 VCO O The output terminal for LSI test. Use in non-connect.
When "High Level" is applied to this input, the decode signal of bit 0
44 CDS I in CONTROL REGISTER 0 is selected for [DSI] and [D50]. When "Low
Level" is applied to this input, the non-decode signals of US1 and USO
of FDC block are selected for IDS1l and [D50].
45 -RDT I The input for the READ DATA from the floppy diskdrive.
46 -IDX I Index pulse input from FDD system interface.
T08569AF-13
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, I FLOPPY DISK CONTROLLER
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NO. PIN NAME l/O PIN FUNCTION
47 -RDY I Drive ready signal from FDD system interface.
- 48 AN? I Write protected indicate signal from FDD system interface.
Head position indicate signal from FDD system interface. Low level
49 -TKO I on this terminal means that the head of FDD is on the TRACK #0
position.
50 .,DSKCHG I Disk change signal from FDD system interface.
Physical active level select on the output of FDD system interface
signal, that is WDT1, WE, HS, STP, DR, HL, LWDEN, MENO--1, DSO--1
51 LA I and MDSLO--1. High level on this terminal means that these signal
will be low active and can connect to directly FDD which has CMOS
type interface specification.
52 -SHEN I Sofitel-gh level on the terminal, no pre-compensation shifting will be
53 SHB I Referto the section 5.1.8.
54 SHA i
This signal decides the operation of the internal VFO circuit. The VFO
55 FVFO I operates in fixed filter n'on-switching rnode when "Hi.gh',.'., and
operates in alternative filters (high gain and low gain filters)
switching mode when "Low".
This output terminal will show the recording format of the operation
56 MFM O of FDC. "High level" on this terminal shows that the FDC works at
MFM recording format and otherwise shows FM recording format.
57 VSS G Chipsground for digital circuits.
58 XIN I This input connects the crystal oscillator er external clock signal. In
the standard usage, use 16MHz crystal oscillator,
59 XOUT O This output is inverted signal of [XIN], or connected the crystal
oscillator,
"High Level" is applied to this input. if "Low Level" is applied, you
60 -SRSEL I will be able to program the step rate (Ref. SPECIFY COMMAND) at the
step of 1ms in mini floppy mode.
61 MODE I "Low level" should be applied.
This signal shows that FDC-lII is in a standby mode. In a standby
62 STNBY 0 mode, all internal clock is stopped for saving power dissipation and
following signals are inactive states WDT1, WE, HS, STP, DR, HL,
LWDEN, MENO--1, DSO-I and MDSLO--1.
63 VSS G Chips ground for digital circuits.
64 -RW/SK 0 "Low" shows that read /write operation is selected, and "High"
shows that seek operation IS selected.
65 LOCK O Theterminalfortest. Use in non-connect.
66 LWDEN o Low density output for FDD. Low active when LA = High.
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NO. PIN NAME IIO PIN FUNCTION
67 MEN1 O Motorenablefordrive #1 for FDD. Low active when LA=High.
68 MENO 0 Motor enable for drive #0 for FDD. Low active when LA=High.
69 WDT1 O Pre-compensated write data for FDD. Low active when LA = High.
70 WE 0 Write enable signalforFDD. Low active when LA=High.
Head select signal when LA = High when LA = Low
71 HS o High HeadO Head1
Low Head1 HeadO
72 VDD V + 5V power supply.
73 VSS G Chips ground for digital circuits.
74 HL 0 The terminal for test. Use in non-connect.
Decoded step pulse signal, connected disk drives for FDD. Low active
75 STP 0 when LA = High.
Decoded direction signal for head seek.
76 DR o when .LA=ngh LA= Low
Low innerseek outer seek
High outerseek inner seek
77 DSI 0 Drive select? signal for FDD. Low active when LA Tr. High. Refer to
TABLE 5.1.11a.
78 DSO 0 Drive select 0 signal for FDD. Low active when LA = High. Refer to
TABLE 5.1.11b.
79 MDSL1 0 These outputs signals show the FDD type which this controller
80 MDSLO o expects. Refer to TABLE 5.1.9.
TCB569AF-15
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5. FUNCTIONAL DESCRIPTION
5.1 CONTROL REGISTER and PART of PERIPHERAL CIRCUIT
5.1.1 RELATION of ADDRESS LINE and EACH REGISTER
AEN H x x x x x x M
x H x x x x M M
M X L M X M X X NO-SELECTION
L L H L L x M x
L L H L H L L H
H L CONTROL REGISTER o
L L H L H H x x NO SELECTION
L H MAIN STATUS REGISTER
L L H H L L H L CONTROL REGISTER 1
L L H H L H H L DATA REGISTER
L L H H H L M M NO SELECTIN
L L Fl H H H H L CONTROL REGISTER 2
x x x x x x L L INHIBIT
x x x x x M H H NO SELECTION
H : High L : Low x : Don'tCare
5.1.2 CONDITION OF STANDBY STATE
LSI will enter into standby mode after several times elapsed, when the SBM bit in the CONTROL
REGISTER 1 is set to "I" and following conditions are filled. The waiting time is decided by the state
of internal FDC mode. Usually, 6ms to 8ms in MINI floppy mode and 3ms to 4ms in STANDRAD
floppy mode. Additional condition is as follows.
C) ..FRST bit of CONTROL REGISTER 1 is set to "I".
C) FDC is in the state that it is waiting command from the host.
The output terminal [STNBY] is activated when FDC is in the standby state, and X'tal oscillation
stops. Standby state allows the drive output signals WDTI, WE, HS, STP, DR, HL, LWDEN,
MENO~1, DSO-land MDSLO~1 to be inactive.
LSI will take off from the standby state when one of following conditions is detected.
C) SBM bit is set to "O".
C) ..FRST bit is set to "O".
C FDC receives a command.
TC8569AF-1 6
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_ FLOPPY DISK CONTROLLER Ill
5.1.3 CONTROL REGISTER 0
5 bit register for write only
BIT SYMBOL NAME MEANING
D7 RESERVED
D6 RESERVED
D5 MEN1 MOTOR ENABLE 1 Radial motor on signal for #1 Drive
D4 MENO MOTOR ENABLE 0 Radial motor on signal for #0 Drive
D3 ENID ENABLE INT & DMA lNTRQ and DRQ2 are enabled when this
REQUEST bit is "High level".
0 on this bit will resetthe internal FDC
D2 -FRST NOT . FDC . RESET block. For normal operation, this bit
should be set to 1.
D1 RESERVED Drive Select bit : 0 on this bit indicates
that drive A is selected, 1 indicates that
DO DSA DRIVE SELECT A drive B is selected.
lf RESET signal get to "High ", all bits are cleared.
5.1.4 CONTROL REGISTER 1
4 bit register for write only
BIT SYMBOL NAME MEANING
D7 ENABLE6 When 1 is applied to this bit during byte
D6 C6 CONTROL 6 write operation of this register, the value of
C6 becomes to D6. When 0 is applied to this
D5 ENABLE4 bit during byte write operation of this
D4 C4 CONTROL 4 register, the value of C6 is to be copy of D6.
D3 ENABLE 2 When 1 is applied to this bit, FDC enables to
D2 SBM STANDBY MODE transfer into standby mode.
D1 ENABLE1 FDC terminal cotmt control bit. Pis.bit. will
be used to terminate data transfer m Non-
DO FDCTC FDC TERMINAL COUNT
D7, D5, D3 and D1 are the write enable bit for the each lower bit. For example, when 03H is written to
the register, only D0 can be set to l,
TC8569AF-17
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Ill] FLOPPY DISK CONTROLLER '
5.1.5 CONTROL REGISTER 2
3 bit register for write and read
BIT SYMBOL " NAME MEANING
D7 DCHG O DISK CHANGE 5 1U? RD7 wired with D7. Referto FIG.
Dti--D2 RESERVED
D1 XRATE1 TRANSFER RATE 1
Referto TABLE 3.2
DO XRATEO TRANSFER RATE 0
BUS CONNECTION METHOD (CMOS) RD7
MPU BUS
DB7 D7
TC8569F
DB6 D6
DBO DO
BUS CONNECTION METHOD (TTL) LS126
_ I RD7
DB7 D7
TC8569F
DB6 B----.....-.-.-- D6
DB0 DIR EN DO
L_, -TGATE
IOR -IOR
FIG.5.1.5 BUS CONNECTION METHOD
TC8669AF-18
TOSHIBA (UC/UP)
5.1.6 RELATION OF ENID,lNT,lNTRQ,DRQ,DRQ2
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FLOPPY DISK CONTROLLER llll
CONTROL ENID
REGISTERO -i>--C) ENID
BLOCK 4
DRQ DELAY -__._fD-------i>--C] DRQ2
Delay Time = 6tct
t tc tc = 62.5ns(1Mbps)
125ns(500Kbps)
250ns ( 250Kbps)
5.1.7 RELATION OF ENID,-DACK2, DMATC, FDCTD
CO NTRO L
REGISTER 0
-DACK2 I
DMATC Cry-
{>0 I y---------"-""-----
CONTROL
’__D_:): TC
REGISTER1
TC8569AF-19
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5.1.8 WRITE COMPENSATION CIRCUIT
-SHEN XRATE1 XRATEO SHB
SHIFT TRANSFER RATE
0 ns x
500 Kbps
250 Kbps
r-x—x—L-r'I-I—r-r-I-l-I-r-
IIIIIIIII—I—I—I—I—X
IIIII—I-r-r—II—r-I-I—X
III—I-IIr-r-XIIr-r-x
Ir—II—II—II—XIr—II—X
5.1.9 FLOPPY DISK DRVE MODE CHANGE
TABLE 5.1.9 FLOPPY DISK DRIVE MODE CHANGE
XRATE1 XRATEO MDSLO MDSL1
LA input= "High"
TC8569AF-20
TOEHiBX (UC/UPL
5.1.10 GATE OUTPUT FOR BUS TRANSCEIVER
but 1y"i:rcu:fri/iVs:, DDEEB
FLOPPY DISK CONTROLLER Ill
-DACK2 AEN -CS1 CS2 A2 A1 A0 AOR -|OW ..TGATE
H H x x x x x x x H
H x H x x x x x x H
H L x bt H
x x L INHIBIT
H L L H L L L x x H
H L L H L L H x x H
H L L H L H L L H H
H L L H L H L H L L
H L L H L H L H H H
H L L H L H H x x H
H L L H H L L L H L
H L L H H L L H L L
H L L H H L L H H H
H L L H H L H L H L
H L L H H L H H L L
H L L H H L H H H H
H L L H H H L rt x H
H L L H H H H L H H
H L L H H H H H L L
H L L H H H H H H H
L x x x x x x M x L
TC8569AF-21
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5.1.11 DRIVE SELECT OUTPUT
CDS = High, LA = High
TABLE 5.1.11a
BIT 0 of the CONTROL US1ofFDC USO of FDC DSI DSO
REGISTER 0 BLOCK BLOCK
1 x x Low High
0 x x High Low
x : Don't Care
CDS = Low, LA = High
TABLE 5.1.11b
BIT 0 of the CONTROL US1ofFDC USO of FDC DSI DSO
REGISTER 0 BLOCK BLOCK
x 0 0 High High
x 0 1 High Low
x 1 0 Low High
x 1 1 Low Low
x : Don't Care
TC8569AF-22
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5.2 PART OF FDC
5.2,1 DIAGRAM OFFDC
BUS REGISTER
------WCK
-----F WDT
DRQ A------
C (c) SERIAL - - £5
2fc Tir-tlr, READ/ INTERFACE ------F PS1
AOR E v)/ll2i/ (z) CONTROLLER SW
..IOW CONTROL __+
A0 -------- LOGIC ------ VFORST
TC ----F
RST -----F
U A----.
l DRIVE INPUT RDY
-cs l INTERFACE (r PORT ----wp
CONTROLLER IDX
CLK ___> (r) ----TKO
VDD -----F
----F uso
vss ------F __, US1
OUTPUT ---F MFM
PORT ---i-RW/SK
---v STP
TC8569AF-23
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(ill FLOPPY DISK CONTROLLER
5.2.2 FDC'S REGISTER AND CPU INTERFACE
FDC has two 8-bit registers accessible by the main system processor. One is a Main Status Register,
and the other is a Data Register. The Main Status Register indicates the status information of the FDC
and is always accessible.
The Data Register is used for data transfer between the FDC and the main processor. Command
bytes are written into the Data Register in order to program the FDC, and also Status bytes are read out
of the Data Register in order to obtain the result after execution of the commands.
Main Status Register may be read and is used to facilitate the data transfer between the processor
and the FDC. The relationship between Main Status Register and [-IOR], [-IOW] and [A0] signals is
shown below.
CS2=A2=1, A1=0, AEN=0
[-CS1] [A0] [-|OR] [-lOW] FUNCTION
H X X X Non Select
L L L L Illegal
L L L H Read Main Status Register
L L H L Write into CONTROL REGISTER 1
L H L L Illegal
L H L H Read from Data Register
L H H L Write into Data Register
Each bit in the Main Status Register are defined as TABLE 5.2.2. The RQM and D10 bits in the Main
Status Register indicate whether Data Register is ready or not and in which direction data will be
transferred on Data Bus.
TC8569AF-24
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DlO I I
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[-IORl Li Ld
A l B l A B [ c l B C B A
FIG.5.2.2 MAIN STATUS REGISTER TIMING
A : (DIO = "Low" and RQM = "High") The processor may write the data in Data Register.
B : (RQM = " Low") Data Register is not ready.
C : (DIO = "High" and RQM = "High") In data register, data byte which will be read out by
processor is already prepared.
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TC8569AF-25
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TABLE 5.2.2 MAIN STATUS REGISTER
BIT SYMBOL NAME MEANING
D7 RQM REQUEST for Indicates that Data Register is ready to send the data to
MASTER or to receive the data from the processor.
Indicates the direction of data transfer between Data
Register and the processor.
D6 DIO DATA IgstTjg-(JT When DIO is a "High", transfer is from Data Register to
the processor. When DlO is a "Low", transferfrom the
processor to Data Register.
Non-DMA Indicates that the FDC is Non-DMA mode. It is set only
mode during Execution-Phase in Non-DMA mode.
Indicates that FDC is in Execution-Phase of a read/write
D4 CB FDC BUSY command, in Command-Phase, or in Result-Phase.
D3 033 FDD 3 BUSY FDD number 3 is in the seek mode.
D2 D2B FDD2BUSY FDD number2 isin the Seek mode.
D1 D18 FDD 1 BUSY FDD numberi isin the Seek mode.
D0 DOB FDDO BUSY FDD numberOisin the Seek mode.
D5 NDM
FDC supports thirteen different commands. Each of commands is initiated by a multi-byte transfer
from the processor, and the result after executing of the command is a multi-byte transfer to the
processor. Because the multi-byte information is interchanged between the FDC and the Processor, it is
regarded that each command consists of following three phases.
Commands-Phase .' The FDC receives the necessary information to perform a particular operation
from the processor.
Execution-Phase ' The FDC performs the specified operation.
Result-Phase '' After the operation Result Status information or other information is sent to the
processor.
In the Command-Phase or the Result-Phase, the processor must read out the Main Status Register
before each byte of information is written into or read out from the Data Register.
When each byte of the command and the parameter is written into the FDC, bit D7 and D6 in the
Main Status Register mustbe in high level and low level, respectively.
Because most of the Commands need multiple bytes, the Main Status Register must be read out
before each byte is transferred to the FDC, In the Result-phase, the bit D7 and D6 in Main Status
Register must be both in high levels before each byte is read out from the Data Register.
The reading out of the Main Status Register before each byte transfer to the FDC is necessary only in the
Command-Phase and the Result-Phase, but it is not always necessary in the Execution-Phase.
TC8569AF-26
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FLOPPY DISK CONTROLLER [HI
When the FDC is in Non-DMA mode, the receipt of each data byte (if the FDD is now reading out
data from the FDD) is indicated by the Interrupt signal [INTRQ].
The generation of the Read signal ([-IOR] = 0) will not only output the data on the data bus but also
reset the [INTRQ] signal. If the processor can not deal with interrupts fast enough (within 7.0ps for
Perpendicular FDD mode) , then it examines the Main Status Register, and then bit 7 (RQM) functions
just like the Interrupt signal. Similarly in the Write command, Write signal resets the Interrupt signal.
If the FDC is in the DMA mode, then the Interrupt signal is not generated during the Execution-
Phase. When the each data byte is available, the FDC generates [DRQ2] (DMA request) signal. Then
the DMA controller generates both DMA Acknowledge signal and Read signal f[-DACK2l = 0 and
[-IOR] = 0).
In a Read command, when the DMA acknowledge signal becomes low level, the FDC automatically
resets the (DRR2). In a Write command, [-IOW] is substituted for [-IOR]. If the Execution-Phase is
terminated (Terminal Count has been inputted) , the Interrupt request is generated. This means the
beginning of the Result-Phase. When the first data byte is read during the Result-Phase, Interrupt
signal is automatically reset. During the Result-Phase, all data bytes shown in the COMMAND TABLE
must be read.
For example, the READ DATA COMMAND has seven data bytes in the Result-Phase. All seven
data bytes must be read out in order to complete the READ DATA COMMAND. This FDC will not
accept the next command until all these seven data bytes are read out. In the same way, all the data
bytes of the other commands must be read out during the Result-Phase. The FDC has five Status
Registers. The Main Status Register mentioned above can always be read out by the processor. The
other four Result Status Register (STO, STI, ST2, ST3) is available only in the Result-Phase, and read
out only after the termination of the command .
The specified command determines how many the Result Status Registers will be read. The
COMMAND TABLE shows the data bytes that are sent to the FDC in the Command-Phase and read out
from the FDC in the Result-Phase. That is, the command code must be sent first, and the other bytes
must be sent in order. So the Command-Phase and the Result-Phase can not be shorten. When the last
data byte in the Command-Phase is sent to the FDC, the Execution-Phase automatically starts.
Similarly, when the last byte in the Result-Phase is read out, the command is automatically
terminated, and then the FDC is ready for a new command.
TC8569AF-27
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Illl FLOPPY DISK CONTROLLER
5.2.3 FUNCTION OF POLING IN FDC
After the SPECIFY COMMAND has been sent to the FDC, the drive select signals, the DSI and D80,
are automatically in the polling mode. Between the commands (and between the step pulses in the seek
mode), the FDC checks the four FDDs looking for a change of the ready signals from drive units.
If the Ready Signal is changed, then the FDC generates the Interrupt Signal. After the processor has
issued the SENSE INTERRUPT STATUS COMMAND, the Result Status Register 0 (STO) is read out,
and the Not Ready bit (NR) in STO shows the present status. Because of the polling of Ready Signal
between the commands, the processor can notice which drives are on line or which drives are off line.
TCB569AF-28
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FLOPPY DISK CONTROLLER llll
TOSHIBA (UC/UP)
5.2.4 TRACK FORMAT
(1) IBM FORMAT
INDEX -r"""'-l., __l_1_
Gap4a SYNC IAM GAP1 i. '... i.. Gap4b
'FF' '00' 'FC' TF' Sector1 ESectorZ i.ssctor::sector n 'FF'
FM : : :
X40 X6 X1 X26
'4E' '00' 'C2' 'FC' '4E' Sector1 :Sectorz ESector--§Sector n '4ii'
MFM : . :
X80 X12 X3 X1 X50
" -..---" RepeatUntil 'ss..,.,
-.,....--"" NumberofSector "s,
SYNC IDAM C H R N CRC Gap2 sync DAWDDAM) 'e," CRC Yf
FM 'oo' IFEI IFFI I00! 'FB' 'FF'
I ('F8')
X6 X1 X1 X1 X1 X1 X2 X11 X6 X1 X2
MFM '00' 'A1' 'A1' '4E' '00' 'A1' 'FB' '4E
M ('FB')
X12 X3 X3 X1 X1 X1 X1 X2 X22 X12 X3 X1 X2
MFM '00' 'A1' 'A1' '4E' '00' 'A1' 'FB' '4E
m. ('F8')
Erase X12 X3 X3 X1 X1 X1 X1 X2 X41 X12 X3 X1 X2
(*1) Programmable
Missing Clock of Address Mark
FM MFM
DATA CLOCK DATA CLOCK
IAM FC D7 C2 Ill
IDAM FE C7 A1 GA
DAM FB cr A1 0A
DDAM F8 C7 A1 0A
TC8569AF-29
TOSHIBA (UC/UP)
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(2) PFD Format
A------ ID Field -------9---------- Data Field ---------H
NEXT INDEX
1 Sector
GapO SYNC IAM Gap1 SYNC IDAM ID CRC Gap2 SYNC DAM DATA cac Gap3 Gap4 $5,518,?
Bytes so 12 3 1 so 12 3 1 4 2 41 12 3 1 256 2 62 515 61
512 83 518 36
1024 113 494 20
Data 4E 00 c2' FC 4E 00 At' FE 4E 00 A1' Jd, 4E 45
* : Include Missing Clock Bits.
Data Clock
TC8569AF-30
FIG 5.2.4 WIDE ERASE FORMAT
TOSHIBA (UC/UP) ELIE J) Cl HUHTEHH 00213620 8S'3 DTOSE!
FLOPPY DISK CONTROLLER llll
5.2.5 MFM RULES (USE IN IBM DISKETTE 2D)
The data bit is written where the each bit will correspond to the center of the bit sell with "I". The
clock bit is written at the head of the bit cell with "O" whose previous bit cell has "O".
BlT-SELL 110010001000
MFM lllllllll
D: Data . Bit
C : Clock. Bit
FIG.5.2.5 MFM RULES
TC8569AF-31
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5.2.6 COMMAND TABLE
(X: Don't care)
READ DATA COMMAND
PHASE RNV D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
MT MFM SK 0 0 1 1 0 Command code
x x x x x HS DS1 DSO
C W R *
EOT * ID information of
GPL starting sector of
DTL command execution
E Data transfer
R R C * * lDinformation of
H * end sector of
R * c o m m a n d
N * execution
WRITE DATA COMMAND
PHASE MN D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
MT MFM 0 0 0 1 0 1 Command code
x x x M x HS DS1 DSO
C W R *
EOT * ID information of
GPL starting sector of
ADTL command execution
E Data transfer
R R C * * IDinformation of
H * end sector of
R * C o m m a n d
N * execution
TC8569AF-32
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FLOPPY DISK CONTROLLER llll
TOSHIBA (UC/UP)
WRITE DELETED DATA COMMAND
PHASE MN D7 D6 D5 D4 D3 D2 DI D0 REMARKS
MT MFM 0 0 1 0 0 1 Command code
x x x x x HS DS1 DSO
C W R *
EOT ID information of
GPL starting sector of
DTL command execution
E Data transfer
R R C * * IDinformation of
H * end sector of
R * C o m m a n d
N * execution
READ DELETED DATA COMMAND
PHASE RNV D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
x x x x x HS DS1 DSO
C IN R *
EOT ID information of
GPL starting sector of
DTL command execution
E Data transfer
R R C * * IDinformation of
H * end sector of
R * c o m m a n d
N * execution
T08569AF-33
TOSHIBA
(UC/UP)
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llliFLor'Py DISK CONTROLLER
READ DIAGNOSTIC COMMAND
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
0 MFM 0 0 0 0 1 0 Commandcode
X X x X x HS DSI DSO
C W R R=No meaning
EOT * ID information of
GPL starting sector of
DTL command execution
E Data transfer
R R C * * IDinformation of
H * end sector of
R * c o m m a n d
N * execution
READ ID COMMAND
PHASE MN D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
0 MFM 0 0 1 0 1 0 Commandcode
C W x x x x x HS DSI D50
R R C * * ID information
H * which read out
R * during execution-
N * phase
T08569AF-34
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FLOPPY DISK CONTROLLER lil
FORMAT COMMAND
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
C W 0 MFM 0 0 1 1 0 1 Commandcode
x X X x x HS DSI DSO
E Data transfer
R * A = No meaning
SEEK COMMAND
PHASE MN D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
C W 0 O 0 0 1 1 1 1 Commandcode
x x x x x xDS1DSO
E Seek
RECALIBRATE COMMAND
PHASE RNV D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
C W 0 0 0 0 0 1 1 1 Command code
x x x x x xDS1DSO
E RECALIBRATE
TC8569AF-35
TOSIII~BA (UC/UP)
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T08569AF-36
ELIE 1) El HU‘WEl-lci 00313835 330
SENSE INTERRUPT COMMAND
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
C W 0 0 0 0 1 0 O 0 Command code
R R STO
SPECIFY COMMAND
PHASE MN D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
0 0 0 O 0 0 1 1
C W SRT I x x x x Command code
x x x x x x x ND
SENSE DEVICE STATUS COMMAND
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
C W 0 0 0 0 0 1 0 0 Command code
x x x x x HS DSI D50
R R ST3
CONFIG COMMAND
PHASE MN D7 D6 D5 D4 D3 D2 D1 DO REMARKS
C W 0 0 0 1 0 0 1 0 Command code
x x x x x x WG FMT
INVALID COMMAND
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
C W The other command code
R R STO STO = 80H
EITOSB
TOSHIBA (UC/UP) ELIE I) III 90972qu Cll3iilia8i?la B7? ©TOS3
TABLE 5.2 SYMBOLS in the COMMAND TABLE (1/2)
SYMBOL NAME DESCRIPTION
C Cylinder Indicates the cylinder number.
Number
D D Indicates the data pattern which is going to be written into data
ata field
D7-D0 Data Bus 8 bit data bus ' D7 is MSB and D0 is LSB,
DSI, 0 Drive Indicates the drive number(O, I, 2, 3).
Select
DATA IF N = 00, indicates the data length per sector which is going to
Length be processed.
EOT End of Indicates the last Sector of a cylinder.
FMT Format Indicates whether IBM format or pre-erase format is used.
GPL Length Indicates the length of Gap 3 (see 5.2.4 Track Format ).
Head . .
H Address Indicates the logical head address.
HS Head Indicates the physical head address.
Select
MFM " " . " . " .
MFM mode If Low ' FM mode IS selected. If High ' MFM mode IS selected.
Multi " . " . . .
MT If High ' multi track operation is to be performed.
N Number y is the code which indicates the number of data bytes written
In a sector.
New . .
. Indicates the new cylinder number to be reached as a result of
NCN Cylinder .
the seek operation.
Number
ND Non-DMA Indicates the Non-DMA mode. Defined by the Specify
Command.
Present
. Indicates the cylinder number when the Sense Interrupt Status
PCN Cylinder
Command has completed.
Number
R Record Indicates the sector number.
R/W 1yrd/ Indicates whether Read or Write.
SC Sector Indicates the number of sector per cylinder.
SK Skip Indicates the skip of the sector which has DDAM or DAM.
TC8569AF-37
TOSHIBA (UC/UP)
EHE I) © 90972”? tltli?la8i?7 $03 EJTOSB
lilirLopr'Y DISK CONTROLLER
TABLE 5.2 SYMBOLS in the COMMAND TABLE (2/2)
SYMBOL NAME DESCRIPTION
SRT Step Rate Indicates the step rate of FDD which is defined by Specify
Time Command.
In scan operation, when STP is set to "1", sector's are processed
STP Step continuously. When STP is set to 'W', sector's are processed one
by one.
pendicular . . .
PFD (Vertical) The drive which has wide pre erase head system.
Conven- . .
MFD . The drive which has tunnel-erase or straddle-erase hard system.
tional FDD
WG )l./,rlt,fate Indicates the timing of Write Gate during write operation.
TC8569AF-38
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FLOPPY DISK CONTROLLER m]
”TOSHIBA (Ut/up)
5.2.7 COMMAND DESCRIPTION
During the Command-Phase, the CPU must examine the Main Status Register before the writing of
the each data byte into the Data Register. The D10 and RQM in the Main Status Register must be in a
low level and a high level, respectively, before each byte is written into the FDC.
READ DATA COMMAND
The FDC needs nine data bytes in order to execute the read data command. After the read data
command has been issued, the FDC begins to search ID address marks and read ID fields. If ID
information stored in the ID register agrees with ID information in ID field read from the diskette, then
the FDC outputs data from the data field byte-by-byte to the main system via the data bus.
After the read operation of the current sector has been completed, the sector number (R) is
incremented by one, the FDC reads the data from the next sector, and outputs the data on the data bus.
This continuous read function is called a "Multi-Sector Read Operation". The read data command may
be terminated by receiving a terminal count (TC) signal. If the FDC receives a TC signal, the FDC stops
outputting data to processor, but continues to read data from the current sector, and cheeks the CRC
(Cyclic Redundancy Code) bytes, and then terminates the read data command at the end of the sector.
The amount of data which can be handled with a single command to the FDC depends on MT (Multi-
Track), MFM (MFM/FM), and N (Number of bytes/sector). The transfer capacity is shown in TABLE
5.2.7a below.
TABLE 5.2.7a
MAXIMUM TRANSFER
CAPACITY
MT MFM N BYTES/ NUMBER OF FINAL SECTOR
SECTOR SECTOR
0 0 00 128 26 Side 0 Sector 26 or
1 01 256 Side1 Sector 26
0 00 128 .
1 1 01 256 52 Sidel Sector 26
0 0 01 256 15 SideO Sector 15 or
1 02 512 Side 1 Sector 15
0 01 256 . _------
1 1 02 512 30 Sidel Sector 15 MiE
0 0 02 512 8 Side 0 Sector 8 or -
1 03 1024 Side 1 Sector 8
0 02 512 .
1 1 03 1024 16 Side1 Sector8
TC8569AF-39
TOSHIBA (UC/UP)
EHE D IEl HUQ?EHH Cl0i?ia8iiiln TEE EJTOSB
(ililFll-OPPY DISK CONTROLLER
The FDC can read out the data from both sides of the diskette by the Multi-Track function. Data
transfer will be performed from the Sector 1 of Side 0 to the last Sector of Side 1 for a particular cylinder at
a time. But this function is effective to only one cylinder of the diskette.
After the reading out of the last sector, the FDC must receive the terminal count. Ifthe FDC does not
receive the terminal count signal, then the FDC sets the EN (end of cylinder) flag of STI to a high level
and terminates the read data command (bits 7 and 6 of STO is also set to a low level and a high level
respectively .' abnormal termination).
When N = o, DTL defines the data length which the FDC must treat as a sector. IfDTL is smaller than
the actual data length in a sector, the data beyond DTL in the sector is not sent to the data bus, but the
FDC reads the whole sector internally, and then checks CRC bytes. When Nf 0 DTL has no meaning.
If the FDC can not find out the right sector until the FDC detects the index hole twice, and the FDC
sets the ND (No Data) flag in STI to a high level, and the read data command will be abnormal
terminated (bit 7 and bit 6 in STO set to a low level and a high level respectively).
After the reading of the ID field and the data field of the each sector, the FDC checks the CRC bytes. If
a read error (incorrect CRC bytes in the ID field) is detected, the FDC sets the DE (Data Error) flag of STI
to a high level, and if data error in the data field is detected, the DD (Data Error in Data Field) flag in ST2
is set to a high level, and then the read data command is abnormal terminated.
Ifthe FDC read a deleted data address mark in the diskette, and SK bit (D5 bit in the command code)
is not set, then the FDC sets CM (Control Mark) flag to a high level after reading out all the data in the
sector, and terminates the read data command. When SK: 1, the FDC skips the sector that has DDAM,
and read out the next sector.
During the data transfer between the FDC and the processor, the FDC must receive the service from
the processor within 7 Sps at the mode of Perpendicular Magnetized FDD, within 13ps in MPM mode and
27ps in FM mode at the mode of Standard FDD. If the FDC does not receive this service in time, the FDC
sets OR (Over Run) flag to a high level, and terminates the read data command (abnormal termination).
If a read (or write) operation is terminated by inputting the terminal count signal, the information of
Result-Phase is defined by MT bit and BOT byte. TABLE 5.2.7b shows the value for C, H, R and N when
the command is normally terminated.
TC8569AF-40
TbsHIBA (UC/UP)
"i-wi/li:::::.:):)::!':, 0020030 '?'l'8
EJTosé
FLOPPY DISK CONTROLLER llll
5.2.7b ID INFORMATION AT NORMALTERMINATION
ID INFORMATION ESULT- ASE
MT EOT FINAL TRANSFERRED SECTOR C H IN R R PH N
1A Sector1to 25 atSideO
0F Sector 1 to 14 at Side 0 NC NC R +1 NC
08 Sector 1 to 7 at Side 0
1A Sector 26 at Sideo
0F Sector15at5ide0 C+1 NC R=01 NC
08 Sector8 at Side 0
1A Sector 1 to 25 atSide1
0F Sector 1 to 14 at Side1 NC NC R+1 NC
08 Sector 1 to 7 at Side 1
1A Sector26at5ide1
OF Sector15 at Side1 Cel NC R=01 NC
08 Sector 8 at Side 1
IA Sector 1 to 25 at Side 0
OF Sector 1 to 14 at Side 0 NC NC R +1 NC
08 Sector1to 7 at Side 0
1A Sector 26 at Side 0
OF Sector 15 at Side 0 NC LSB R = 01 NC
08 Sector 8 at Side 0
1A Sector 1 to 25 at Side 1
OF Sector1to14 at Side1 NC NC R +1 NC
08 Sector 1 to 7 at Side 1
IA Sector 26 at Side1
OF Sector 15 at Side1 C +1 LSB R = 01 NC
08 Sector 8 at Side 1
NOTE NC (No Change) : The same value as the one at the beginning of
command execution.
LSB(LeastSignificantBit) : TheIeastsignificantbitofHiscomplemented.
TC8569AF-41
TOSHIBA (UC/UP) - ENE D I: 90972“! 0025831. EBHDEZITOSB
illl FLOPPY DISK CONTROLLER
WRITE DATA COMMAND
The FDC needs nine data bytes in order to execute the write data command. If the write data
command has been issued, the FDC begins to read the ID field. If the sector number stored in ID
register (IDR) matched with the sector number read from the diskette, then the FDC takes data from
the processor byte-by-byte via the data bus, and outputs to the FDD,
After the writing the data into the current sector, the FDC increments the sector number stored in
R by one, and then the FDC writes the next data field. The FDC continues this Multi-Sector write
operation until the terminal count signal is issued. Even if the FDC has received the terminal count
signal, the FDC continues writing for the sector, and the data field will be completed. If the FDC
receives the terminal count signal while the FDC is writing data in data field, then the remained data
field will be filled with 00.
The FDC reads out the each sector of ID field, and checks the CRC bytes, If the FDC finds out the
Read Error in ID field (incorrect CRC bytes), the FDC sets DE (Data Error) of STI to a high level, and
terminates the write data command (abnormal termination).
The rules of the write commands are much similar to the rules of the read data command. The
following items are same, see the previous section READ DATA COMMAND.
D Transfer Capacity
C EN flag
Ci ID information at the normal termination
El Meaning of DTL when N = 0 and when N:ae 0
During the execution of the write data command, the data transfer between the processor and the
FDC must be performed within 7.0ps at the mode of Perpendicular Magnetized FDD, within 14ps in
MFM mode and 29ps in FM mode at the mode of Standard FDD. If it is not performed, the FDC sets
OR flag of STI to a high level, and terminates the command (abnormal termination).
WRITE DELETED DATA COMMAND
This command is the same command as the write data command except that the FDC writes the
DDAM (Deleted Data Address Mark) at the beginning of the data field instead of the normal DAM
(Data Address Mark),
READ DELETED DATA COMMAND
This command is the same as the read data command except that the FDC reads the sectors with
DDAM instead of those with DAM at the beginning of a data field. If the FDC detects DAM and
SK=0, then the FDC will read the whole sector and set CM flag in ST2 to a high level and terminate
the command (normal termination). If the FDC finds out DAM and SK: 1 then the FDC will skip the
sector with DAM and read the next sector.
TC8569AF-42
-r/o:iu:iiiiuc%-ir, ---, - -" ”‘LuETE: niFri-GinhrioiidiSii!" 3651333
FLOPPY DISK CONTROLLER Ill!
READ DIAGNOSTIC COMMAND
This command is the same as the read data command except that the FDC reads all the data
continuously from each sector of a track. J ust after the FDC receives the index signal, the FDC begins
to read out all the data field on the track as a continuous block. Even if the FDC finds out the CRC
error in ID or data field, the FDC continues to read data from the track. The FDC compares the ID
information read out from each sector with the value stored in IDR, and if there is no comparison, the
FDC sets ND flag to a high level. This command has neither the Multi-Track function nor the skip
function.
This command will be terminated when EOT number of sectors have been read out. When ID
address mark on the diskette is not found out until the FDC finds out the index hall twice, MA
(Missing Address Mark) in STI is set to a high level, and the command is terminated (abnormal
termination).
READ ID COMMAND
This command is used to inform the processor of the current head point. The FDC stores the first ID
information to be read out. If the right ID address mark is not found on the diskette until the FDC
finds out the index hall twice, the FDC sets MA flag in STI to high level, and if there is no ID field
without CRC error, ND flag in STI is set to a high level, and the command is terminated (abnormal
termination).
FORMAT COMMAND
The format command allows an entire track to be formatted. After the index hall is detected, the
FDC writes data on the diskette. Gaps, address marks, ID fields and data fields on IBM system 34
(double density) or IBM system 3740 (single density) or pre-erase format are recorded. The particular
format is controlled by the values programmed in N, SC, GPL and D during the command-phase. The
data byte stored in D is written into the processor. That is, the FDC requests four data bytes per sector
for C, H, R and N. This function allows the diskette to be formatted with non-sequential sector
numbers.
After the each sector is formatted, the processor must send the new values of C, H, R and N to the
FDC for the next sector on the track. After a sector is formatted, the contents of the R-register is
incremented by one. Thus, when the R register is read out during the result-phase, it contains a value
of R+ 1. This incrementing and formatting continues for the track until the FDC detects the index
hall for the second time. When the FDC finds the index hall twice, the command is terminated.
If the ready signal changes to a low level at the beginning of the command execution, then the
command is terminated. TABLE 5.2.7c shows the relationship of N, SC and GPL for various sector
sizes.
TC8569AF-43
TOSHTBA (UC/UP)
llli FLOPPY DISK CONTROLLER
TABLE 5.3.7c RELATIONSHIP of SECTOR SIZES
vhs: I) E ‘llJ‘l'PEHCI 0035633 LID?
IZITOSB
SECTOR SIZE
FORMAT BYTE /SECTOR N (16) N (16) N (16) REMARKS
128 00 1A 18 IBM Diskette1
256 01 OF 2A IBM Diskette 2
IBM 512 02 08 3A
Format
FM mode 1024 03 04 -
2048 04 02 _
4096 05 01 -
256 01 1A 36 IBM Diskette 20
IBM 512 02 OF 54
Format 1024 03 08 74 IBM Diskette 2D
MFM 2048 04 04 -
mode 4096 05 02 -
8192 06 01 ....
256 01 30 3E
Pte-erese 512 02 24 53 v ' I FDD MFM d
Format ertlca mo e
1024 03 14 71
*Note: GPL defines the length of GAP placed just after each sector.
SEEK COMMAND
This command is used to move the read/write head from cylinder to cylinder. The FDC compares
the PCN which is current head position with the NCN. Ifthere is a difference, the FDC performs the
following operation.
PCN < NCN
PCN > NCN
l Direction signal to the FDD is set to a high level (LA=low), and the step pulses are
issued (Step in).
'. Direction signal to the FDD is set to a low level (LAzlow), and the step pulses are
issued (Step out).
The rate of outputting the step pulses is controlled by the SRT (step rate pulse) in the specify
command. The FDC compares NCN with PCN at outputting the step pulses, and if NCN=PCN, then
SE (seek end) flag in STO is set to a low level, and the command is terminated. The FDC is in FDC
busy state during the command-phase of this command, but the FDC is in non-busy state, the FDC
accepts another seek command. This function allows the FDC tn do the parallel seek operation for up
to 4 FDDs at a time.
TC8569AF-44
uii:iETiu:rri/ir0:rioiiiiiiiiail BHéthTOSB
FLOPPY DISK CONTROLLER HI]
-ro:i;rcrsui" (uc/UE)
If the FDD is in the not ready state at the beginning of the execution-phase of this command or
during the seek operation, the NR (not ready) flag in STO is set to a high level and the command is
terminated.
RECALIBRATE COMMAND
The read/write head within the FDD is moved to the track 0 position under control of the
recalibrate command. The FDC clears the contents of PCN register, and checks the track 0 signal. If
the track 0 signal is in a low level, the FDC sets the direction signal to a low level, and issues the step
pulses.
When the track 0 signal changes to a high level, the FDC sets SE (seek end) flag to a high level, and
terminates the command. If the track 0 signal is still low after the FDC has issued the 255 step pulses,
SE flag and EC flag in STO are set to both high levels, and the command is terminated. The recalibrate
command is the same as the seek command about the function to overlap the operation to multiple
FDDs and about the loss of the ready signal.
SENSE INTERRUPT STATUS COMMAND
The FDC generates the interrupt signal by the following reasons.
(1) The beginning of result-phase in the following commands .'
a. Read Data Command
b. Read Diagnostic Command
c. Read ID Command
d, Read Deleted Data Command
e. Write Data Command
g. Write Deleted Data Command
(2) The change of ready line of FDD.
(3) At the end of the Seek or Recalibrate Command
(4) During the execution-phase in the non-DMA mode.
Interrupts caused by reason 1 and 4 occur during the normal command operation, and the processor
can notice the interrupts easily. But the interrupts caused by the reason 2 and 3 may be identified
with the request of issuing the sense interrupt status command. When this command is issued,
interrupt signal is reset, and bit 5, bit 6 and bit 7 in STO indicate the reason of the interrupt.
TC8569AF-45
TOSHIBA (tlc/tlp) EHE D © 909729”! UUEEBES arf DTOSH
llll FLOPPY DISK CONTROLLER
TABLE 5.2.7d SEEK AND INTERRUPT CODE
INTERRUPT CODE SEEK END
MEANING
BIT 7 BIT 6 BIT 5
Changing of the state of the
1 1 0 .
Ready Line
0 O 1 Normal termination of the
Seek and Recalibrate Command
tl 1 1 Abnormaltermination of the
Seek and Recalibrate Command
Neither the seek nor the recalibrate command has a result-phase. Therefore, it is necessary to use
the sense interrupt command after these commands in order to terminate them effectively and confirm
the head position (PCN).
SPECIFY COMMAND
This specify command initializes the values of internal timer. The SRT defines the time interval
between step pulses. This timer is programmable from 1 to 16ms in increments of lms (F=1ms,
E=2ms.....,0=16ms).
The interval times mentioned above are a direct function of the clock. The times indicated above
are for a 8MHz clock. If the clock frequency is 4MHz (mini floppy), all the times are twice as long as
the times indicated above. If the cloek frequency is 16MHz(Perpendicu1ar Magnetized Floppy), all the
times are half as long as the times indicated above. The ND bit is a flag to select the DMA operation or
non-DMA operation. If ND is in a high level then non-DMA mode is selected, and if ND is in a low
level then DMA mode is selected.
SENSE DEVICE STATUS COMMAND
The processor may use this command whenever it wishes to know the status of the FDDs. The drive
status information is contained in ST3.
TC8569AF-46
ToiHIBA tdc/up)" -i:,ruiTo -IZI Ju:viiGCrii:riisaai, Ill, IZITOSEI
FLOPPY DISK CONTROLLER (lil
CONFIGURATION COMMAND
This command is used to select the data format and write gate timing. The FMT bit indicated the
data format. When this bit is "I" pre-erase format is selected, and standard IBM format is selected
when this bit is "O".
The WG bit indicates the write gate timing. When this bit is "I" the timing for pre-erase head is
selected. In this case write gate is activated after 3 byte following ID area. When this bit is "o"
conventional timing is selected. In this case write gate is activated from SYN C area. Default value of
these bits are "0" (Conventional FDD).
TABLE 5.2.7e FMT/WG VALUE vs. DRIVE/MEDIA COMBINATIONS
DRIVE MEDIA FMT WG
Perpendicular 1 1
Perpendicular Magnetized FDD Magnetized FDD
Conventional FDD 0 1
Conventional FDD Conventional FDD 0 0
INVALID COMMAND
If an invalid command (a command not defined above) is send to the FDC, the FDC terminates the
command. The FDC does not generate the interrupt signal during the Result-Phase. Bit 6 and bit 7 in
the main status register set to both high levels indicates to the processor that the FDC is in the Result-
Phase and that the contents of STO must be read out. STO is set to a 80H showing that an invalid
command was received.
The sense interrupt status command must he sent after and interrupt of the seek command or
recalibrate command has occurred, otherwise the FDC regards this command as invalid. The users
may use this command as a non-Op command to place the FDC in a stand-by or non-operation state.
T08569AF-47
TC8569AF-48
Wait for
command><__ C-Phase ———>§<——‘ E-Phase
Wait for
R-Phase command
Signal t INT
/--N'/
system DRQ
— DACK
main -RD
system
iii? 'WR—U‘lnr'lrlru u nu g? "‘
STATUS
- .-, /
- s..-...-----'-----...-...---
NDM --
--- I H
___ --r----
2rd 3rd 59W“
data data ........ data
data of data field
v-------- .....
___ ---t-------------------
'"* Receive DTL
“‘> Receive GSL
""—-* Receive EOT
" """" * Receive N
" """""" '> Receive R
--------- >' Receive H
---------- '>' Receive C
‘- ----------- '> Receive HD, US
---------------- '> Receive Command
___. _-...,-- ._....._.__-........._._......._.._I
Register
- --r------------------
- -_.-------------------------
---i---_----------------------------
___ -.j-----------------------u
-----+--.--------.------------------g
..... ---+-----------------------
_---.-....--....---....---..-'
- -.--_... -i--------------u
___...- _------.-----"
e--,,..-..-.----......----...."
----------------- Set 572
L --------------------- Set 5T1
_______________________ Set STU
Non-DMA Mode
DMA Mode
No data transfer occured when READ ID
These are not executed when READ ID
FlG.5.2a READ DATA, READ DELETED DATA, READ DIAGNOSTIC, READ ID
m] FLOPPY DISK CONTROLLER
TOSHIBA (UC/UP)
ELIE D I: ”IUCNELIEI 003563? Mi? IZITOSEI
Wait for
command
C-Phase
Signal to
system
Signal
system
'v - LMV
Wait for
command
R-Phase ————> <—-—-
/--N''/
'y'""'''''"'""""""'"" rm -
-Ni9Vsif%r
lll|'—lllI_IJlIlJ
STATUS DIO
Register
TC8569AF-49
CB—I-r
----------t------------------."
-.-.- - - o-
rwNrNp'hreNewNkw'_
Receive
1st data of
ID field
'> Receive/DTL STP/D
"' ’ Receive GSL/GPL
'L ----- > Receive N
....... > Receive R
_________ p Receive H
___------_-.> Receive C
............. > Receive HD, US
- _-.._ r----------------.....----.-.---.
--- __....-. -- i------......----.-----.-....,
...._- _--... o------------------------..,..-..'
___I.___. w.----......-------.---.,.----.--."
_______________ ,. Receive Command
Receive
2nd data
___.J -. ........ ._’
Receive
last data
"Set N dummy
_____ Set R data
--------- Set H
------------- Set C
L ——————————————— Set 5T2
--------------------- Set 5T1
------------------------- Set 5T0
- .0“.-- .-------.
- _______d ._.._____.I
- --..,.-..-------.---u
_ m.-------..-..--------.-.
4 _---...,--------....-----..,
- --.--- ._____.........______.._...____._.l
*1 : Non-DMA Mode
*2 : DMA Mode
*3 : These are not executed when WRITE ID
FIG 5.3b WRITE DATA, WRITE DELETED DATA, WRITE ID
“I WWII
FLOPPY DISK CONTROLLER (ll
ENE I) © 90972”? 0025638 T99 CUTOSB
TOSHIBA tuc/up)"
TOSHIBA (UC/UP)
ELIE 1) I: quanta Mii%83n niiiEiro:i;s,
llll FLOPPY DISK CONTROLLER
Wait for command _ C-Phase R-Phase - Wait forcommand
Signalto INT " "
main system DRQ 0
’ -DACK "I"
Signal from -WR I II
main system
"s -RD I
"" RQM II I
I I l I
Status DIO I l I I
l r l t
I I i I
ss CB l s a a
_..__,... -....-.
', I l . -.i-.e-_----_.. Setdummy data
l l L ---------- SetST3
l I.-.» Receive HD, US Data
I . Register
'----- Receive command
FIG 5.3c SENSE DEVICE STATUS
Wait for command C-Phase Wait for command
/ Moll
Signal to INT " "
mainsystem DRQ 0
" -DACK
Signal from -WR I II II
main system
" RQM I I I I I
Status DIO i
's. C8 I
L") Receive ND
_____ ' Receive SRT Data Register
_________ - Receive com mand
FIG 5.3d SPECIFY
TC8569AF-50
TOSHIBA (UC/db; ----"
335437 E5 m:iciiwperdoiii,aG bu? tJTdsé
FLOPPY DISK CONTROLLER III]
. . . f
Wait forco___>mmand - C-P'nase - e---- E-P'nase .----_ - C-Phase .Fe-- R-Phase ---F 1dvai-tforsco11! orcommand
Signalto INT
mamsystem 's DRQ "o
-DACK "I''
Signal from -WR I II I I
main system _
-RD II II
’ RQM I I I I I I I I
I I I I - A K
, l ', f I l t
DIO ', I I I I I I
Status i , f l E E -e----
I I l ' I I I
095" l I i l : l I
038 ---F--1,-l- ( g -f---'r----
l ' I I I I
CB f l E g i l l
rs, ---..1. i , . I l . .---.-.
l I t t I I I
t l l I t l t
*Tnis is not I i l I I I I
executed when I I '---- Receive NCN* Lceive I tl ..- Set dummy data
RECALIBRATE l L---- Receive us gjgiter command,' L --_-.r- SetPCN
L ---_... _ Receive command I‘ ------------- Set STO
FIG 5.3e SEEK, RECALIBRATE & FIG 5.3f SENSE INTERRUPT STATUS
Wait for command C-Phase R-Phase Wait for command
" "o''
Signal to MT " "
main system DRQ 0
" -DACK " I"
Signal from AVR l
mmn system
Status Dio l l I
l : ',
\ C8 5 'I I
-"-t"'
t' l l
_ ', c---. Set dummy data
Receive INVALID L __________ Set STO
command or Si command
(without pending
interruption)
FIG 5.39 INVALID ID
Data Register
TC8569AF-51
TC8569AF-52
C8. 4 §
m_Um §
-m<<\mmmx \\§m wfimnmnmsaam a1,2 \ \\\\§A
xmmnE am: ox
msi \\ \\\ \ gwx \\\\\\Mw\ \
\ \ \\ \\ \\§\x\\\\\\\\\\§« mm
5% 335» 92m 6.28. 93 2% wm 98 22a 6
m :nm 03» m =8 0::
n u Umam .58 U u
mm mm: xm>U U>._.>. mm>o UmrmAmD 0.51? xmbu UszOmjn wm>U :u
IS ” ANmfimmzqsm ijEanmHma
_<:n_<: Ewfimmzam mmr
ll I FLOPPY DISK CONTROLLER
bHE I) IE “IDENBLI‘I UUEEBHL 563 EITOSB
"TOSHIBA (UC/UP)
TOSHIBA (UC/UP) - - DE B 7:7 1irriiriarouaiiirrcri-l:1::lio:i-s
FLOPPY DISK CONTROLLER lill
last sector
Write of
+~——>[Time indicated GSL
—>;«13yte
GAP3 SYNC Area
Data Area Splice point
‘~3 Byte ((
GAPZ SYNC ((
1f ;_1L___/r
Splice pomt
//////%<
I DA rea
FIG 5.3i WRITE DATA, WRITE DELETED DATA (PFD)
Ready WPRT Check
/////Z///
Track Format
llIll"!!!HIIHIIINIUIWHW
U/fl’ /
WDATA 7
U50, 1
a', 't
T08569AF-53
TOSHIBA (UC/UP)
3037:3qu DUEEBH3 Nil, DTOS3
MFLOPPY DISK CONTROLLER
(CHW) VLVCI 03.1.3130 ELLIZ-IM 'ViVC] ELLIHM [E'S 9H
Ulod a): d
1 . .l f eaJv Bled lugfdaaglds
cu DNAS EdVD SS DNAS ZdVD eerC” .‘JNAS
exfiaL—>: <— alkaZ—A ?<—
159 pawnpw ewuy<—+ ' '
‘-—J SS §\——+/ M
/ W/ /%x 8% W // / //
%/ /)¢V// / % 5% W // / mm
4:13:91 315;: MS \__$ /I >PatD mam 'Aavaf 3M
W//// /
aAng Smuiueas ums WNEBS/MH'
X WK 3CIIS
\ W L’Osn
TC8569AF-54
T bhE I) E anvauq i:ioieiV, aaa't3?b$§
FLOPPY DISK CONTROLLER llil
Toiuo:i3ai./c/upn
w,--'"'" w,,,,---'"-).'","',, Lu.
lt, )fi
V't 'c-c''"; a..
G?...... m
o."- m
32:: s.-..e".'."2.'.t spC..tt ,1.e; sp.CC.? tV
'ii' 'il
a ir-i-l
--'ss-c--iiii1itiiiii-ii ----- E
‘. red";: D.
"rr))):),), \\
Track format
READY WPRT Check
WHllIIHNWHWIHIU
use 1 M
SIDE y/flx
MFM // ,
1hdl n: 5 'a "u
3 t; b a cu a ($2
ti' u.. _I E E 3 EC;
TC8569AF-55
TOSHIBA (UC/UP) ELIE D I: mvrhelici unaiéaiis Lee Eifosa
llll FLOPPY DISK CONTROLLER
#n #0 #(n-1) #n #(n+1)+‘(n+3) fn #(n+1)#(n+3) #n #(n+1)
US0,1 iii)( c; ( )(T)( )(T)( X
SIDE ' 5 \
' (( ff ff
l H n H
I th-- H,
-Rw/sEEK.iiiiiiiiiiiiiiiiiiiiiiikt'1i/
DIR igiiiiiiiiiE5r X58 )(5 X
TStable
(no step pulse)
1 Cycle ------F
Period defined by the
SRT in SPECIFY command ,
Generate at 152/
scan operation
q #n meansthe drive number which is assigned by USO,1
(Drive number is 0 to 3, so that, n = 3 then n ol means 0)
o The READY check is done to the drive which assigned by USO, 1
FIG 5.3l SEEK, RECALIBRATE
USO, 1
"IIN/SEEK
Clue MiN 2us MIN (8MHz)
2 SIDE
Signal reception
TRKO Signal
WPRT Signal reception
FIG 5.3m SENSE DEVICE STATUS
TC8569AF-56
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FLOPPY DISK CONTROLLER “u
Toskriltt/chspl
5.2.8 RESULT STATUS REGISTER
RESULT STATUS REGISTER 0 (STO)
BIT SYMBOL NAME DESCRIPTION
D7 = 0 and D6 = 0
Normal termination of command (NT), command was
completed and properly executed.
D7 = 0 and D6 =1
Abnormal termination of command (AT). Command
D7 execution was started, but was not successfully completed.
IC Interrupt code
D6 D7=1andD6=0
Command was invalid command (1C). The command which
has been issued was not started.
D7 =1 and D6 =1
Abnormal termination because of the changing of the
ready line from the FDD during the execution of command.
D5 SE Seek End This flag is set to a
completed.
' when the seek command was
When the track 0 signal was not set to a "I" after 255 step
D4 EC Equipment Check pulses during the recalibrate command, this flag is set to a
When the FDD is in the not-ready state and a read/write
command is issued, this flag is set. For example, when a
D3 NR Not Ready read/write command is issued for side 1 of a signal sided
drive, this flag is set.
D2 HD Head Select This flag indicates the state of the head at interrupt.
3; (lil Drive Select 0,1 These flags indicate the drive number at interrupt.
TC8569AF-57
TOSHIBA (UC/UP) ENE I) III 909'?qu UUEEBH? TTh L_JTOSB
llll FLOPPY DISK CONTROLLER
RESULT STATUS REGISTER 1 (STI)
BIT SYMBOL NAME DESCRIPTION
D7 EN End of Cylinder This flag is set when the FDC tries to access a sector beyond
the last sector of a cylinder.
D5 DE Data Error This flag is set when the FDC finds the CRC error either in
the ID field or the data field.
This flag is set when the FDC does not receive the service
D4 OR Over Run from the main system during data transfers within a
certain time interval.
Cl This flag is set when the FDC can not find out the sector
specified in the IDR during the execution of following
commands.
READ DATA
READ DELETED DATA
WRITE DATA
D2 ND No Data WRITE DELETED DATA
Cl This flag is set when the FDC can not find the ID field
without the CRC error during the execution of the
READ ID COMMAND.
El This flag is set when the starting sector cannot be found
during the executing the READ DIAGNOSTIC
COMMAND.
This flag is set if the FDC detects the write protect signal
from the FDD durig the executing folowing commands.
D1 NW Not Writable WRITE DATA
WRITE DELETED DATA
FORMAT
El This flag is set if IDAM cannot be found out until the
. . FDCfindstheindex halltwice.
DO MA Missing Address Mark E] This flag is set if the FDC cannot find the DAM or
DDAM. The MD flag of ST2 is also set in this case.
TCB569AF-58
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FLOPPY DISK CONTROLLER 1lll
RESULT STATUS REGISTER 2 (ST2)
in Data Feid
BIT SYMBOL NAME DESCRIPTION
While executing the READ DATA, this flag is set when the
FDC finds out the sector with the DDAM. During executing
D6 CM Control Mark the READ DELETED DATA COMMAND, this flag is set when
the FDC finds out the sector with the DAM.
D5 DD Data Errorin Data Field Tizizflag IS set when the FDC detects a CRC error m data
This flag is set when the contents of C on the medium is
D4 NC No Cylinder differrent from that stored in the IDR. This flag is related
with the ND flag.
D3 - This bit has no meaning.
D2 - This bit has no meaning.
This flag is set if the content of C on the medium is FF and
D1 BC Bad Cylinder differs from that stored in IDR. This bit is related with the
ND bit.
DO MD Missing Address Mark This flag is set if the FDC cannot find out the DAM or
DDAM while the data are read from the medium.
RESULT STATUS REGISTER 3 (ST3)
BIT SYMBOL NAME DESCRIPTION
D7 This bit has no meaning.
D6 WP Write Protect This bit indicates the state of the write protect signal from
the FDD.
D5 RDY Ready This bit indicates the state of the ready signal from the
D4 TKO Track 0 This bit indicates the state of the track 0 signal from the
D3 This bit has no meaning.
D2 HD Head Address Je; bit indicates the state of the head select signal to the
D1 DS1 Drive Select1 :33 bit indicates the state of the drive select 1 signal to the
DO DSO Drive Select 0 This bit indicates the state of the drive select 0 signal to the
TC8569AF-59
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illl FLOPPY DISK CONTROLLER
5.3 VFO UNIT
5.3.1 VFO UNIT BLOCK DIAGRAM
LPF1 LPF2 CONT
MFM CHARGE PUMP
XRATE1 o--- CLOCK
XRATEO GEN.
SWITCH
-RDT DIGITAL CWIND
SYNC/GAP SEQUENCER Timing RDTA
DETECTOR Adjust
VFORST
FIG.5.3.1 VFO BLOCK DIAGRAM
TC8569AF-60
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5.3.2 DESCRIPTION OF EACH BLOCKS
(1) Time base generator/Divider circuit
This block consists of 16MHz crystal oscillator and divider. It generates all timing signals for
VFO operation. The operation mode MFM and MIN signals change the divisor of these timings.
XRATEO XRATEO FLOPPY MODE MODULATION fDW (KHz)
MFM 5 0
0 0 Standard Floppy 0
FM 250
0 1 - - -
MFM 250
1 0 Mini Flo
ppy FM 125
1 1 Vertical Floppy FM 000
(2) Sync gap detector/digital one-shot
SYNC pattern detect circuit when the PDC begins the read operation. SYNC pattern "00" is
continuance pulse series whose interval is TSYNC. This circuit judges to be SYNC the pulse series
whose interval is within TSYNC, and the other pulse series to he GAP. When 16MHz clock is applied
in [XIN] terminal, the value of TSYNC are as follows.
XRATEO XRATED FLOPPY MODE MODULATION TSYNC (ps)
MFM 1.68 ' 2.25
0 0 Standard Floppy
FM 3.38 - 4.93
o 1 - - -
MFM 3.38 ' 4.93
1 0 MiniFIoppy
FM 6.80 - 10.0
MFM -- 1.20
1 1 VerticalFlo
ppy FM
TC8569AF-61
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TOSHIBA (UC/UP) bHE 1) El 130973“! DUEbBSl HEB EZITOSB
Ill! FLOPPY DISK CONTROLLER
(3) Voltage Controlled Oscillator (VCO)
This VCO is automatically adjust its center frequency using PLL circuit. When 16MHz is used for
[XIN] clock, 2MHz is the frequency at VCONT voltage is 2.5V. The conversion gain via voltage on
VCONT terminal is as follows.
Kv = 2.5 X 106 [rad/sec V]
(4) Timing Adjusting Circuit
This circuit regenerates data and clock bit in MPM signal so as to get best read margin against the
peak shift phenomenon in the data from the FDD.
(5) Sequencer
VFO start its operation with the starting of read request from the FDC. The sequencer controls all
operation that is, hunting SYNC pattern, detecting address mark, changing PLL filter constant etc.
5.3.3 VFO OPERATION FLOW OF VFO
The operation of the VFO part is explained as the combination of the control mode of each circuit. The
mode of each part which concerns the VFO operation is as follows.
[Phase Comparator]
One input of the phase comparator is the window signal which is the divided signal of the VCO output.
The other input is either the read data or standardized clock from [XlN] whose frequency is the same as
window signal.
There are things to switch the charge pump outputs and to change the gain of phase comparator in
order to distinguish look state from unlock state of the VCO.
[External Input]
SYN C .' Input to indicate that the FDC is in read data,
VFORST ', Pulse generated by internal FDC when the FDC becomes SYN C state, and when the
first data byte after sync detection is not address mark and the FDC begins to search
next sync pattern.
VFO has three transition states as follows.
th VCO is tracing for basic clock froleIN] 16MH2 with high gain.
QH VCO is tracing for read data with high gain.
th. VCO is tracing for read data with low gain.
TC8569AF-62
TOSHIBA (UC/UP) ELIE 1) El quwaua 0025552 359 Erios3
FLOPPY DISK CONTROLLER llll
There is SYNC/GAP detector to control state transition except mentioned above. This circuit always
checks read data pulses. If there is a pulse without regular interval time, GAP is outputted. This output
is held for 8 bit time, SYNCD is outputted when there is no GAP output during 4 byte time FIG.5.3.3a
shows VFO states tranSition flow. FIG.5.3.3b shows the timing of VFORST which the FDC outputs.
SYNC = 0
re'' ( SYNC=0
/ SYNC=1 l
GAP=1 + SYNC=1
\vromm SYNC=1&GAP=0
FIG.5.3.3a VFO STATUS TRANSITION
TC8569AF-63
TOSHIBA (UC/UP) - ELIE DA © auavaua 0025553 afs CIToszi
lil FLOPPY DISK CONTROLLER
(i) FDC SYNC SEARCH
SYNC SEARCH MODE
FDC SYNC ON
Data/Clock
EXCHANGE
=caCfvo.o No
ID? NO
FlG.5.3.3b VFORSTTIMING
TC8569AF-64
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FLOPPY DISK CONTROLLER llll
TOSHIBA (UC/UP)
5.3.4 FILTER CR CONSTANT OF VFO
When the VFO is used in the alternative filter switching mode, the external components for the low
pass filter are needed as follows.
LPF2 ---MA
R3 I CI C2
CONT l
FIG.5.3.4 FILTER CIRCUIT
Recommended CR constant for leps, 500Kbps and 250Kbps is as follows. The accuracy of component
is less than 5% each.
TC8569AF-65
TOSHIBA (UC/UP) ENE J) III anemia?! uuébaés ova iZITosa
llll FLOPPY DISK CONTROLLER
Also, when the VFO is used in a fixed filter non-switching mode, the external components for the low
pass filter are needed as follows.
CONT l
FIG.5.3.4b FILTERCIRCUIT
Recommended CR constant for MIN and STD mode is as follows.
R1 15m
R4 3.9KO
c2 0.01pF
TC8569AF-66
ELIE 1) CI "i/di/arp:-, maidsir"dii h?osi
FLOPPY DISK CONTROLLERHH
TOSHIBA (UC/UP)
5.3.5 VFO TIME MARGIN
(1) Outline of time margin
Raw data being read from floppy disk drive have dynamic/static data rate variations on account of
the variation in the rotational speed of disk (for example, wow flatter) . On high density recording,
magnetic effects cause read data to move to early or late position, which is called peak shift. Raw
read data are influenced by the variation in disk speed on both writing and reading, which is
regarded as low speed variation. The VFO is designed to track this variation. On the other hand, it
is necessary to reduce the variation by peak shift, because its frequency is near the data transfer
frequency.
Example l Waveform in case of data 6B2 in MFM mode for mini-floppy
DATA BYTE 6 B 2
DATA BIT 0 l 1 I 1 l o 1 I o l 1 I 1 0 L 0 I 1
“gall? C D D D D D C D
I I I I I I I I
6ps -,i.. 4ps ju. 8ps i..' 8ps -i.. 4ps c:', tips i.: tips
PEAK SHIFT
WRITE I I I I I I I I
DATA : 5.5ps i... 5ps i. 7.5ps i' 7.5ps i; 5ps i, 5.5ps i.. tips ,
WINDOW T
FlG.5.3.5a EXAMPLE of PEAK SHIFT
In the example above, there are + 0.5ps pulsejitters by peak shift. The VFO operates to track the
variation in disk rotation but to ignore the variation of this peak shift, and then generates the
WIND ow signal to sample data accurately. The time margin is the tolerance for the peak shift. This
value in the case of an ideal VFO is a half of the cycle of the bit transfer rate. It is 2ps in MPM mode
for mini-floppy (250Kbps) .
”limb“!
TC8569AF-67
TOSHIBA ttlc/OP)
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ELIE D III 9097211“! 002565? TUI CITOSEI
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
VSS = 0V (GND)
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage VDD -0.5 ' +7.0 V
Input Voltage " VSS-0.5 ' VDD+0.5 V
Operating Tom - 30 ~ + 70 "C
Temperature
Storage Temperature TSTG - 65 ' + 125 'C
Output Current lotm i 2 (*1) mA
Output Current Ioun f. 8 (*2) mA
Output Current lour3 ' 3 (*3) mA
Power Dissipation PD 300 mW
(note) if LSI is used above the maximum ratings, permanent destruction of LSI can result.
In addition, it is desirable to use LSI for normal operation under the recommended
conditions. If these conditions are exceeded, reliability of LSI may be adversely
affected.
*1 (Output terminal group 1)
*2 ( Output terminal group 2)
*3 (Output terminal group 3)
WDT1, WE, HS, HL, MEND~1, DSO--1, STP, DR,
MDSLO--1, LWDEN
The other output terminals and Data bus
6.2 RECOMMENDED OPERATING CONDITIONS
VSS = 0V (GND)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT
Operating Temperature to’PR - 30 . + 70 "C
Supply Voltage VDD 4.75 5.25 V
Clock Frequency Fc 15.5 16.5 MHz
TC8569AF-68
--_ ---- ,iu_ ---_=
TOSHIBA (UC/UP) but: 1) I: anavau; 3025353 65? IZITOSB
FLOPPY DISK CONTROLLER , ,
6.3 DC CHARACTERISTICS TENTATIVE
VDD = 5.0V i: 5%, VSS = 0V (GND), tOPR = - 30~ + 70°C
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Hysteresis Width (*2) Wm 0.2 V
High Level Input Current (*1) IIHI 2.5 500 pA
VIN =VDD (*2) (*3) lm23 - 10 10 11A
Low Level Input Current (*1) hm --500 -2.5 11A
VIN=0V (*2) (*3) IIL23 --10 10 PA
High Level Input Voltage (*1) Vim 3.5 VDD V
(*2) VIH2 2.4 VDD V
(*3) Wm 2.2 VDD V
Low Level lnputVoltage (*1) VILI 0 1.2 V
(*2) Wu) 0 0.58 V
(*3) V1L3 0 0.8 V
High Level Output Current (*4) 10m - 0.5 mA
VOH =VDD - 0.4V (*5) IQHZ - 3.0 mA
(*6) IOH3 - 2.0 mA
Low Level Output Current (*4) 10” 0.5 mA
VOL = 0.4V (*5) Ion 6.0 mA
(*6) loL3 2.0 mA
Power Supply Current (*1) IDm 20 40 mA
Standby Current lam 100 pA
*1 (Inputterminal group 1) : XIN
*2 ( Input terminal group 2) : Schmitt trigger input : -RDT, ADX, -RDY, -WP, mo,
-DSKCHG
*3 (Input terminal group 3) : The other input terminals and Data bus
*4 (Output terminal group 1) : XOUT
*5 ( Output terminal group 2) : Output from FDD : WDT1, WE, HS, HL, MENO~1, DSO-I, STP,
DR, MDSLO--1, LWDEN
*6 ( Output terminal group 3) : The other Output terminals and Data bus
TC8569AF-69
TOSHIBA (ucfup)
llll FLOPPY DISK CONTROLLER
ELIE 1) CI 90972”? 002585“! 713 lilTOSB
AC CHARACTERISTICS TENTATIVE
VDD = 5.0V i 5%, VSS = 0V (GND), tOPR = - 30-- + 70°C
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Clock cycle time tcy 40 ns
Clock high level width tCH 20 ns
AEN setup time before -IOR tAENR 0 ns
AEN hold time after-IOR tRAEN 0 ns
-CS setup time before -IOR tSR 0 ns
-CS hold time after -IOR tag 0 ns
Address setup time before -lOR tAR 20 ns
Address hold time after -IOR tRA 0 ns
Data delay time from -IOR tag 100 ns
Data float delay time after -IOR top 20 100 ns
Pulse width of -IOW tRR 200 ns
AEN Setup time before -|OW tAENw 0 ns
AEN hold time after -IOW tWAEN 0 ns
-CS setup time before ..low tsw 0 ns
-CS hold time after -IOW tws 0 ns
Address setup time before -IOW tAw 20 ns
Add ress hold time after -l0W tWA 10 ns
Data setup time before -IOW tow 20 ns
Data hold time after -IOW two 10 ns
Pulse width of -KYN tww 200 ns
INTRQ delay time from-Km (*1) tRIR 250 ns
(*2) Rm 500 ns
INTRQ delay time from -|OW (*1) tune 250 ns
(*2) twm 500 ns
DMA cycle time (* 1) tDRQ2CY 7.5 115
(*2) tDRQZCY 13 ps
DRQ2 delay time from -DRQ (*1) tDDRQ 375 ns
(*2) tDDRQ 750 ns
T08569AF-70
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FLOPPY DISK CONTROLLER HI]
ITOSHIBA (UC/UP)
TENTATIVE
PARAM ETER SYMBOL MIN. TYP. MAX. UNIT
DRQ delay time from -DACK2 tACDitQ2 200 ns
..IOR delay time from DRQ2 tDRQ2it 0 ns
-lOWdeIay time from DRQ2 toito2W 0 ns
-IOR/-|OW delay time from DRQ2 (*1) tDRQZRW 7.0 ps
(*2) tDRQ2Rw 12 ps
Pulse width of -DACK2 (*1) tAA 125 ns
(*2) tAA 250 ns
-DACK2 setup time before -IOR (*3) tACR 0 ns
-DACK2 hold time after -10R (*3) tRAc 0 ns
-DACK2 setu p time before -lOW (*3) MON 0 ns
A9ACK2 hold time after AOW (*3) MAC 0 ns
Pulse width of DMATC , (*1) tTc 63 ns
(*2) trc 125 ns
RD7ENde1ay time from -IOR t7ENR 100 ns
RD7EN delay time from -lOR t7ENF 100 ns
RD7 delay time from -IOR tRmo 100 ns
RD7 flaot delay time man: 20 100 ns
DS setup time before STP (*1)(*4) tossr 10 ps
(*2)(*4) tDSST 20 ps
DS hold time after STP (*1)(*4) tSTDs 2 ps
(*2)(*4) tsms 4 ps
DR setup time before STP (*1)(*4) mg 0.5 115
(*2)(*4) tDST 1 ps
DR hold time after STP (*1)(*4) tsm 12 p5
(*2)(*4) tsro 24 115
Pulse width of STP (*1) tSTP 3 3.5 ps
(*2) tSTP 6 7 115
Pulse width of WDT1 (*1) twom 250 ns
(*2) twom 500 ns
-RDT low level width tRDm 130 ns
-RDT high level width titDD2 130 ns
-IDX low level width (*1) tle 125 ns
(*2) tIDx 250 ns
*1 : Value for Perpendicular magnetized floppy mode
*2 I Value for Standard mode. In case of mini floppy mode, each value is twice
*3 : AEN="High"duringthe DMAcycle
*4 : CDS="Low"
TC8569AF-71
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llll FLOPPY DISK CONTROLLER
6.4.1 AC TEST INPUT WAVE FORM
Inputterminal group1 : XIN
1.0V 1.5V (VIL)
lnputterminalgroup2 : Schimitttriggerinput
3.0V Ctr 2.4V (VIH) Ctr:
0.3V 0.6V. ( VIL)
Inputterminal group 3 : The other input terminals and Data bus
2.4V = 2.2V (VIH) rr)(rr
0.4V 0.8V (VIL)
6.4.2 OUTPUT LOAD CIRCUIT
TERMINAL
5.6kf2
TC8569AF-72
TOSHIBA (UC/UP)
6.4.3 TIMING CHART
C) Read Operation
A2.-A0
ELIE I) III “IUCNEHCI DOEHP'QF EE'IB Q7083
FLOPPY DISK CONTROLLER IO
tAENR tRAEN/r'_
----F A-------
tsa tRS
L-...,
- -» ,
tSR tas
tAR tan tRA
.____3 _"""-'-""-"'--""-
TC8569AF-73
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© Write Operation
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- tw -j
L-.-....-.-
"N tsw '." tws
A2--AO K
taw ‘tWA>
D7--DO
_ .----+ _ i
tow two
-lOW tww "_------------
TC8569AF-74
TOSHIéA (UC/UP)
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FLOPPY DISK CONTROLLER Illl
1fp Non-DMA Operation
- tRIR -
- twm ---F
(it) DMA Operation
tAcorua2 H
-DACK2 "N, ,
tACR -
-IOR ts,cw -----F
---tmuw, ---
- tsaozw ----F
llNlHI]IWIIWIIIW
TC8569AF-75
TOSHIBA (UC/UP) EHE I) © “109739“! Miela6la5 Th'? EITOSEI
(ill FLOPPY DISK CONTROLLER
6) Wave form of Terminal Count
©Seek Operation ( For CDS = Low, DSO~1)
- toss, ---F _ tsms -
- tDST -
STP I tsro
(LA=high) ir, tSTP I L
© Wave form of RD7,RD7EN
-lOR -"'"'""-] fC-"'--"
RD7 I--......-.-.-- -----! ----._
RD7EN ..._..._y?
TC8569AF-76
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FLOPPY DISK CONTROLLER ill;
Tosri:n3Crk/t.rh-
© Wave form of Write Data
(LA = High)
(9, Wave form of Read Data
-RDT -----ir--rt.rsrr)------
I taaoz ---F
(Kl Wave form of INDEX
"DX -------iT.rc.r.rr.)o------
WIWUIHHWNW!!!"
TC8569AF-77
TOSHIBA (UC/UP) LQVEini -i:':rcii:ftiriirici-ijr:iiii:0si,/lrirossi'
flll FLOPPY DISK CONTROLLER
7. PACKAGE DIMENSION
QFP80-P-1420 Unit : mm
25.6 i 0.3
I 20.0 i 0.2
1.0TYP
14.0:02 19.6h0.3
H 0.35i0.1 ' 0.1660
fl aua):szcs7::', I
2.7:t0.2
0.25 t0.15
note) Package width and length do not
include molding and tieber
protrusions. 'r,
0.15 -
I 1.63102 I
- 0.05 -
TC8569AF-78
www.ic-phoenix.com
.
