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TC6387XB
SD Memory Card / SDIO Card Controller
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
SD Memory Card / SD10 Card Controller
"r"C6387X
Outline
Rev. 1.0 2002-02-06
TOSHIBA CORPORATION
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE NO.1
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
Revision History
TITLE: TC6387XB Specifications
CONTENTS
REVISED
Released lst edition
S. Ueta
T. Takada
*Modified SD Control Register Map again(page 16).
*Regarding [4.7 SDLED signal], added the comments in detail(page 21).
*Regarding [4.7 Clock supply to SD Card], added the comments in
detai1(page 21-22).
*Added DC and AC specifications/page 26-40),
S. Ueta
T. Takada
*Regarding [4.1.2 Compact Flash (CF) Interface], defined that #STSCHG
of CF interface is not connected to TC6380AF signal(page 13).
*Added [Appendix](page42-46).
S. Ueta
T. Takada
Corrected the written(pagel4, red letters).
S. Ueta
T. Takada
Added each signal states in suspend mode(#SUSPEND=Low)(page24).
S. Ueta
T. Takada
200l-l2-20
Added an interrupt specification in detail(Pagel9-37).
S. Ueta
T. Takada
Regarding AC Characteristic, modified written max time to min time.
Regarding Attribute Memory Interface AC Characteristic, added a
specification of th0h8 (page 57).
Regarding SD Card Interface AC Characteristic, modified a specification of
Fpp (l6MHz-925MHz) (Page 59).
S. Ueta
T Takada
Deleted the function of CompactFlash Interface. Then, defined again HISEL
signal as RSV2 signal.
Deleted the function of SDICK. Then, defined again SDICK signal as RSVO
signal and CKSEL signal as RSVl signal.
Modified [4.5 Interruption].
Modified the recommended external resistances of #SDCD and SDWP
signals.
Added [6. Caution in coding device driver].
Added [B Reference diagram].
S. Ueta
T Takada
TOSHIBA CONFIDENTIAL
TOTAL 62
PAGE NO.2
TD s Fil II IA TC6387XB Specification
Rev. 1.0 02/02/06
Contents
1 Overview 5
1.1 Chip Specifications 5
1.2 Overview Specifications 5
2 Block Diagram 6
3 Signals 7
3.1 Pin Assignments 7
3.2 Pin Signals 8
3.3 Power Supply/GND (10 pins) 11
3.4 Summary: Interface Pins ll
4 Functionality Descriptions 12
4.1 Host Interface 12
4.2 Resource Area 12
4.3 Register Map 14
4.3.1 SD Host Controller Configuration Register 14
4.3.2 SD Control Register 15
4.4 Clock/Reset 16
4.4.1 Clock 16
4.4.2 Reset-related items 16
4.5 Interruption 17
4.5.1 SD card insertion interrupt by #SDCD 17
4.5.2 SD card removal interrupt by #SDCD 17
4.5.3 Buffer write enable interrupt 18
4.5.4 Buffer read enable interrupt 19
4.5 .5 Response end interrupt 20
4.5 .6 ww end interrupt 21
4.5.7 Illegal access error interrupt 22
4.5.8 Buffer underflow error interrupt 23
4.5.9 Buffer overflow error interrupt 24
4.5.10 Time out error(command) interrupt 25
4.5.11 Read data time out error interrupt 26
4.5. 12 Busy time out error interrupt 28
4.5.13 CRC status busy time out error interrupt 29
4.5.14 CRC status time out error interrupt 31
4.5.15 End bit error interrupt 33
4.5.16 CRC error interrupt 34
4.5.17 Command Index error interrupt 35
4.5. 18 Illegal function select interrupt 36
4.5. 19 SDIO Card interrupt 37
4.6 Card Slot Power Supply Control 38
4.6.1 SD Card Slot Power Supply Controller 38
4.7 SDLED signal 39
4.8 Clock supply to SD Card 39
4.9 Suspension 40
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TD s Fil II IA TC6387XB Specification
Rev. 1.0 02/02/06
4.10 Pull-up/down Resistance 42
4.10.1 Host Interface 42
4.10.2 SD Card Interface 42
4.10.3 System Interface 42
4.11 Connection example of SD Card socket 43
5 Electrical Characteristic 44
5.1 Absolute Maximum Standard 44
5.2 DC Characteristic 44
5.2.1 Recommended Conditions for proper performances 44
5.2.2 Host Interface DC Characteristic 45
5 .2.3 SD Card Interface Pin DC Characteristic 46
5.2.4 SD Card Power Supply Control DC Characteristic 46
5.2.5 System Interface Pin DC Characteristic 47
5.2.6 TEST Pin DC Characteristic 47
5.2.7 Power Consumption Characteristic 48
5.3 AC Characteristic 49
5.3.1 Host Interface Signal AC Characteristic 49
5.3.2 SD Card Interface Signal AC Characteristic 53
5.3.3 System Interface Signal AC Characteristic 54
6 Caution in coding device driver 55
6.1 Regarding a SD card insertion and removal 55
6.2 Regarding controlling Stop Clock Control Register 55
7 Package outline 56
Appendix 57
A TC6387XB function confirmation with standard memory interface 57
A1 Sample soft for standard memory interface of TC6387XB 57
A2 Wait mode specification 58
A.3 The wiring image of 16bit internal wait mode 59
A4 The wiring image of 16bit external wait mode 60
B Reference diagram 61
TOSHIBA-CONFIDENTIAL
TOTAL 62 PAGE NO.4
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
1 Overview
TC6387XB is a controller LSI for SD Memory Card/SDIO Card that comes in with interfaces for Standard
Memory with 16 bits bus. Also, TC6387XB meets SD Memory Card Physical Layer Specification and SD I/O Card
Specification. TC6387XB automatically detects card types and power supply just by inserting SD Memory Card or
SDIO Card.
By using buffer-off function of #SUSPEND signal and gated clock control, power consumption of the system
can be kept to a minimum.
1.1 Chip Specifications
- 0.35um CMOS Process
- 0.8mm ball Pitch 64-pin FBGA Package
(Body Size: 7mm x 7mm)
(Height : Max.1.2mm)
1.2 Overview Specifications
- Host Bus Interface
Standard Memory Interface
16 bit bus Interface
- Interruption Support
- Operating Frequency 33MHz
- Compatible w/ Power Supply Control LSI MIC2563
- Supports SD Card l Slot
- Meets SD Memory Card Physical Layer Specification
Ver.1.0 FBGA Package
Operating Frequency (Max. 25MHz)
MultiMedia Card Read/Write Capability
Compatible w/ 3.3V
Compatible w/ Multi Block Write/Read
Not compatible w/ SPI Mode
Within 5 12Byte*2 Double Buffers
- Meets SD I/O Card Specification Ver.1.0
Operating Frequency (Max. 25MHz)
Compatible w/ 3.3V
Compatible w/ Multi Block Write/Read
Though Toshiba specified TC6387XB DC supply voltage range(3.0v < Vdd < 3.6V) as recommended commercial
operating condition, SDIO card specification has different DC supply voltage range(3.1v < Vdd < 3.5V). Toshiba
recommend DC supply voltage range(3.1v < Vdd < 3.5v) in case customer use a SDIO card with TC6387XB as
recommended commercial operating condition.
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TOTAL 62 PAGE NO.5
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
2 Block Diagram
Svstem Bus .
l TC6387XB
Interrupt System Interface
Control Control
SD Memory Card /SDIO Card
Power Control Control Register
- Control
SD Memory Card / SDIO Card
Control
Power i
SD Memory Card
—> / SDIO Card
Switch
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TOTAL 62 PAGE NO.6
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
3 Signals
3.1 PinAssignments
Top View
1 2 3 4 5 6 7 8
A CLK32 RSVO TSTl #SUSPEND #HCS HA1 HA5 HA6
B SDPWR VDD TST2 RSVI HA2 HA3 VDD HA7
C VDD SDCD3 SDCD2 TSTO RSV2 HA4 HA8 HA9
D SDCLK SDCMD SDCDI vss vss HA10 HAll HDl
E SDCDO #SDCD SDWP vss vss HDO HD4 HD2
F SDLED HRDY #PCLR HD14 HD12 HD6 HD5 HD3
G #HINT VDD #HOE #HWE HD13 HDIO VDD HD7
H HCLK VSS #HBEH #HBEL HD15 HDll HD9 HD8
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TOTAL 62 PAGE NO.7
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
3.2 Pin Signals
Host Interface (33-pin)
NAME Pin IO VCC (V) F UN CTION/REMARKS
HD15 H5 System Data 15-0
HD14 F4
HD13 G5
HD12 F 5
HDII H6
HD10 G6
HD9 H7
HD8 H8 IO 3.3
HD7 G8
HD6 F6
HD5 F7
HD4 E7
HD3 F8
HD2 E8
HDl D8
HDO E6
HAll D7 I System Address ll-l
HA10 D6 I
HA9 C8 I
HA8 C7 I
HA7 B8 I
HA6 A8 I
HA5 A7 I
HA4 C6 I
HA3 B6 I 3.3
HA2 B5 I
HA1 A6 I
#HCS A5 I Chip Selection
#HOE G3 I Output Enabled
#HWE G4 I Write Enabled
#HBEL H4 I Byte Enabled L
#HBEH H3 I Byte Enabled H
HRDY F2 0 (OD) *1 Ready
*1 Levels cannot be converted.
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PAGE NO.8
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
Pin Signals gcont'd)
SD Card Interface (9-pin)
NAME Pin IO VCC (V) FUNCTION/REMARKS
SDCD3 C2
SDCD2 C3 SD Card /Data Bus
SDCDI D3 IO
SDCDO El
SDCMD D2 3.3 SD Card /Command
SDCLK Dl 0 SD Card /Divided HCLK Clock for SD Card(Max.25MHz)
#SDCD E2 SD Card /Detection
I SD Card /Write Protection
SDWP E3 Media is write-protected when this Pin indicates "High".
SDLED Fl 0 SD Card /LED signal
* Buffer with pull-up resistance
SD Card Power Supply Control (l-pin)
VCC (V)
FUNCTION/REMARKS
SD Card Power Supply Control. 3.3V Enable Signal
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
Pin Signals (cont'd)
SYSTEM Interface (5-pin)
NAME Pin IO VCC (V) FUNCTION/REMARKS
HCLK HI System Clock (max.33MHz)
CLK32 Al Used fer card detection and for Interruption detection when
3 3 HCLK lS stopped.
#HINT Gl 0 (OD) *1 . Interruption
#PCLR F3 I All registers are cleared when this signal is asserted
#SUSPEND A4 Suspend
*1 Levels cannot be converted.
TEST Pin (3-pin)
NAME Pin IO VCC (V) FUNCTION/REMARKS
$:$? i: I 3 3 Test Mode Signal 2,1,0 Utilized for Test Mode
. Set "000" for TST[2-0] under normal circumstances.
TSTO C4
Other Pin (3-pin)
NAME Pin IO VCC(V) FUNCTION/REMARKS
RSVO A2 Link to directl ound.
RSVI B4 3.3 Link to directl ound.
RSV2 C5 Link to directl ound.
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TOTAL 62 PAGE NO. 10
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
3.3 Power Supply/GND (10 pins)
NAME Pin FUNCTION/REMARKS
VSS H2, D4, E4, D5, E5 GND
VDD Cl, B2, G2, B7, G7 3.3V
3.4 Summary: Interface Pins
Interface
SD Card
SD Card Power Supply
Control
S stem SYSTEM Interface, TEST Pins, Other Pins
Power Su l
Grand Total
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE N011
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4 Functionality Descriptions
4.1 Host Interface
TC6387XB supports standard memory interfaces and the following suggests examples of circuits for
connecting to Standard Memory Interface:
Standard Memory TC6387XB
Al l-l HAI l-l
D15-0 HD15-0
-CS #HCS
-OE #HOE
-WE #HWE
-BEH #HBEH
-BEL #HBEL
-RDY HRDY
4.2 Resource Area
TC6387XB holds the following Resource Area:
l) SD Host Controller Configuration Area
2) SD Control Register Area
See below for mapping of SD Host Controller Configuration Area and SD Control Register Area. Further, SD Control
Register Area are mapped to any memory resources(800-FFFh) by setting BASE Address Register in SD Host
Controller Configuration Area.
Offset FUNCTION/REMARKS
000 - OFFh Reserved for Configuration Area
100 - lFF h Reserved for Configuration Area
200 - 2FFh SD Host Controller Configuration Area
300 - 3FFh Reserved for Configuration Area
400 - 7FFh Reserved for Configuration Area
800 - 8FFh SD Control Register
900 - 9F F h (BASE Address Register of SD Host Controller Configuration Register
A00 - AFFh -configurable in Offsetl0h--)
B00 - BFFh
C00 - FFFh
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TOTAL 62 PAGE NO. 12
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
- SD Control Register Area
As for accessing Resource in SD Control Register Area, use Configuration Register Base Address
Reg.(C0nfig.0ffset: 10h) in SD Host Controller for mapping the settings to access designated Memory Areas
(800-FFFh).
SD Host Controller Host Memory
Configuration Registers Space
Offset
Offset Base Address + 000 h
10 h -..._---------------> SD Control
Base Address ........... Register .......... Base Address + lFF h
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TOTAL 62 PAGE No.13
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
4.3 Register Map
TC6387XB holds internal registers for SD Host Controller.
SD Host Controller Configuration Register
SD Control Register
SD Host Controller Configuration Register
00 Port
Reserved 2
Reserved 3
Reserved l
Command
Reserved 5
Reserved 4 08h
Reserved 6 I
SD Control Register Base Address
20h-2Bh
Reserved 8
Reserved 7
Reserved 9 34h
Interrupt Pin
Reserved 10 3Ch
Clock Mode Gated Clock Control
Stop Clock Control 40h
Pin Status
Power Control?
Power Contr012
Power Control] 48h
Reserved l 1
Card Detect Mode 4Ch
SD Slot 50h
Reserved 12
Reserved 13
Reserved 16
Reserved 15
64h-7Fh
Reserved 14 80h
Reserved 19
Reserved 18
Reserved 17
Reserved 20
8C-EFh
Extend Gated Clock
Contr012
Reserved 21
Extend Gated Clock
Control 1
Reserved 24 Reserved 23
Reserved 22 F4h
SDLED Enable 1
Extend Gated Clock
Control?
Reserved 25 F8h
Reserved 28
SDLED Enable 2
Reserved 27
Reserved 26 FCh
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TOTAL 62 PAGE NO. 14
TDSIHIIIIA
4.3.2 SD Control Register
TC6387XB Specification
Base Address: SD Control Register Base Address (Conf. 10h)
Rev. 1.0 02/02/06
Offset 15-08 bit I 07-00 bit Offset 15-08 bit I 07-00 bit
002h SD Control Reserved 1 000h SD Command
006h Argument] 004h Argument0
00Ah Transfer Sector Count 008h Stop internal action
00Eh Responsel OOCh Response0
012h Response? 010h Response2
016h Response5 014h Response4
O l Ah Response7 018h Response6
OlEh SD Buffer Control & Error Status OlCh SD Card Status
022h SD Interrupt Maskl 020h SD Interrupt MaskO
026h SD Memory Card Transfer Data Length 024h SD Card Clock Control
02Ah --- 028h SD Memory Card Option Setup
02Eh SD Error Detail Status 1 02Ch SD Error Detail Status 0
032h --- 030h SD Data Port
036h --- 034h Transaction Control
03Ah --- 038h ---
03Eh --- 03Ch -
0E2h SD Control Reserved 2 OEOh SD Software Reset
0E6h SD Control Reserved 3 0E4h ---
OEAh --- 0E8h ---
OEEh --- OECh -
0F2h --- OFOh ---
0F 6h SD Control Reserved 4 0F4h ---
OFAh SD Control Reserved 6 0F8h SD Control Reserved 5
OFEh SD Control Reserved 8 OFCh SD Control Reserved 7
102h SD Card Port Selection 100h SD Command
106h Argument] 104h Argument0
10Ah Transfer Block Count 108h -
10Eh Responsel 10Ch Response0
112h Response? 110h Response2
1 16h Response5 1 14h Response4
1 lAh Response7 1 18h Response6
llEh SD Buffer Control & Error Status 11Ch SD Card Status
122h SD Interrupt Maskl 120h SD Interrupt MaskO
126h SDIO Card Transfer Data Length 124h ---
12Ah --- 128h SDIO Card Option Setup
12Eh SD Error Detail Status] 12Ch SD Error Detail StatusO
132h --- 130h SD Data Port
136h Card Interrupt Control 134h Transaction Control
13Ah SDIO Host Information 138h Clock & Wait Control
13Eh SDLED Control 13Ch Error Control
1E2h SD Control Reserved 9 1E0h SD Software Reset
1E6h --- 1E4h -
lEAh --- 1E8h ---
lEEh --- lECh ---
1F2h --- lFOh SD Control Reserved 10
1F6h --- 1F4h ---
lFAh --- IF 8h ---
lFEh --- lFCh ---
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TOTAL 62 PAGE NO. 15
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.4 Clock/Reset
4.4.1 Clock
TC6387XB holds the following two Input Clock Pins: HCLK, CLK32
(l) HCLK : System Clock Input (33MHz Max.).
Basic Clock for System Interface and internal operations.
(2) CLK32 , Clock Input for 32KHz. The interrupt signal, implied for a SD card insertion and detachment,
shall be generated synchronous to this signal. In addition, this signal is base clock, which input
to a register which set timeout error time on SD data from a SDIO card.
4.4.2 Reset-related items
- #PCLR: Reset Signal is asserted when power is supplied.
All registers(built into TC6387XB) are cleared by #PCLR.
Be sure to deactivate assertion of #PCLR when power supply and HCLK oscillation (better than lms) are fairly
stable.
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TOTAL 62 PAGE NO. 16
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5 Interruption
When the TC6387XB detects the each interrupt sources, TC6387XB asserts interrupt signals (#HINT). It is necessary
that the interrupt mask bits are released. This mask bits releasing is controlled by setting SD Interrupt Mask
Register(0ffset:020-023h, 120-123h). Each factor of the interrupt can be evaluated by referring to SD Card Status
Register(0ffset:01C-01Dh, llC-l th) or SD Buffer Control & Error Status Register(0ffset:01E-01Fh, llE-l th).
The details of each factor are listed below.
4.5.1 SD card insertion interrupt by #SDCD
+ Interrupt Assert Condition
When an SD card is inserted to a slot, #SDCD is lowered. This condition causes an interrupt to be generated.
#SDCD is not recognized as being lowered unless it remains in "0" state for the number of HCLK cycles specified
by CDM[1:0] of Card Detect Mode Register(Config Offset:4Ch). The interrupt is asserted in th timing of raising of
CLK32 from #SDCD low state.
+ Factor Evaluation Method
The SCIN bit(D4) of SD Card Status Register(Offset:01C-01Dh) is set to "1".
+De-asserting Method
(1) "0" is written into the SCIN bit(D4) of SD Card Status Register(Offset:0lC-01Dh).
(2) " 1" is written into the MCIN bit(D4) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:0EOh).
4.5.2 SD card removal interrupt by #SDCD
+ Interrupt Assert Condition
When an SD card in a slot is removed, #SDCD is raised. This condition causes an interrupt to be generated. After
#SDCD is high, the interrupt is asserted in th timing of raising of CLK32.
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
+ F actor Evaluation Method
The SCOT bit(D3) ofSD Card Status Register(0ffset:01C-01Dh) is set to " l".
+De-asserting Method
(1) "0" is written into the SCOT bit(D3) of SD Card Status Register(Offset:0lC-01Dh).
(2) " 1" is written into the MCOT bit(D3) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = " 'l
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:0E0h).
4.5.3 Buffer write enable interrupt
+ Interrupt Assert Condition
When data to be transmitted to the card becomes available for the internal buffer, SD Data Port
Register(Offset:030-031h, 130-131h), to be written for a write command, an interrupt is generated.
SDCLK I I I I I I
SDCD3-0 ""“\_C..i.....II..:I:i.i.i.IIIWEiiéifiéfiéwH.....i.WWIIff... CRC16
Write is enabled when the data is transf _
the internal buffer to the data transmission circ'
#HINT PPPPPFF_FF_FFFFlF__._ FPFF» -,
+ Factor Evaluation Method
In the case of SD memory Card, the SBWE bit(D9) of SD Buffer Control & Error Status Register(Offset:01E-
01F h) is set to " l". In the case of SDIO Card, the SBWE bit(D9) of SD Buffer Control & Error Status
Register(Offset:11E-11Fh) is set to "1".
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
+De-asserting Method
SD memory Card
(1) "0" is written into the SBWE bit(D9) of SD Buffer Control & Error Status Register(Offset:01E-01Fh).
(2) " l" is written into the MBWE bit(D25) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "O" into the SRST bit(DO) of SD Software Reset Register(Offset:0E0h).
SDIO Card
(1) "0" is written into the SBWE bit(D9) of SD Buffer Control & Error Status Register(Offset:llE-llFh).
(2) " 1" is written into the MBWE bit(D25) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = " ".
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(0ffset: 1E0h).
4.5.4 Buffer read enable interrupt
+ Interrupt Assert Condition
When one block of data from the card is stored fully into the internal buffer for a read command, an interrupt is
generated.
+ Factor Evaluation Method
In the case of SD memory Card, the SBRE bit(D8) of SD Buffer Control & Error Status Register(0ffset:01E-
Oth) is set to "l". In the case of SDIO Card, the SBRE bit(D8) of SD Buffer Control & Error Status
Register(0ffset:1 lE-l th) is set to " l".
+De-asserting Method
SD memory Card
(1) "0" is written into the SBRE bit(D8) of SD Buffer Control & Error Status Register(Offset:01E-01Fh).
(2) " l" is written into the MBRE bit(D24) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:0E0h).
SDIO Card
(5) "0" is written into the SBRE bit(D8) of SD Buffer Control & Error Status Register(Offset:llE-11Fh).
(6) "1" is written into the MBRE bit(D24) of SD Interrupt Mask Register(0ffset:120-123h).
(7) Hardware reset by #PCLR = "O".
(8) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:lE0h).
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5.5 Response end interrupt
+ Interrupt Assert Condition
After a response received from an SD card, an interrupt is generated. Regarding Rlb response type, after busy
released from an SD card, an interrupt is generated.
HCLK -lllllllllllllllllll_l-lll,
SDCLKlllllllllll,
SDCMD —| Endbit
SDCLK |_| |_|
SDCMD w
+ Factor Evaluation Method
In the case of SD memory Card, the SREP bit(D0) of SD Card Status Register(Offset:0lC-01Dh) is set to "1". In
the case of SDIO Card, the SREP bit(D0) of SD Card Status Register(Offset:l1C-llDh) is set to "1".
+De-asserting Method
SD memory Card
(1) "O" is written into the SREP bit(D0) of SD Card Status Register(Offset:0lC-01Dh).
(2) " 1" is written into the MREP bit(D0) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = " 'l
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:0EOh).
SDIO Card
(1) "0" is written into the SREP bit(D0) of SD Card Status Register(0ffset:1 lC-l th)
(2) " l" is written into the MREP bit(D0) of SD Interrupt Mask Register(0ffset:120-123h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:1EOh).
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5.6 R/W end interrupt
+ Interrupt Assert Condition
When read or write processing for an SD card is completed, an interrupt is generated.
SDCLK J
End bit of Write CRC Status
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PAGE No.21
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
+ Factor Evaluation Method
In the case of SD memory Card, the SRWA bit(D2) of SD Card Status Register(Offset:01C-01Dh) is set to "1". In
the case of SDIO Card, the SRWA bit(D2) of SD Card Status Register(Offset:11C-11Dh) is set to " l".
+De-asserting Method
SD memory Card
(1) "O" is written into the SRWA bit(D2) of SD Card Status Register(0ffset:01C-01Dh).
(2) " 1" is written into the MRWA bit(D2) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:0E0h).
SDIO Card
(1) "0" is written into the SRWA bit(D2) of SD Card Status Register(0ffset:llC-11Dh)
(2) " 1" is written into the MRWA bit(D2) of SD Interrupt Mask Register(0ffset:120-123h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:1E0h).
4.5.7 Illegal access error interrupt
+ Interrupt Assert Condition
When an incorrect command index is written into SD Command Register(Offset:000-001h, 100-101h), an interrupt
is generated. Each of the following cases is recognized as an incorrect index. (3) is only applying to SD memory
(1) SD Command Register is written before the previously issued command is not completed.
(2) Though the REP2-0 bits(D10-8) are set to 011b(no response), the NTDT bit(D11) is set to 1b(with data).
(3) Though the CMD1-0 bits(D7-6) are set to 00b and the CIX bits(D5-0) are set to 001100b(CMD12), the NTDT
bit(Dl 1) is set to 1b(with data).
HCLK Tlll,
SDCLK I I I-l-
HAI7-0]
#HWE —| J
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
+ Factor Evaluation Method
In the case of SD memory Card, the ILA bit(D15) of SD Buffer Control & Error Status Register(Offset:01E-01Fh)
is set to "1". In the case of SDIO Card, the ILA bit(DIS) of SD Buffer Control & Error Status Register(Offset:11E-
11Fh) is set to " l".
+De-asserting Method
SD memory Card
(1) "0" is written into the ILA bit(D15) of SD Buffer Control & Error Status Register(0ffset:0lE-OIFh).
(2) " 1" is written into the IMSK bit(D31) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = " ".
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(0ffset:0E0h).
SDIO Card
(1) "0" is written into the ILA bit(D15) of SD Buffer Control & Error Status Register(Offset:l1E-llFh).
(2) " 1" is written into the IMSK bit(D31) of SD Interrupt Mask Register(0ffset:120-123h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:1E0h).
4.5.8 Buffer underflow error interrupt
+ Interrupt Assert Condition
If the host reads SD Data Port Register when the data buffer is empty, an interrupt is generated.
SDCL L] M [_] [_f-I,
HA[7-0] 0x30 N,)
#HRE -l
+ Factor Evaluation Method
In the case of SD memory Card, the SFUF bit(DS) of SD Buffer Control & Error Status Register(Offset:01E-01F h)
is set to "1". In the case of SDIO Card, the SFUF bit(DS) of SD Buffer Control & Error Status Register(Offset:
11E-11Fh) is set to "l".
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
+De-asserting Method
SD memory Card
(1) "0" is written into the SFUF bit(DS) of SD Buffer Control & Error Status Register(Offset:0lE-01Fh).
(2) " l" is written into the MFUF bit(D21) of SD Interrupt Mask Register(Offset:020-023h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:0E00
SDIO Card
(1) "0" is written into the SFUF bit(D5) of SD Buffer Control & Error Status Register(Offset:l1E-llFh).
(2) "1" is written into the MFUF bit(D21) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(0ffset:1E0h).
4.5.9 Buffer overflow error interrupt
+ Interrupt Assert Condition
If the host writes SD Data Port Register when the data buffer is full, an interrupt is generated.
SDCLK |_l |_l |_| g [_l-l-
HA[7-0] 0x30 VI
#HWE fl /
+ Factor Evaluation Method
In the case of SD memory Card, the SFOF bit(D4) of SD Buffer Control & Error Status Register(Offset:01E-OlFh)
is set to "l". In the case of SDIO Card, the SFOF bit(D4) of SD Buffer Control & Error Status Register(0ffset:
11E-11Fh)is set to "l".
+De-asserting Method
SD memory Card
(1) "0" is written into the SFOF bit(D4) of SD Buffer Control & Error Status Register(Offset:0lE-01Fh).
(2) " l" is written into the MFOF bit(D20) of SD Interrupt Mask Register(0ffset:020-02310).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:0E0h).
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
SDIO Card
(1) "0" is written into the SFOF bit(D4) of SD Buffer Control & Error Status Register(Offset:l1E-llFh).
(2) " l" is written into the MFOF bit(D20) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "O" into the SRST bit(DO) of SD Software Reset Register(Offset:1E0h).
4.5.10 Time out error(command) interrupt
+ Interrupt Assert Condition
If the start bit of a response is not received within SDCLK period X 640(SD memory Card) or X 64(SDIO Card)
after the end bit of a command is transmitted to the card, this condition is considered a time out error and an
interrupt is generated.
+ Factor Evaluation Method
In the case of SD memory Card, the SCTO bit(D6) of SD Buffer Control & Error Status Register(0ffset:01E-
01Fh) and the NCR bit(Dl6) of SD Error Detail Status Register(0ffset:02C-02Fh) are set to "1". However, if a
response for automatically issued CMD12 is not received, the NRS bit(D17) is set to " 1" for differentiation.
In the case of SDIO Card, the SCTO bit(D6) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and
the NCR bit(D16) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "l".
+De-asserting Method
SD memory Card
(1) "0" is written into the SCTO bit(D6) of SD Buffer Control & Error Status Register(Offset:0lE-01Fh).
(2) " 1" is written into the MCTO bit(D22) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:0E0h).
SDIO Card
(1) "O" is written into the SCTO bit(D6) of SD Buffer Control & Error Status Register(Offset:llE-llFh).
(2) " 1" is written into the MCTO bit(D22) of SD Interrupt Mask Register(0ffset:120-123h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:1EOh).
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TDSIHIIIIA
4.5.1 1 Read data time out error interrupt
+ Interrupt Assert Condition
TC6387XB Specification
Rev. 1.0 02/02/06
If the start bit of data is not detected within the specified period after the end bit of a response for each read
command, an interrupt is generated. In the case of SD memory Card, the specified period is set in RTO[3:0] of
SD Memory Card Option Setup Register(0ffset:028h) in the form of a multiple number of the SDCLK period. In
the case of SDIO Card, the specified period is set in TO[3:0] of SD Memory Card Option Setup
Register(0ffset:128h) in the form of a multiple number of the CLK32 period. Read data time out error is classified
into between a command and a read data, and between a read data and a read data in a multiple block transfer.
*Between a command and a read data, time out
SDCMD =f"s1-----
Setti g time in
MHNT- FPFP_FPFFV
CLK32 F‘W
Setting tim' in TO3-0 bits
#HINT _-___
SDCMD =e-s PF.............--.........--..........- -.... . ....._.__............._lt.t.........._._lt............__
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
*Between a read data and a read data, time out
SDCLK J |_J [_] |_|
SDCD3-O -bCDattrCCRtrCEhiF" FF_VVVV PVFPFPFFFFP_VVVVVVVVPPFPFFFFFFFF ---.---
Setting time .
#HINT ,. .....................................
SDCLKJ I_l M |_l
CLK32 -]
SDCD3-O -yCDati5CCRrTrCErif' FF_FVV
Setting tim
+ Factor Evaluation Method
In the case of SD memory Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-
01Fh) and the NRCS bit(D20) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1".
In the case of SDIO Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:llE-11Fh) and
the NRCS bit(D20) of SD Error Detail Status Register(Offset:12C-12Fh) are set to "1".
+De-asserting Method
SD memory Card
(1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(0ffset:01E-01Fh).
(2) " 1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:020-023h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:0E0h).
SDIO Card
(1) "O" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(0ffset: l lE-l Wh).
(2) " 1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:1E0h).
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5.12 Busy time out error interrupt
+ Interrupt Assert Condition
If a busy declaration from the card (DATO = "0" after response end) remains longer than the specified time, this
condition is considered as a time out error and an interrupt is generated. In the case of SD memory Card, the
specified period is set in RTO[3:0] of SD Memory Card Option Setup Register(Offset:028h) in the form of a
multiple number of the SDCLK period. In the case of SDIO Card, the specified period is set in TO[3:0] of SD
Memory Card Option Setup Register(Offset: 128h) in the form of a multiple number of the CLK32 period.
CLK32 |_| ‘_|
SDCMD jL 'PF...........--............-.-
Setting time i TO3-0 bit
+ Factor Evaluation Method
In the case of SD memory Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-
01F h) and the NRCS bit(D20) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1".
In the case of SDIO Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(0ffset:11E-11Fh) and
the NRCS bit(D20) of SD Error Detail Status Register(0ffset:12C-12Fh) are set to "l".
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
+De-asserting Method
SD memory Card
(1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-01Fh).
(2) " l" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:020-023h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "O" into the SRST bit(D0) of SD Software Reset Register(0ffset:0E0h).
SDIO Card
(1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset: 1 lE-l th).
(2) " 1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = " ".
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(0ffset: 1E0h).
4.5.13 CRC status busy time out error interrupt
+ Interrupt Assert Condition
If a busy declaration from the card (DATO = "0" after Write CRC Status) remains longer than the specified time,
this condition is considered as a time out error and an interrupt is generated. In the case of SD memory Card, the
specified period is set in RTO[3:0] of SD Memory Card Option Setup Register(Offset:028h) in the form of a
multiple number of the SDCLK period. In the case of SDIO Card, the specified period is set in TO[3:0] of SD
Memory Card Option Setup Register(Offset:128h) in the form of a multiple number of the CLK32 period.
Setting tirr
SDCDO I l
#HINT ................................ j) 5) FF
End bit of Write CRC Status
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
End bit ofWrife CRC Status
+ Factor Evaluation Method
In the case of SD memory Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-
01Fh) and the KBSY bit(D22) of SD Error Detail Status Register(Offset:02C-02Fh) are set to " l".
In the case of SDIO Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(0ffset:11E-11Fh) and
the KBSY bit(D22) of SD Error Detail Status Register(0ffset:12C-12Fh) are set to " l".
+De-asserting Method
SD memory Card
(1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(0ffset:01E-01Fh).
(2) " l" is written into the MDTO bit(D19) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(0ffset:0E0h).
SDIO Card
(1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(0ffset: 1 lE-l th).
(2) " 1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:1E0h).
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5.14 CRC status time out error interrupt
+ Interrupt Assert Condition
If the start bit of CRC status is not detected within the specified period after the end bit of block data for a write
command, an interrupt is generated. In the case of SD memory Card, the specified period is set in RTO[3:0] of SD
Memory Card Option Setup Register(Offset:028h) in the form of a multiple number of the SDCLK period. In the
case of SDIO Card, the specified period is set in TO[3:O] of SD Memory Card Option Setup Register(Offset:128h)
in the form of a multiple number of the CLK32 period.
SDCLK _Tl_Tl_j
SDCDO Ty L
Setting ti
CLK32 m -] L] |_l Ll
Write CRC Status
SDCDO 7 \ '\__:
Setting time in
#HINT ""\
+ Factor Evaluation Method
In the case of SD memory Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset:01E-
01F h) and the NWCS bit(D21) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "1".
In the case of SDIO Card, the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset: l lE-l th) and
the NWCS bit(D21) of SD Error Detail Status Register(Offset: l2C-12Fh) are set to "l".
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
+De-asserting Method
SD memory Card
(1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(0ffset:01E-01Fh).
(2) " l" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:020-023h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "O" into the SRST bit(D0) of SD Software Reset Register(0ffset:0E0h).
SDIO Card
(1) "0" is written into the SDTO bit(D3) of SD Buffer Control & Error Status Register(Offset: 1 lE-l th).
(2) " 1" is written into the MDTO bit(D19) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = " ".
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(0ffset: 1E0h).
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5.15 End bit error interrupt
+ Interrupt Assert Condition
If a bit that should be the end bit for the response, read data or CRC status received from the card is "0", an
interrupt for detecting an incorrect end bit is generated.
SDCLK = _ l-]
SDCMD -End_bitr-,
+ Factor Evaluation Method
In the case of SD memory Card, the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:01E-
01F h) and the WEBER bit, REBER bit, SEBER bit and CEBER bit(D5-2) of SD Error Detail Status
Register(0ffset:02C-O2Fh) are set to "1".
In the case of SDIO Card, the SEND bit(D2) of SD Buffer Control & Error Status Register(0ffset:11E-11Fh) and
the WEBER bit, REBER bit and CEBER bit(D5-4,2) of SD Error Detail Status Register(Offset:12C-12Fh) are set
to "1".
Bit Name Error factor Notes
5 WEBER End bit error for Write CRC status
4 REBER End bit error for read data
3 SEBER End bit error of a response for automatically issued CMD12 Only SD memory Card
2 CEBER End bit error for a response (other than SEBER)
+De-asserting Method
SD memory Card
(1) "0" is written into the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset:0lE-01Fh).
(2) "1" is written into the MEND bit(D18) of SD Interrupt Mask Register(Offset:020-023h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(Offset:OE0h).
SDIO Card
(1) "0" is written into the SEND bit(D2) of SD Buffer Control & Error Status Register(Offset: 1 lE-l IF h).
(2) "1" is written into the MEND bit(D18) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "0" into the SRST bit(D0) of SD Software Reset Register(0ffset:1EOh).
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5.16 CRC error interrupt
+ Interrupt Assert Condition
If the CRC value for the response, read data or CRC status received from the card does not agree with the value
internally calculated by TC6387XB, an interrupt is generated
SDCMD ubanaaa.lu= _
SDCD3-0 C"''"-''"''":";;''.'';';?''""-')) g
SDCLK I I I I I I S I I I ,
+ Factor Evaluation Method
In the case of SD memory Card, the SCRC bit(Dl) of SD Buffer Control & Error Status Register(0ffset:01E-
01F h) and the WCRCE bit, RCRCE bit, SCRCE bit and CCRCE bit(D11-8) of SD Error Detail Status
Register(0ffset:02C-O2Fh) are set to "1".
In the case of SDIO Card, the SCRC bit(Dl) of SD Buffer Control & Error Status Register(0ffset:11E-11Fh) and
the WCRCE bit, RCRCE bit and CCRCE bit(D11-10,8) of SD Error Detail Status Register(Offset: 12C-12Fh) are
set to " l".
Bit Name Error factor Notes
11 WCRCE Write CRC status error for a write command
10 RCRCE CRC error for read data
SCRCE CRC error of a response for automatically issued CMD12 Only SD memory Card
8 CCRCE CRC error for a response (other than SCRCE)
+De-asserting Method
SD memory Card
(1) "0" is written into the SCRC bit(Dl) of SD Buffer Control & Error Status Register(Offset:0lE-01Fh).
(2) "1" is written into the MCRC bit(D17) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:OE0h).
SDIO Card
(1) "0" is written into the SCRC bit(Dl) of SD Buffer Control & Error Status Register(Offset:11E-11Fh).
(2) "1" is written into the MCRC bit(D17) of SD Interrupt Mask Register(0ffset:120-123h).
(3) Hardware reset by #PCLR = "O".
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(0ffset:1EOh).
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5.17 Command Index error interrupt
+ Interrupt Assert Condition
If the command index portion of the response received from the card does not agree with the index issued just
before, an interrupt is generated.
SDCMD c End bit _
+ Factor Evaluation Method
In the case of SD memory Card, the SCIX bit(DO) of SD Buffer Control & Error Status Register(0ffset:01E-
Oth) and the RCMDE bit(DO) of SD Error Detail Status Register(Offset:02C-02Fh) are set to "l". If a response
for automatically issued CMD12 is not normal, " l" is set to the SCMDE bit(DO).
In the case of SDIO Card, the SCIX bit(DO) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) and
the RCMDE bit(DO) of SD Error Detail Status Register(0ffset:12C-12Fh) are set to "l".
+De-asserting Method
SD memory Card
(1) "0" is written into the SCIX bit(DO) of SD Buffer Control & Error Status Register(Offset:01E-01Fh).
(2) " l" is written into the MCIX bit(D16) of SD Interrupt Mask Register(0ffset:020-023h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(0ffset:0EOh).
SDIO Card
(1) "0" is written into the SCIX bit(DO) of SD Buffer Control & Error Status Register(0ffset: 1 lE-l 1F h).
(2) " l" is written into the MCIX bit(D16) of SD Interrupt Mask Register(Offset:l20-l23h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(0ffset: IEOh).
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TD s Fil II IA TC6387XB Specification
4.5.18 Illegal function select interrupt
+ Interrupt Assert Condition
Rev. 1.0 02/02/06
Although a transaction is remaining on the SD bus, or a state of SD controller is acceptable, other function in
SDIO Card is selected by SD host controller, then an interrupt is generated.
HCLK (lil-l-l-l-lil-L
SDCLK -] l-l f-] l-] _
HA[7-O] 0x00 f
#HWE —I f,
SDCD3-0 Write data or Read data
#HINT "'"\
HCLK (lil-l-lil-l-l-l,
mm -I l-] l-] _ I--]
HA[7-0] 0x00
#HWE —I
SDCD3-0
#HINT \—
+ Factor Evaluation Method
The ILFSL bit(D13) of SD Buffer Control & Error Status Register(Offset:11E-11Fh) is set to "1".
+De-asserting Method
(1) "0" is written into the ILFSL bit(D13) of SD Buffer Control & Error Status Register(0ffset:11E-11Fh).
(2) " 1" is written into the IFSMSK bit(D29) of SD Interrupt Mask Register(Offset:120-123h).
(3) Hardware reset by #PCLR = "O''.
(4) Software reset by writing "0" into the SRST bit(DO) of SD Software Reset Register(Offset:1E0h).
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PAGE N036
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.5.19 SDIO Card interrupt
+ Interrupt Assert Condition
When an interrupt from SDIO Card by using SDCDl signal is detected, an interrupt is generated. Please release
the interrupt mask by the CIMSKO bit(D8) of Card Interrupt Control Register(Offset:136h), so the interrupt from
#HINT would be generated.
SDCLK-l _ l-] m f-n,
SDCDl I
+ Factor Evaluation Method
The CINTO bit(D12) of Card Interrupt Control Register(0ffset:136h) is set to "1".
+De-asserting Method
(1) "0" is written into the CINTO bit(D12) of Card Interrupt Control Register(0ffset:136h).
(2) " l" is written into the CIMSKO bit(D8) of Card Interrupt Control Register(Offset:136h).
(3) Hardware reset by #PCLR = "O''.
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TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.6 Card Slot Power Supply Control
TC6387XB is designed to provide connection with MIC2563(Power Supply Control LSI).The following
suggests applicable circuits:
System
Supply 3.3V
ENO SDVCC
TC6387XB 8: ENI (3.3v)
SDPWR tr VC3EN —> SD Card Slot
f'- ENO
MIC2563
4.6.1 SD Card Slot Power Supply Controller
Power supply for SD Card is controlled by configuring Power Control Register 2(Config Offset 49h) after detecting
SD Card insertion. When #SUSPEND is asserted to low, power supply for SD Card can be automatically shut out
by configuring Power Control Register 3(Config Offset 4Ah).
Parallel Power Supply Control Signals
Signal Name Function/Remarks Pin
SDPWR SD Card Slot Power Supply Controller. Bl
3.3V Enable Signal
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.38
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
4.7 SDLED signal
TC6387XB has the SDLED signal for SD interface. This signal is controlled by setting SDLED Control
Register(0ffset:13Eh). Before accessing SDLED Control Register(0ffset: 13Eh), please set following registers.
*Set SDLED Enable Register l(Config Offset:FAh) to 12h.
*Set SDLED Enable Register 2(Config Offset:FEh) to 80h.
4.8 Clock supply to SD Card
The SDCLK signal is used for a provision ofSD Memory Card or SDIO Card. Please refer to the following
setting for enabling the SDCLK output.
(1) Set Stop Clock Control Register (Config Offset:40h) to th.
(2) Set D0 of SD Software Reset Register (Offset:0E0h) to 1b.
(3) Set D7-0 of SD Card Clock Control Register (Offset:024h). These bits are used for setting the frequency of
SDCLK.
80h : SDCLK=HCL10512
40h : SDCLK=HCLK/256
20h : SDCLK=HCLK/l28
10h : SDCLK=HCLK/64
08h : SDCLK=HCLK/32
04h : SDCLK=HCLK/l6
02h : SDCLK=HCLK/8
01h : SDCLK=HCLIU4
00h : SDCLK=HCLK/2
In addition, TC6387XB holds a function that SDCLK can have same frequency as HCLK. In this case, D7-0
settings of SD Card Clock Control Register (Offset:024h)becomes invalid setting.
* Set D0 ofClock Mode Register (Config Offset:42h) to lb.
* Set D15 of SD Card Clock Control Register (Offset:024h) to lb.
Please attend that the specification of SDCLK is max.25MHz at the case of SD Card and is max.20MHz at the
case of MultiMedia Card.
(4) D8 of SD Card Clock Control Register (Offset:024h) to lb.
(5) D8 ofClock & Wait Control Register (Offset:138h) to lb.
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.39
TD s Fil II IA TC6387XB Specification
Rev. 1.0 02/02/06
4.9 Suspension
TC6387XB executes buffer-off for Input Signals from Host interface and SD Card by asserting #SUSPEND.
Phase I Phase II
Phase III
Phase IV
#SUSPEND
Register Clear
(Internal)
HCLK l l l l
SUSPEND State
* Phase I: Immediately after the power is turned ON, #PCLR indicates "L" whereas #SUSPEND indicates "H". All
the circuits are cleared in this state.
* Phase II: Assertion 0f#PCLR deactivated (H). Normal state.
* Phase III: Assert #SUSPEND to activate SUSPEND state. TC6387XB executes Anti-Penetration Process for Input
Signals in this state. Also, TC6387XB does not accept Host Interface transactions in this state.
Moreover, stopping HCLK can reduce the power consumption.
* Phase IV: TC6387XB is brought back to normal state by deactivating assertion of #SUSPEND.
TOSHIBA CONFIDENTIAL
TOTAL 62
PAGE NO.40
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
It shows what state each signals are in suspend mode (#SUSPEND=Low).
NAME Pin IO State NAME Pin IO State
HD l 5 H5 IO Hi-Z #HC S A5 I Hi-Z
HD14 F4 IO Hi-Z #HOE G3 I Hi-Z
HD13 G5 IO Hi-Z #HWE G4 I Hi-Z
HD12 F5 IO Hi-Z #HBEL H4 I Hi-Z
HDl l H6 IO Hi-Z #HBEH H3 I Hi-Z
HDIO G6 IO Hi-Z HRDY F2 0 (OD) Hi-Z
HD9 H7 IO Hi-Z SDCD3 C2 IO Hi-Z
HD8 H8 IO Hi-Z SDCD2 C3 IO Hi-Z
HD7 G8 IO Hi-Z SDCDI D3 IO Hi-Z
HD6 F6 IO Hi-Z SDCDO El IO Hi-Z
HD5 F 7 IO Hi-Z SDCMD D2 IO Hi-Z
HD4 E7 IO Hi-Z SDCLK DI 0 L
HD3 F8 IO Hi-Z #SDCD E2 I -
HD2 E8 IO Hi-Z SDWP E3 I -
HDI D8 IO Hi-Z SDLED Fl C) Hi-Z
HDO E6 IO Hi-Z SDPWR B l O *
HAI 1 D7 I Hi-Z HCLK HI I -
HA10 D6 I Hi-Z CLK32 A1 I -
HA9 C 8 I Hi-Z #HINT Gl 0 (OD) Hi-Z
HA8 C7 I Hi-Z #PCLR F3 I -
HA7 B8 I Hi-Z #SUSPEND A4 I -
HA6 A8 I Hi-Z TST2 B3 I -
HA5 A7 I Hi-Z TSTl A3 I -
HA4 C6 I Hi-Z TSTO C4 I -
HA3 B6 I Hi-Z RSVO A2 I -
HA2 B5 I Hi-Z RSVI B4 I -
HAI A6 I Hi-Z RSV2 C5 I -
* This signal is not controlled by #SUSPEND signal. The state before suspend mode (#SUSPEND=high) is held.
TOSHIBA CONFIDENTIAL
TOTAL 62
PAGE No.41
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
4.10 Pull-up/down Resistance
PULL- UP/DOWN Resistance is to be installed for each interface in TC6387XB. Be aware that Resistance Values
(described "Res. Val." in the following tables) indicated in the following tables are provided only for references.
4.10.1 Host Interface
NAME Pin IO Pull-up/ Pull-up Res. Val. FUNCTION/REMARKS
Pull-down Power
HRDY F2 0 Pull-up VCC lOKQ Ready
4.10.2 SD Card Interface
NAME Pin IO Pull-up/ Pull-up Res. Val. FUNCTION/REMARKS
Pull-down Power
SDCD3 C2 Pull-up SDVCC 47Kf2
SDCD2 C3 IO Pull-up SDVCC l00Kn SD Card Slot /Data Bus
SDCDI D3 Pull-up SDVCC lOOKQ
SDCDO El Pull-up SDVCC lOOKQ
*1 . 33KQ SD Card Slot /C0mmand
SDCMD D2 IO Pull-up SDVCC *2 / l00KQ *1 : Support MultiMedia Card
. *2 : Do not support MultiMedia Card
SDCLK Dl O - - - SD Card Slot /Divided HCLK Clock
#SDCD E2 I Pull-up VCC lOKQ SD Card Slot /Detection
SDWP E3 I Pull-up VCC 10Kf2 SD Card Slot /Write Protection
4.10.3 System Interface
NAME Pin IO Pull-up/ Pull-up Res. Val. FUNCTION/REMARKS
Pull-down Power
#HINT G1 (8D) Pull-up VCC lOKQ Interruption
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE NO.42
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
4.11 Connection example of SD Card socket
It is shown that total 10 signal connections example of TC6387XB which have 9 signals of SD card interface and 1
signal of a power supply control for SD card. As for our company, using FPSOO9-3000 of theYAMAICHI Company did
a movement confirmation of the SD card. An outside pull-up/down resistance that is mentioned on an item of the "4. 10
Pull-up/down resistance" is not shown in a bottom figure. When you design a circuit, please refer to recommended
resistance by an item of the "4.10 Pull-up/down " and a bottom figure.
TC6387XB
T vvav
MIC2563 manufactured by the
MICREL Company
Vdd FPSOO9-3000 manufactured
CLK by the YAMAICHI Company
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.43
TDSIHIIIIA
5 ElectricalCharacteristic
5.1 Absolute Maximum Standard
Absolute Maximum Ratings
TC6387XB Specification
Rev. 1.0 02/02/06
Symbol Parameter Min Max Unit Condition Note
Vcc Supply Voltage Range -0.3 5.0 V GND=0V 1
Vin3 Input Voltage (3.3V) -0.3 Vcc+0.3 V GND=0V
Vout Output Voltage -0.3 Vcc+0.3 V GND=0V
Tstg Storage Temperature Range -40 125 degree C
Note l: Vcc Power Supply
Note: Absolute Maximum Ratings indicates that stress greater than the values described above might cause permanent
damages to the devices and does not guarantee all the performances within Absolute Maximum Ratings
5 .2 DC Characteristic
5.2.1 Recommended Conditions for proper performances
Symbol Parameter Min Typ Max Unit Note
Vcc Supply Voltage for Core Logic 3.0 3.3 3.6 V
Topr Ambient Temperature under bias 0 25 70 degree
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.44
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
5.2.2 Host Interface DC Characteristic
Host Interface DC Characteristic(Vcc =3.0-3.6V, Ta=0-70degree C)
Symbol Parameter Min Max Unit Condition Note
Vih Input High Voltage 0.8Vcc - V l-l
Vil Input Low Voltage - 0.2Vcc V 1-1
Iilk Input Leakage Current -10 10 uA 0Voh Output High Voltage 2.4 - V Iout=-4mA 1-2
Vol Output Low Voltage - 0.4 V Iout=4mA 1-2
Notel-l: Applied for HD[15-0] ,HA[11-1], #HCS, #HOE, #HWE, #HBEL, #HBEH pins
N0te1-2: Applied for HD[15-0], HRDY pins
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE N045
TDSIHIIIIA
5 .2.3 SD Card Interface Pin DC Characteristic
SD Card Interface DC Characteristic: 3.3V Operation
(Vcc =3.0-3.6V, Ta=0-70degree C)
TC6387XB Specification
Rev. 1.0 02/02/06
Symbol Parameter Min Max Unit Condition Note
Vih Input High Voltage 0.7Vcc Vcc+0.3 V 2-1
Vil Input Low Voltage Vss-0.3 0.175Vcc V 2-1
Vih Input High Voltage 0.8Vcc - V 2-2
Vil Input Low Voltage - 0.2Vcc V 2-2
Vohl Output High Voltage l 0.75Vcc - V Iout=-1mA 2-3
3.0VVoll Output Low Voltage l - 0.125Vcc V Iout=1mA 2-3
3.0VVoh2 Output High Voltage 2 2.4 - V Iout=-4mA 2-4
Vol2 Output Low Voltage 2 - 0.4 V Iout=4mA 2-4
Iilk Input Leakage Current -10 10 uA 0Rdat3 Pull-up resistance inside 10 90 Kn
card (pinl)
Note2-l Applied for SDCD[3:0], SDCMD, SDWP pins
Note2-2 Applied for #SDCD pin
Note2-3 Applied for SDCD[3:0], SDCMD, SDCLK pins
Note2-4 Applied for SDLED pin
5.2.4 SD Card Power Supply Control DC Characteristic
SD Card Power Supply Control DC Characteristic: 3.3V Operation
(Vcc =3.0-3.6V, Ta=0-70degree C)
Symbol Parameter Min Max Unit Condition Note
Voh Output High Voltage 2.4 - V Iout=-100uA 2-5
3.0VVol Output Low Voltage - 0.6 V Iout=100uA 2-5
3.0VNote2-5 Applied for SDPWR pin
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.46
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
5.2.5 System Interface Pin DC Characteristic
System Interface Pin DC Characteristic
(VCC =3.0-3.6V, Ta=0-70degree C)
Symbol Parameter Min Max Unit Test Condition Note
Vih Input High Voltage 0.8Vcc - V 3-1
Vil Input Low Voltage - 0.2Vcc V 3-1
Iilk Input Leakage Current -10 10 uA 0Voh Output High Voltage 2.4 - V Iout=-4mA 3-2
Vol Output Low Voltage - 0.4 V Iout=4mA 3-2
Note3-1 Applied for HCLK, CLK32, #PCLR, #SUSPEND pins
Note3-2 Applied for #HINT pin
5.2.6 TEST Pin DC Characteristic
TEST Pin DC Characteristic
(Vcc =3.0-3.6V, Ta=0-70degree C)
S bol Parameter . Condition
Vih In ut Hi Volta e
Vil In ut Low Volta e
Iilk In ut Leaka e Current 0Note4-1 Applied for TST[2:0] pins
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE NO.47
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
5.2.7 Power Consumption Characteristic
Power Suppl Current
Symbol Parameter Min Typ Max Unit Condition
Iccstd 1 Power Supply Current, uA HCLK=0,
Standby CLK32=0
VCC=3.6V
I-, J = -s, #SUSPEND=low
Iccstd 2 Power Supply Curren CCI) "'') uA HCLK=0,
Standby CLK32=32KHz
'33) _J VCC=3.6V
Cl El _.,...-. #SUSPEND=low
IccSD/M Power Supply Current, mA HCLK=33MHZ,
MC Operating SD Card or CLK32=32KHz
MultiMedia Card VCC=3.6V
TOSHIBA CONFIDENTIAL
TOTAL 62
PAGE No.48
TDSIHIIIIA
5.3 AC Characteristic
5.3.1 Host Interface Signal AC Characteristic
(1)System Clock AC Characteristic
Vcc=3.0-3.6V, Ta=0-70degree C)
TC6387XB Specification
Rev. 1.0 02/02/06
Symbol Parameter l Min I Max l Unit I Notes
Tcyc CLK cycle time 30 oo ns
Thigh CLK High time 10 - ns
Tlow CLK Low time 10 - ns
tld HCLK Rising Time - 5 ns
tle HCLK Falling Time - 5 ns
HCLK Timing
= Tcvc =
A Tlow Thigh _
r - __-___-_ - - ........ - ................... 0.8VCC
HCLK - ____________ - - - ___-_-__-_.
0.2VCC
- i-tle _ "-t1d
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.49
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
(2)#PCLR Reset AC Characteristic
(Vcc=3.0-3.6V, Ta=0-70degree C)
S bol Parameter
Trst Reset active time after wer stable
Trst-clk Reset active time after CLK stable
#PCLR Reset Timing
POWER / ii,
b.8Vcc T 0.8Vcc
E: rst =
#PCLR ::'
9.2Vcc TTrst-clk
i 0.8Vcc
HCLK I
0.2Vcc
#PCLR Reset Timing
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.50
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
(3)Standard Memory Interface Signal AC Characteristic
(Vcc=3.0-3.6V,Ta=0-70degree C)
Symbol Parameter Min Max Unit Notes
thosl Address setup to #HCS O - ns
thos2 #HCS, #HBEL, #HBEH setup to #HOE or 20 - ns
thos3 Address setup to #HOE or #HWE low 20 - ns
th0s4 Address setup to #HOE or #HWE low 20 - ns
tpd0 Data delay time after #HWE low - lHCLK ns
thohl Data hold after #HWE high 5 - ns
thoh2 #HCS, #HBEL, #HBEH hold asserted 10 - ns
after #HOE or #HWE de-asserted
thoh3 Address Hold after #HOE or #HWE 5 - ns
de-asserted
twhl #HOE high time 3HCLK - ns
twh2 #HWE high time 3HCLK - ns
twll #HOE low time 3HCLK - ns *1
tw12 #HWE low time 3HCLK - ns *1
tosl Data Setup for HRDY Release lHCLK - ns
tpdhl #HOE,HD[15:0] hold time 5 - ns
tl #HOE low to HRDY low time 15 - ns
t2 #HWE low to HRDY low time 15 - ns
twl HRDY low time lHCLK - ns
tw2 HRDY low time lHCLK - ns
*1 There are two ways to have wait modes.
A. External wait mode method(ie. not to use CPU generated wait time):
Please input #HOE/#HWE signal using pulse width of 3HCLK minimum. If this has been applied, HRDY of
TC6380AF signal will be activated and read/write cycle will be extended to access registers. By this method,
read/write access cycle will become 16HCLK maximum.
B. Internal wait mode method(ie. use CPU generated wait time):
Please input #HOE/#HWE signal using enough pulse width, which should be 16HCLK minimum. If this has
been applied, HRDY signal is not necessary for TC6380AF register read/write operations.
TOSHIBA CONFIDENTIAL
TOTAL 62
PAGE NO.51
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
HA[11:1]
#HBEL, #HBEH
HD[15:0]
HA[11:1]
#HBEL, #HBEH
HDHSIO]
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE N052
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
5.3.2 SD Card Interface Signal AC Characteristic
(Vcc=3.0-3.6V, Ta=0-70degree C)
SDCLK (output)
OUTPUT
0.125Vcc
Todly (max)
Vol--0.125Vcc,
Vil=0.25Vcc,
Timing for SD Card Interface Signals
Vih=0.625Vcc
V0h=0.75Vcc
odly (
Symbol Parameter Min I Max l Unit I Notes
SDCD[3:0], SDCMD, SDCLK
Fpp Clock frequency Data Transfer Mode 0 25 MHz Cl=25pF
Fod Clock frequency Identification Mode 0 256 KHz Cl=25pF
Twl Clock Low time 10 - ns Cl=25pF
Twh Clock High time 10 - ns Cl=25pF
Ttlh Clock fall time - 10 ns Cl=25pF
Tthl Clock rise time - 10 ns Cl=25pF
Tisu Input set-up time 10 - ns Cl=25pF
Tih Input hold time 10 - ns Cl=25pF
Todly Output delay time - 15 ns Cl=25pF
SD Card Interface Signals Timing
0.75Vcc Fpp, Fod
TOSHIBA CONFIDENTIAL
TOTAL 62
PAGE No.53
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
5.3.3 System Interface Signal AC Characteristic
(Vcc=3.0-3.6V, Ta= 0-70degree C)
CLK32 AC Characteristic
(Vcc:3.0-3.6V, Ta=0-70degree C)
Symbol Parameter l Min I Max l Unit I Notes
Tcyc32 CLK cycle time 31 oo us
Thigh32 CLK High time ll - us
Tlow32 CLK Low time ll - us
t1d32 CLK32 Rising Time 10 - ns
tle32 CLK32 Falling Time 10 - ns
CLK32 Timing
= Tcvc32 =
a Tlow32 aThigh32 =
__-_, - __-_-_ - - - - ................... 0.8VCC
CLK32 _-__-___-_ - ________ - ___-_-___
0.2VCC
-Fi-->i-
tle32 t1d32
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE NO.54
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
6 Caution in coding device driver
6.1 Regarding a SD card insertion and removal
If a SD card would be inserted or removed, you should perform software reset with SD Software Reset
Register(Offset:0E0h, IE0h).
*In SD card insertion
If a SD card would be inserted, you should perform software reset with SD Software Reset Register(Offset:0E0h,
1E0h). Then, you should release software reset and initialize a SD card.
*In SD card removal
If a SD card would be removed, you should perform software reset with SD Software Reset
Register(0ffset:OEOh, 1E0h). Afterward, when a SD card would be inserted, you should release software reset
and initialize a SD card.
6.2 Regarding controlling Stop Clock Control Register
Stop Clock Control Register(Config Offset:40h) is used to control internal clocks of TC6387XB. When you
would set this register, you could not set different values between EMCK3 bit(D2) and EMCKl bit(DO).
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE N055
TD s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
7 Package outline
H (l)-l)cc)i)ly--C,
G OOOOOOOS- f
r oooooooo
E C)C)C)OC)OC)C)
n C)OOC)C)OC)O---i
c oooooooo
B 00000000
A oooooo o---)
0’48 mosmlm
1.8M0x
[0].]20A CCC] 0.60
u \) k) k) k) K} \)
Al pin
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE NO.56
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
Appendix
A TC6387XB function confirmation with standard memory interface
TOSHIBA connected TC6387XB board to MNIA7T0200 board manufactured the COMPUTEX corporation. Then ,
TOSHIBA confirmed to the function of SD memory Card and MMC. The following indicates these circuits.
Standard memory interface connection
MNIA7T0200 board TC6387XB board
SD memory Card
(ARM7) TC6387XB
A.1 Sample soft for standard memory interface of TC6387XB
TOSHIBA developed the device driver of SD memory Card with above environment. TOSHIBA provide these driver
source to you as sample soft of TC6387XB.
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE NO.57
TDSIHIIIIA
A.2 Wait mode specification
TC6387XB Specification
Rev. 1.0 02/02/06
MNIA7T0200 board and TC6380A board support internal and external wait mode of 32/16/8 bit access. The
correspondence list indicates as followings.
MN1A7T0200 TC6387XB TC6387XB Notes
board specification board
32bit internal wait mode Support Not support Not support *1
16bit internal wait mode Support Support Support
8bit internal wait mode Support Support Support
32bit external wait mode Support Not support Not support *1
16bit external wait mode Not support Support Support *2
8bit external wait mode Not support Support Support *2
*1 Because TC6387XB supports 16 bit bus interface, TOSHIBA do not confirm this function.
*2 MNIA7T0200 board supports only external wait mode of 32 bit access. When TOSHIBA confirmed to the
function of SD memory Card, SDIO Card and SmartMediaTM with external wait mode of 16bit and 8bit access,
TOSHIBA deal with these mode by controlling #HCS, #HWE, #HRE, #HBEH, #HBEL, HA[11:1], HD[15:0] and
HRDY with using FPGA LSI mounted to TC6387XB board. External wait access of 16 bit and 8 bit were realized by
shifting address bits against external wait access of 32 bit from MNIA7T0200 board. These access(*3) can be switched
by FPGA register.
*3 Internal wait access of 16 bit, external wait access of 16 bit and external wait access of 8 bit.
TOSHIBA CONFIDENTIAL
TOTAL 62
PAGE No.58
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
A.3 The wiring image of 16bit internal wait mode
In 16 bit internal wait mode, the connection of MNIA7T0200 board and TC6387XB is as following.
MNIA7T0200 board TC6387XB board
FNCS[3]
FA[23]
FA[22] #HCS
FA[21]
FA[20]
FNWE[1] #HWE
FNWE[0]
FNRE #HOE
FA[0] #HBEH
331:3 HAll
(IT, ] HAIO
[8] HA9
:22] HA8
(t) 1 HA7
PAM HA6
Ill) HA5
(cf/f, HA4
l] HA3
FM ] HA2
FA[1] HAI
£312] HDI5
(elf, HD14
FD[12] HD13
FD[II] HD12
FD[10] HDII
(e/ ] HDIO
(ef) HD9
l)) HD8
IT,", Hm
FD[5] HD6
1)Y, HD5
(ef, HD4
(e) HD3
l)) HD2
1:1)[0] HDl
[ 1 HDO
FNIRQIO] #HINT
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.59
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
A.4 The wiring image of 16bit external wait mode
In 16 bit external wait mode, the connection of MNIA7T0200 board and TC6387XB is as following.
MNIA7T0200 board access to TC6387XB board with 32 bit.
MNIA7T0200 board TC6387XB board
FNCS[3] -
FA[23] -
FA[22] - Dsc tr#HCS
FA[21] -
FA[20] -
FNWE[1] =e:rD-- I '-t:ro--tr #HWE
FNWE[0] '
FNRE tH2>o Cy-c-e #HOE
FA[1] - a D: C, l Y-csc tr #HBEH
tr#HBEL
FA[12] tr HAll
FA[11] tr HAIO
FA[10] tr HA9
FA[9] tr HA8
FA[8] tr HA7
FA[7] tr HA6
PAW F HA5
FA[5] tr HA4
FA[4] tr HA3
FA[3] tr HA2
FA[2] HA1
FD[15] = tr HD15
FD[14] = tr HD14
FD[13] Mt tr HD13
FD[10] Mt tr H1310
FD[9] = tr HD9
FD[8] = = HD8
FD[7] = tr Hm
FD[6] = tr HD6
FD[5] = tr HD5
FD[4] Mt tr HIM
FD[3] Mt tr Hm
FD[2] = tr Hm
FD[1] = > HDl
FDIO] = tr HDO
COUNTERWW
FNACK "'r + M-- HRDY
CPUCLK CPUCLK
(20MHz) ----F lpulse
f 3.3V
FNMI M- 33MHz
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.60
TDSIHIIIIA
TC6387XB Specification
Rev. 1.0 02/02/06
B Reference diagram
Ti E' 4 I
In F >.
= = 8 8 E hl [tIsl CI
ld Cl < I I I I I II
o I I " 4t 4t " ' I
HCLK li'. HOST IIF (33pin)
CLK32 'd?..
#HINT =
#PCLR E
#SUSPEND F- " A
- , ' E
tn o Q.
TST2 E TC6387XB
TST1 r- E" .2
TSTO a a 3 E"
r- tO O .-
- " n.
RSV2 E
RSV1 A SD Card Power
m 1: .
v, .- . .
RSVO ll! 3- SD Card " (9pin) Control Pin(1pin)
tD N N- O Cl ld CI CI
3.3V SDVCC ii'iiiittii',ci.ci,1i/ii/i,/i] ,
U) m (n w p, w 2 w (n 8
g, g iii 8 8 bl' if Please check
'" ,- ,- '" '" '" the chapter 4.6
application circuit.
':Change the resistance co m '" o g x g RD w w w
r- - _ I-
ualuetobe33kf1 [ily,'::::--,:'';)-',:?,",-.',''!,;,?,?::'',:'',',''))'-)',''
in case one uses MMC. fl 9)
SD Card Socket
YAMAICHI-denki
FPS009-3000
TOSHIBA CONFIDENTIAL
TOTAL 62 PAGE No.61
TU s Fil II IA TC6387XB Specification Rev. 1.0 02/02/06
c TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations
in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in
the most recent products specifications.
Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
q The information contained herein is presented only as a guide for the applications of our products, No responsibility is
assumed by TOSHIBA for any infringements of patents or other rights ofthe third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.
q The information contained herein is subject to change without notice.
TOSHIBA CONFIDENTIAL
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