TC59S6416BFT-80 ,MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHICTOSHIBA TC5956416/08/04BFT/BFTL-80,-1O1,048,576-WORDSX4BANKSX16-BITS SYNCHRONOUS DYNAMIC RAM2,097,1 ..
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TC59S6404BFT-80-TC59S6408BFT-10-TC59S6408BFT-80-TC59S6416BFT-80
MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
1,048,576-WORDSx4BANKSx16-BITS SYNCHRONOUS DYNAMIC RAM
2,097,152-WORDSX4BANKSx8-BITS SYNCHRONOUS DYNAMIC RAM
1194,304-WORDSx4BANKSx4-BITS SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
TC59S6416BFT/BFTL is a CMOS synchronous dynamic random access memory organized as
1,048,576-wordsX4 banksX 16 bits and TC5986408BFT/BFTL is organized as 2,097,152 wordsX4
banksXBbits and the TC59S6404BFT/BFTL is organized as 4,194,304 wordsX4banksX4 bits. Fully
synchronous operations are referenced to the positive edges of clock input and can transfer data up to
125M words per second. These devices are controlled by commands setting. Each bank are kept active
so that DRAM core sense amplifiers can be used as a cache. The refresh functions, either Auto
Refresh or Self Refresh are easy to use. By having a programmable Mode Register, the system can
choose the most suitable modes which will maximize its performance. These devices are ideal for main
memory in applications such as work-stations.
FEATU RES
TC5956416/6408/6404
- 80 - 10
to: Clock Cycle Time (Min.) 8ns 10ns
tRAs Active to Precharge Command Period(Min.) 48ns 60ns
tAc Access Time from CLK (Max.) 6ns 7ns
tRc Ref/Active to Ref/Active Command Period (Min.) 68ns 84ns
Iccl Operation Current (Max.) (Single bank) 90mA 70mA
Icco Burst Operation Current (Max.) 140mA 110mA
lcce Self- Refresh Current (Max.) 1mA 1mA
0 Single power supply of 3.3Vi0.3V
0 Up to 125MHz clock frequency
0 Synchronous operations : All signals referenced to the positive edges of clock
0 Architecture : Pipeline
0 Organization
TC59S6416BPT/BFTL : 1,048,576 wordsX4 banksX16bits
TC59S6408BFT/BFTL : 2,097,152 wordsX4 banksX8bits
TC59S6404BFT/BFTL : 4,194,304 wordsX4 banksX4bits
0 Programmable Mode register
0 Auto Refresh and Self Refresh
o Burst Length : 1, 2, 4, 8, Full page
0 KS Latency : 2, 3
0 Single Write Mode
0 Burst Stop Function
0 Byte Data Controlled by L- DQM, U- DQM (TC59S6416)
0 4K Refresh cycles / 64ms
0 Interface : LVTTL
. Package
TC59S6416BPT/BPTL : TSOP ll 54 - P - 400 - 0.80B
TC59S6408BFT/BFTL .' TSOP ll 54 - P - 400 - 0.80B
TC5986404BFT/BFTL : TSOP ll 54 - P - 400 - 0.80B
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-01-12 1/51
TOSHIBA TC59$6416/08/04BFT/BFTL-80,-10
PIN NAMES PIN ASSIGNMENT (TOP VIEW)
A0--AI 1 Address TC59S6416BFT/BFTL
BSO, BSI Bank Select TC59S6408BFT/BFTL
DQO~DQ3 I-TC5956404BFT/BFTL "
(TC59S6404) Vcc Vcc Vcc 1 54 a Vss Vss I/ss
DQ(V-DQ7 Data In ut/Out ut Boo Boo NC 2 NC DQ7 D015
(TC59S6408) p p VccQ VccQ VccQ 3 Cl V550 V550 V550
DQ1 NC NC 4 Cl NC NC DQ14
DQO~DQ15 DQ2 DQ1 D00 5 Cl DQ3 DQ6 DQ13
(TC59S6416) VssQ V550 V550 6 Cl VccQ VccQ VccQ
3 Chi Select DQ3 NC NC 7 Cl NC NC DQ12
- p DQ4 DQ2 NC 8 Cl NC DQ5 DQ11
RAS Row Address Strobe VccQ VccQ VccQ 9 Cl V550 V550 V550
W Column Address Strobe 005 NC NC Cl NC NC DQ10
- . DQ6 DQ3 DQ1 Cl DQ2 DQ4 D09
WE Write Enable V550 V550 V550 Cl VccQ VccQ VccQ
DQM DQ7 NC NC a NC NC 008
Vcc Vcc Vcc Vss Vss Vss
(TC59S6408/ . . LDQM NC NC Cl NC NC NC
6404) Output disable/Write Mask m m m Cl DQM DQM UDQM
UDQM/LDQM E E E II CLK CLK CLK
(TC59S6416) RCS RA; “Ag Cl CKE CKE CKE
. cs cs cs Cl NC NC NC
CLK Clock Inputs BSO BSO BSO Cl A11 A11 All
CKE Clock enable BS1 BS1 BS1 Cl A9 A9 A9
A10/AP A10/AP A10/AP Cl A8 A8 A8
Vcc Power (+33” A0 A0 A0 Cl A7 A7 A7
Vss Ground A1 A1 A1 a A6 A6 A6
A2 A2 A2 A5 A5 A5
VccQ P?wer ”:3: A3 A3 A3 Cl A4 A4 A4
( or I/O u er) Vcc Vcc Vcc Cl Vss I/ss Vss
VssQ Ground
(for I/O buffer)
NC No Connection
1998-01-12 2/51
TOSHIBA
TC59$6416/08/04B FT/BFTL-80,-1O
BLOCK DIAGRAM
ROW DECODER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
RON DECODER
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
CLK - CLOCK
BUFFER
6 CONTROL ,
W COMMAND--)) SIGNAL
- GENERATOR
CAS DECODER
REGISTER
ADDRESS
J BUFFER
REFRESH COLUMN
COUNTER COUNTER
NOTE :
DATA CONTROL
CIRCUIT
< >°° (r)
BUFFER
COLUMN DECODER
RON DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
RON DECODER
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
The TC59$6404BFT/BFTL configuration is 4096x1024x4 of cell array with the DO pins numbered DQO-3.
The TC59$6408BFTIBFTL configuration is 4096x512x8 of cell array with the DO pins numbered DQO-7.
The TC59S6416BFT/BFTL configuration is 4096x256x16 of cell array with the DO pins numbered DQO-15.
1998-01-12 3/51
TOSHIBA
ABSOLUTE MAXIMUM RATINGS
TC5956416/08/04B FT/BFTL-80,-1O
SYMBOL ITEM RATING UNITS NOTES
VIN. VOUT Input ' Output Voltage - 0.3--Vcc + 0.3 V 1
Vcc, VCCQ Power Supply Voltage -0.3~4.6 V 1
TopR Operating Temperature 0-70 ''C 1
TSTG Storage Temperature - 55~150 T 1
TSOLDER Soldering Temperature(10s) 260 °C 1
PD Power Dissipation 1 W 1
IOUT Short Circuit Output Current 50 mA 1
RECOMMENDED DC OPERATING CONDITIONS (Ta = Oto 70°C)
SYMBOL PARAMETER MIN TYP MAX UNITS NOTES
Vcc Power Supply Voltage 3.0 3.3 3.6 V 2
VccQ Power Supply Voltage (for I/O Buffer) 3.0 3.3 3.6 V 2
" Input High Voltage 2.0 - Vcc + 0.3 V 2
" Input Low Voltage -0.3 - 0.8 V 2
Note: 1/Amax) =Vcc/VccQ+ 1.2V for pulse width s 5ns
1hdmin)=Vss/VssQ-1.2V for pulse width s 5ns
CAPACITANCE (Vcc = 3.3V ' f=1MHZ ' Ta = 25°C)
SYMBOL PARAMETER MIN MAX UNIT
Input Capacitance (A0 to A1 l, BSO,BS1, tTS,Ris, CAS, m, DQM, CKE) - 4
I Input Capacitance (CLK) - 4
Co Input/Output capacitance - 6.5
NOTE: These parameters are periodicaly sampled and not 100% tested.
1998-01-12 4/51
TOSHIBA
RECOMMENDED DC OPERATING CONDITIONS
TC5956416/08/04B FT/BFTL-80,-1O
(Vcc = 3.3V i 0.3V, Ta = 0~70°C)
MIN. MAX.
MIN. MAX.
SYMBOL UNITS NOTES
OPERATING CURRENT
th= min ' tRc= min
Active Precharge command cycling
without Burst operation
1 bank operation
STANDBY CU RRENT
. - CKE=VIH
tck=min , CS=VIH
VIH /L = " (min)/1hL(max)
Bank: inactive state CKE=V'L (Power Down mode)
lcczp 1 1
STANDBY CU RRENT
- CKE = "
CLK = " I cs = "
VIH/L = VIH(min)/VIL(maX)
Bank : inactive state CKE=VIL (Power Down mode)
lcczps 1 1 mA
NO OPERATING CU RRENT
. CKE--Ve
tck=min
CS =V|H (min)
Bank : active state (4 banks) CKE=VIL (Power Down mode)
BURST OPERATING CURRENT
tCK = min
Read/Write command cycling
|CC4 140 110 3,4
AUTO REFRESH CURRENT
tCK= min ' tRc= min
Auto Refresh command cycling
140 110
SELF REFRESH CU RRENT
Self Refresh mode Standard roducts( )
CKE = 0.2V .
Low Power Version (BFTL)
450 450
SYMBOL MAX. UNITS NOTES
INPUT LEAKAGE CURRENT
(OVEVINévcc. all other pins not under test=0V)
OUTPUT LEAKAGE CURRENT
(Output disable, OI/S VourS VCCQ)
LVTTL OUTPUT "H" LEVEL VOLTAGE
( IOUT = - 2mA)
vOH 2.4
LVTTL OUTPUT "L" LEVEL VOLTAGE
( IOUT = 2mA)
VOL 0.4
1998-01-12 5/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
AC CHARACTERISTICS AND OPERATING CONDITIONS
(VCC = 3.3V i 0.3V, Ta = 0 to 70°C) (Notes : 5, 6, 7)
SYMBOL PARAMETER MIN._80MAX. MIN. - "I, UNITS NOTES
tRc Ref/Active to Ref/Active Command Period 68 84 9
tRAg Active to Precharge Command Period 48 100000 60 100000 ns 9
tRCD Active to Read/Write Command Delay Time 20 24 9
tCCD Read/Write(a) to Read/Write(b) Command Period 1 1 Cycle 9
tRp Precharge to Active Command Period 20 24 9
tRRD Active(a)toActive(b) Command Period 20 20 9
tWR Write Recovery Time CL* = 2 10 12
CL* = 3 8 It)
tCK CLK Cycle Time CL* = 2 10 1000 12 1000
CL* = 3 8 1000 10 1000
tCH CLK High Level Width 3 3 10
tCL CLK Low Level Width 3 3 10
tac Access Time from CLK CL* = 2 6 8
CL* = 3 6 7
tOH Output Data Hold Time 3 3
tHZ Output Data High Impedance Time 3 8 3 10 8
th Output Data Low Impedance Time 0 0
tss Power Down Mode Entry Time 0 8 0 10
tT Transition Time of CLK (Rise and Fall) 0.5 10 0.5 10
tDs Data - in Set- up Time 2 2.5
tDH Data-in Hold Time 1 1
tAs Address Set- up Time 2 2.5
tAH Address Hold Time 1 1
tCKS CKE set- up Time 2 2.5
tCKH CKE Hold Time 1 1
tCMS Command Set- up Time 2 2.5
tCMH Command Hold Time 1 1
tREF Refresh Time 64 64 ms
tasc Mode Register Set Cycle Time 16 20 ns 9
* CL is CAS Latency.
1998-01-12 6/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
NOTES :
Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause
permanent damage to the device.
2. All voltages are referenced to Vss.
3. These parameters depend on the cycle rate and these values are measured at a cycle rate with
the minimum values of tag and tRC. Input signals are changed one time during tag.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power- up sequence is described in Note 11.
6. AC TEST CONDITIONS
Output Reference Level 1.4V/1.4V
Output Load See diagram B below
Input Signal Levels 2.4V / 0.4V
Transition Time(Rise and Fall)of Input Signals 2ns
Input Reference Level 1.4V
3.3V 1.4V
1.2kn £500
Output Output L: 'r)z--son",
J; 50pF 8700 J; 50pF
A.C. TEST LOAD (A) A.C. TEST LOAD (B)
7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals
have a fixed slope.
8. tHz defines the time at which the outputs achieve the open circuit condition and is not
referenced to output voltage levels.
1998-01-12 7/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
9. These parameters account for the number of clock cycles and depend on the operating frequency
of the clock, as follows .'
the number of clock cycles = specified value of timing/ clock period
(count fractions as a whole number)
10. tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to
V1H(min.). tCL is the pulse width of CLK measured from the negative edge to the positive edge
referenced to V1L(max.).
11. Power-up Sequence
Power-up must be performed in the following sequence.
1) Power must be applied to Vcc and VCCQ(simultaneously) while all input signals are held
in the "NOP"state. The CLK signals must be started at the same time.
2) After power-up a pause of at least 200 pseconds is required. It is required that DQM and
CKE signals then be held"high"(Vcc 1eve1s)to ensure that the DQ output is impedance.
3) A11 banks must be precharged.
4) The Mode Register Set command must be asserted to initialize the Mode Register.
5) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal
circuitly of the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh
dummy cycles.
12. AC Latency Characteristics
CKE to clock disable (CKE Latency) 1
DQM to output in High-Z (Read DQM Latency) 2
DQM to input data delay (Write DQM Latency) 0
Write command to input data (Write Data Latency) 0
E to Commadn input (3 Latency) 0
Precharge to DO Hi-Z Lead time CL=2 2
CL = 3 3 Cycle
Precharge to Last Valid data out CL= 2 1
CL = 3 2
Burst Stop Command to DO Hi-Z Lead time CL=2 2
CL = 3 3
Burst Stop Command to Last Valid data out CL=2 1
CL = 3 2
Read with Autoprecharge Command to Active/Ref Command CL-- 2 BL+tRp
CL-- 3 BL+tRp Cycle
Write with Autoprecharge Command to Active/Ref Command CL-- 2 BL+tRp l
CL = 3 BL +tRp
1998-01-12 8/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
TIMING DIAGRAMS
Command Input Timing
tCK tCL tCH
"ly ss,CNs-f-hNs tf-trc-or-
tCMH (( tCMH_ tCMS
j " V'" At
k (m, (
W. itiiiiiiir
_ tCMH (
tas t J
fiet'r"
tgcs tCKH I tog tCKH (( ths tCKH
CKE t l l Jg
A l E E (g i j,
CLK " -
A0 toA11
1998-01-12 9/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Read Timing
l Read CAS Latency
A0toA11 tF"
tac I tac I tHz I
th t0H ' tOH l
DQ VALID VALID
f DATAOUT DATAOUT
Read Command , Burst Length I
1998-01-12 10/51
TOSHIBA
TC5956416/08/04B FT/BFTL-80,-1O
Control Timing of Input Data (TC59S6408/ 6404BFT)
(Word Mask)
CLK -/'iy'-l_/'-l_/'-l_/'-l,
tCMH tCMS tCMH tCMS
l l l l
DQM 7 K
tos tDH tos tDH tos tDH tos tDH
- 04—)
VALID VALID VALID ti VALID
DQOto D07 DATAIN -iiisr si DATAIN @BATAIN DATAIN
(Clock Mask)
ux_f-'N,_o "It-
tCKH tCKs tCKH tCKS
CKE l l / t
tos tDH tos tDH tos tDH tos tDH
--i 0 -
VALID VALID VALID ti VALID
DQOtODQ7%DATAIN ti DATAIN Af DATAIN itieTiiiix
Control Timing of Output Data (TC59S6408/ 6404BFT)
(Output Enable)
tCMH tcus tCMH tCMS
DOM / / l i
tac I tAc I tHz _ tac I tAC g
tOH I tOH I tOH I th t0H
VALID VALID l VALID
DQO to DQ7 DATAOUT DATAOUT ( OPEN DATAOUT
(Clock Mask)
CLK _/-1c; /-l_/'-l,
tCKH tCKs tCKH tCKS
CKE K K 7 7
tac I tac I tac I tac I
t0H I t0H I tOH t0H
VALID VALID
DQO to DQ7 DATAOUT VALID DATA OUT DATAOUT
TOSHIBA
TC5956416/08/04B FT/BFTL-80,-10
Control Timing of Input Data (TC5986416BFT)
(Word Mask)
ctr_/'iy"l_/'-l_/'-l_/'-l,
tCMH tCMS tCMH tCMS
LDQM 7 I
tCMH tons tCMH tCMS
UDQM 7 7 I I
tDs tDH tDs tDH tDs tDH tDs tDH
VALID VALID VALID ti VALID
DQ0to DQ7%DATAIN its'" si DATAIN @DATAIN M
tos tDH tos tDH tos tDH DS tDH
DQ8to 0015 DATAIN
(Clock Mask)
cu=/'''"'"'''"'""'"'1;
DATA IN
DATA IN
r'"''"-";
tCKH tCKS tCKH teg
l l / /
DQO to o/iirzr: IN
VALI D
DATA IN
VALID VALID
DATA IN DATA IN
DQ8 to DQ15%+DATA IN
DATA IN
VALID VALID
DATA IN DATA IN
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Control Timing of Output Data (TC5986416BFT)
(Output Enable)
CLK _/'-l_/'-l_/'-l_/i/'-l,
tCMH tCMs tCMH tCMS
LDQM 7 7 f i
tCMS tCMH tCMS
-"% tCMH st-'-- _ -
U DQM 7 7 K
tac tAc tHz tac I tac
t0H 4 t0H I t0H I 4 th I t0H I
VALID VALID K OPEN VALID
DQO to DQ7 DATAOUT ta DATAOUT tii) DATAOUT tit
tAc tAc tAc I tHz I tAc
_ t0H _ tOH I _ t0H I t0H th
VALID VALID VALID OPEN
DQ8 to D015 DATAOUT jiiia DATAOUT DATAOUT
(Clock Mask)
CLK _/-1c; "\_/-N,
tCKH tCKS tCKH tCKS
, r , r _ r 0
CKE l l l t
K f 7 7
tAc tac tac tac
t0H t0H t0H t0H
DQO to DQ7 die?, VALID DATA OUT del',
tAc tAC tAc tAc
tOH t0H t0H tOH
DQ8 to DQ15 DX¢AU3UT VALID DATA OUT Dkalgm
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Mode Resister Set Cycle
CLK /r\-/-1sc,
tCMs tCMH
c-s-Clit 1_/-
tCMS tCMH
tons tCMH
tCMS tCMH
tAs tAH
A0 to A11 Register set
BSO,1 data
next command
A0 Burst Length
A2 A1 A0 Sequential Interleave
A1 Burst Length <: 0 0 0 1 1
A2 0 0 1 2 2
0 1 0 4 4
A3 Addressing Mode 0 1 1 8 8
A4 1 0 1 Reserved
1 1 0 Reserved
A5 CAS Latency < ',- 1 1 1 Full Page
A6 A3 Addressing Mode
" 0 Se uential
A7 "0 (Test Mode) 1 Ingerleave
A8 "0" Reserved :1 A6 A5 A4 CAS Latency
A9 Write Mode 0 o 0 Reserved
0 0 1 Reserved
A10 "0" 0 1 0 2
0 1 1 3
A11 "o'' 1 0 0 Reserved
Reserved
BSO "0" A9 Single Write Mode
" " 0 Burst read and Burst write
BS1 0 1 Burst read and Single write
1998-01-12 14/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
OPERATING TIMING EXAMPLE
Figure 1. Interleaved Bank Read (Burst Length=4 , CA3 Latency=3)
(CLK = 100MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
cs'\_._/ _.:_._s-i.i:C..-/....''.:. \_._I
EtRC 2
.iteci: i . . 5 5 2 2 . 5 ted.
R/-sszr:.ii. [/2 22: At..'-..'.'-:..:.' 22222 rm; [22222121222222 /.lrt,si.ziri). ,
2=tRAs: i i 1RAsE
. . 2tR:s: 2 i . s itRpe i i s 22tRAs
m2v2/2AI/2 "ie::..,')'':..'.'.""::.'.:,.''.,... r222: \22222\§2222Y//222 Ii.' 2222\2
isscsi',),'zirai''t'ari'u.ijsi.ai',' I _,',v'a'...vai','., 2222\2222222/2/27
tRCD§§§"5§§§tRCD=2§’
. IEtRCD fi.-.:'":'.".:: : :2tRco
A1o7xRAaX/2/ 222 [/22 22Rabm 2222224722 2222 i.". [2222232222 222 222m?
“281“ 22,2 rs) 22022222 2222222 /s_.',_ac.i,.sxti':'aas.i.',scraj.:.'.'; ws.:','," 2AcAvx2/21mx2/22 _i2aci,':z m: 22x2
CKE . . . . . . . . . . . . . . . .
22A? i.' i' i' ..:' "itAc:'.. i.' i' i.' i' E‘ACE i' i' i' i.' EtAC
DO 3 i i 2 2 ...' mivo airv1tniv2 via 2 r'0ix0rbk1l0ix210i3Fi, i-Lci02auAiyLel-.'.
tRRD ’ERRD tRRD I tRRD
Bank #0 Active Read Precharge Active I Read PrechargeI Ac
Bank #1 Active Read Precharge Active Read
Bank #2
Bank #3
1998-01-12 15/51
Bank #1 Active Read A
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 2. Interleaved Bank Read (Burst Length=4, Chg Latency=3, Auto Precharge)
(CLK = 100MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
".r..'.i.i'..'-r':'..ii,.'p::..i. '.i.us:..i.-ri.'.'. \__/:\__l\__/
ite 3 , tRC
. . . 5tRC5 5 5 5 5 5 5 s.'.., . 5 5 tRc 5
'u-xi.irr.'/s.r'ari's i...rtsyi..'/.rj'...ri./'seilt,t,-cil.i'iil. 17/5 5//1;: _:isi.l'tusxs...iv'sac..'.1ai.r/..'zr'.:_ W
5’ERAs : i I-RAs
55tRAs5 5 5 5 5 5tRP5 5 5 5 5 5EtRAs5
m45\7//5//A '1:: \7//////A '1/45 vr..'.yvs..i.iai', 'ie/i.'.)'"),::...;..';';,-:''." 1//5///:: _:...vd.':?
WJEVi/Z/JE2575/17:142W:W/flzwi/XMEW/f/Izvmw
Armv/mr/mvw/m
t5 '..i"'.:
.. 5tRCD5 . . . 555tRCD55
A10 ARAax/A/ /5// W "f" tf" 1574 WWW ///5 Vai.'." "i'''-"....."'',:.'" //4 W/
onf‘gv 7x5RAax7/A Az:.:.'.''""..'..')-,).:.),...,''.' ci'," /5// :..'ir/i.iacr_',_x-zi..i.e 'ta.iryv..i." /s.._,utct:ii.vrve..i" AARde/ /'::'.laas',_i.:z-zii._..',iar-/._iexs,._
.5tAC5 5 5 5 5 5tAc5
i-e-f i i i i-e-e.'
DO 2 i i i , , av'vo am vin am mzmz-I:
I tRRD I tRRD I tRRD I tRRD
I I I I
Bank #0 Active Read AP* l Active ReTad 5 AP* i Active
Active Read
Bank #2
Bank #3
* AP is internal precharge start timing.
1998-01-12 16/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 3. Interleaved Bank Read (Burst Length=8, CM Latency=3)
(CLK-- 100MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
m1/4/4/4\ //_////4\ '/4/4//4: W4l/4/141A4V4/ 44;
i.' /4/ j', s), /4
..tRAS:. . E E . tERAS : E E E i
4 tRP i.' 4 4 4 4 4 4 44tRAS 4 E . .i' i.' i.' i.' tei'
cTs_4¥/////4x/\/////4Y////4A V44; V4/44/134V/7/Ai4lg4V/4/4/ 44/
w: 4444; si..' 4444; vi''-'')':..:. c',ivai'i' (''.rv.'ivi..:'.'' 4444; x? 4444 ws.".?
850/3WZ/WIéW/flé/Z/wéW/VI/i/xZ/A?”/7444 _...eiris?sird'r
i,' . 4thD4 4 i..' 4 i.' i..' 44tRCD 4 4 i.' i.' i.' i,' '.i.ts."', . .
A10 /XRAaX’/1.//1’//X 4fV/4//1’4/XRBbX//4/ ////A4 se/ai, 4l’/4/ 1’4/XRAcX1’4/ /41//\4:4'4 l’// 44/14’ /4/
A0238, avi.'.)')..'.'" (e; CAxX/// /4 /w..i,eoeiya/,rv;.ita/.ist_) 47/4/ 44/ ,t/:_.''scrrs..,.'.svi.'_.'acti..",i.zr2..'..r "it w...''" /4/ 14/
i.uci:.i.i.i:ii'.i.tAc"ii"iii'i'.itj'
..i-i"-%i:'.:.'i.i.i'.'.:.r'":'.i:':i...i':..i.'Af
DO 2 E E E , 2 jaio aim ai2 aka aim aks aka bo b1 _. , b44 be; be b47 i czh
I tRRD
tRRD I
Bank #0 Active Read 4 Precharge Active Read
Bank #1 Precharge Active Mad Precharge
Bank #2
Bank #3
1998-01-12 17/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 4. Interleaved Bank Read (Burst Length=8, Chg Latency=3, Auto Precharge)
(CLK-- 100MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
. i i . i i' i' i.' 5tRC5 i.' i' i' i..' i' i..' i..' i.' i..' i..' i i' i i
. . . 5 . . 5 . . 5 tRC:." : . 5 5 .
RAS%5 I/5//5/4: \///////////4x§//5//5/45Y//////4\ V4 wire..'::.:,,).:];..:,).,...-'.:.;,,-,'':..."
itRzAs i E E 5 RF 3 ".." E E E 'RAS.:
5tRAS5 i' 5 i' 5 5 5 tRp i'
cng5V/MW/fl/y/4W45/A5W/fl/4/4 i'.v's'"....i"i'ai,'...."'.'r'..li...".,'.r
"s":,.. v4 A.,lai.'.', 44/344454/344:4/44424444av4/1/444
IRcD'§§§§2'egigitRco
. :..tRCD-
A10mi.ars..iri.ra..i.i. vac'.'..-'...-"..'.'"'...:'"...'"'''..."'..'.;''"".:."':. W/flXRAcW/d ss...)"".'..-;.''..'-.'.'."..;
A0toA9, Z1155ax4/ 4Ac5xxy// j..." /5/ /4xaabX// MCBvXV/ /5/ iARACW/ //Xc52X// /5/ si.: 4/ 5/
A11 5 .
CKE i'.."."'.".".:"."'..""..'".
.itarcr,.i':.i.ii.i.iitA.i.:.iii.ita;
DQ i Z i i i , akoait1ait2ait3 aitaaitsak6 ax? 'v y 2 i 'v '45 ive EczoE
tRRD I tRRD
i. 1 1 i
Bank #0 Ac ive Read AP* Active Read
Bank #1 Active Read AP*
Bank #2
Bank #3
* AP is the internal precharge start timing.
1998-01-12 18/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 5. Interleaved Bank Write (Burst Length=8)
(CLK-- 100MHz)
8 9 1O 11 12 13 14 15 16 17 18 19 20 21 22 23
cs_\__/ \__/\__/ '_::'.)-::.:.'.'.. _.'.,'.:). V771\__/\___/"—
5tRc :
o-Cai..." 777/74: ":.:'ii_.'..'r'"it,ci:rod'.'...)a_.."i. 7/7/5//E 5E\ 7///////7/7\ 7/7771 :5\ W
tRAs: . .
. 55tRAS 5 5 5 'i,,
CASJ; ':_:'.r)..rri?ai.i. 7/////// Y7/57/7/AE 'ir:..'.'. Y////7//////l V7///X5 [W
55tRCD 5 ii., itRcoi.. . . . 5 .iterri.
"a"::, ":":jr2irc..-'.ori. 7//7///7/Y7/7//7\ 'i/r."'..".-'..":').'.'.-...':.-:.'...-.)... 'irrit'C.',r.i. l/5/7
350% V777 V//////77/7;V//77 _.:'s:'.'." _:..i.pw,:.'vl.'.'r.'.'zi_sci..a ///7x§15\//7?
A10 451154777 51/7/ 77/7 77xRBbx7/7/7x ':'..'.:te/.yv.i,," J.-.." 7/ ///xRAcx7// /'.z_,,/ia,._:i'.i.t:.".,'"
“31/59 ZXRAaX/5/ //chxx77/ 'c..." v/i..." MRabV/ //XCByX’//’/ j..." w''..." 7/7/ 7xRAcx777/XCAZX7 z/r/
DQ -:'.',-.i-a:r,i-:l:.-w'iorc.'..ec) '.:..v"//aas.'..'.'oaai:_.xsra.ixaa._.'.'x7ri:v0ttoi'. bv1va2va3 ai.." ///wawaX bV6va7X c201 c2135 c22
tRRD I 1:R5RD I
ti'i,,e
Bank #1 Active Write Precharge
Bank #2
Bank #3
Bank #0 Ac Write Precharge Active Write
1998-01-12 19/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 6. Interleaved Bank Write (Burst Length=8, Auto Precharge)
(CLK-- 100MHz)
012 3 4 5 6 7 891011121314151617181920212223
. . . . . . . . . :tRc; .
RASQ; _/vi.."'" :/1: _i.jv..'." ' ' Aa..i V// (ei.'.. V1 // 1.lts".'.-.:i." ' 111,2 [M1‘j/d. "..i_t,,tsi'rsi.i.', 1/
. . E tRAS E . . ': RP: E E . . RAS:' g
: . 2 . . . . . . . "ERAS: 2 2 2 2 2 2 2tRP
4W/1xw/1/11/W/1x ////////////I 'iioi...'/wi'staiij'a.i.."?
vtg.i.'iz//ui.'.rt'/i'_ 11gw/11§////111//1;x/1 1/?” §/
3507/72/11§V/2//2///2//2//§V2//////§V//?/2///2///2//? (ii.'irl'a.iteiri?
22tRCD2 . 2 2 2 2 i' 2:tRCD2 . 2 2 2 2 2 2 2 22tRCD
AmgXR/Aa X/1/ /..)sa::',': i'.:vd...'" 1/ j..." //XRBbX/// /A: :Y///:/ 1:7 j..." // 1/ 1//XRAbX/// ///5 \’////
A0e,A9ari_cvi) 1/ 1W» 1 1/ 1/ /i'.'.yrsi.i.evs::..' 1/ 2_.''..ur-ci..i.sy-vi.i. ':." 1/ 1/ 1.i./ /y..ir _..'_.'rx:i..iai:ic-v.i..l. ff" ws..'..'.'')';.'..'',;).'.''. 1 wi..:
DQ -i'-i'-i''-sizrarhvd? bp-ja ages! r/ra rd-mi-ia 591x bg/ZX ii-gi ' xiprr'v-ah'isthiahLn ciot CE1X C12
I tRRD I tRRD I
Bank #0 Active Write AP* Active Write
Bank #1 Active Write AP*
Bank #2
Bank #3
* AP is the internal precharge start timing.
1998-01-12 20/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 7. Page Mode Read (Burst Length=4, CM Latency=3)
(CLK = 100MHz)
0 1 2 3 4 5 6 7 8 9 1O 11 12 13 14 15 16 17 18 19 20 21 22 23
2 i i i i i 2 2tCC20 i.' 1220332 i.' 2CCD2 2 2 2 2 i i i i i
Ttiss':.-:.:''.:--:.':':.-.:':'-.::':'':)'..
24==2=sztRMa:s=z2_2222tRp2
RTs’AW/44 \=. i...",..''"'.,.":::,. W/lg "i.'.."..'." /2/4=I V4424; Y///2/4\2 V/2/ 42/42//2/42/ /2/
md2W2/[2A2IEW///4\5V/Ail//4%\ [/42//24A 2V//4; \///////////
vs-viii/r/ia''..:. :i.vi.',"r/,)a:i,''", 2V42/42 V/2/42/4I i.i)i"ri.,'yr'i..", i.'.'.vas",',esa:i, V////4////////
BSO%§W/%A§IaW//ami//IWV/I/MaV/AEV/I/I//////I/;/
22tRCD 2 2 22tRCD
A10sir-i,.,art.i-/,.';a 'ins...''";",',,-.,,'".:,'', 2F/2/A 2V//2 /Y//X ::.'.)e"ryi.,'tr,i,". W i..:.'roi',/c'..'r),,'s";"rsi.'.'r;i"
A0eeiarziia-ti') /':i.'.arii_nr-i'..i.rar,.,/ //Xc-xx7///chyX/// _'rv...i_sao...''.uryi':.i,'e //Xcazx4// 2/ /2 /2///2/ 2/ /2 /2//
CKE 2t l ", 2t 2
I I I I I I I A I I I A i I I I
. it - E i i E 5 I I : I . 5 it 5
i' -..'- Sui' 2 StA . I 5 f i 5 i 5 I A .
DQ 2 2 2 2 2 j alo all ale al? biay bin a'o a'1 a2 amo am1am2 bto btl bt2 bt?
I-tisa-e
Bank #0 Active Read 2 l Read Read l Precharge l
Bank #1 Active Read Read AP*
Bank #2
Bank #3
* AP is the internal precharge start timing.
1998-01-12 21/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 8. Page Mode Read/ Write (Burst Length=8, m Latency=3)
(CLK= - 100MHz)
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
'.iesi.'ii'.i.ii.::.:'.i:.ii.'-i.':i.i.i'.iei.
w,,i/.'_..:'/.'.:/."_.'-.'r/,..'.':.'_. W////////7MW//////AV////f/
wéwmrM/i/Mz/i/M/Mw/xi/i/xiaéw/‘H‘M
W45W245V2/f/2????kk/Aiwi/T/k/ZMA W//////
Bmirk/WWI/i/Z/kZ/k/kk/I/AiV/k/fk/k/fl M//////
E:tRCD:
A10at-i",a-Tri.rri..ril, 'si..?),,-',,-)..-),,-'.".,-''..-),,-)..':".:,, 'r",',-.'.'"',",-.'.'.'-",,'-'.'::. tir(/r'/.,jt,
A0eeas'i.sar/i'_ //chx)r/// v....''" // wi..'." // v,.'.'." // wi..'." Ai'..'.ysy-i.,ivvi.'', // wi..'." "r'.'; v:..)' // /i:./ // v,.') ////:/
CKE":..:.:.'::::..:..::"..:'".:.":)'".:":.:'...:.":".:.:":'.
Do ...' a a g a 5 (r .'1.'2.' .'4.' :a:voMzEa:vsW//:////
i=-5=':onsozozoéQz:DzDzvstwS::2:
Bank #0 Active Read Write Precharge
Bank #1
Bank #2
Bank #3
NOTE): See Figure 17,20
1998-01-12 22/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 9. Auto Precharge Read (Burst Length=4, CAS Latency=3)
(CLK = 100MHz)
9 10 12 13 14 15 16 17 18 19 20 21 22 23
_'tRc.'.i'i'.:'_.i,i'i.'.i..'.ii,''.i:'.''.:'.i.tRci.
RAS4////\41I///4/4EY///////////47//,\ ”4/444 vs'..'.':.:.'','.-.'.':;.''.'-.).-.'.''.-'.-..',,,.).'.'"
4IRA5 i , . :‘tRp4 : . . 1 4tRASE :' , tRp4 :
cs-ss/r/sr'..::. vairs.iia.'.":.; V////4///////74/4 _..jy.)./y-),''.aa'.i.i. 'i't'.ci'.t/j..//j...'ri.rs_..'s.'.rs.)
WE44/44 trio-c.",','...:.: v/ra-e,",'-.'.''.-"'.,,-,.",'-..''.'",,."'):.,', V//////d ws.._c,t/r.i'.'ri,tc...izxi.riv"
8501/1111 1434111411Aé/1143/W/11M11
11tRCD . 1 1 i.' 1 1 i.' 1 i' 111RCD
A10 /.".isrv:.:...:Tpci,i:" /Y44§ 17/4/47 /74//// i:,_aRAi.ityv,..'.'p'"/si,.ii.,i, _,r.,si.'..r/r).,) ".'..'r,_"r..".'rv".'.." /47
A03? 4xRAaX4 4/Xcwa7/ /4 4/ 4/ 4/ "i..; 4/xRAbW/ 4/Xchx4 4/ w''... "v.i..Y" 4 4/ /4 /44
'i'..:tAci..:..'i..i.i:i.i'i..i.i..itAci,
i-e-fi.::.:.:..::'.::...
Doi...'.'...''.. .i.'.aw0awlaiv2ai3'.:.i:'..:. ':..:i.bwibx1ibis2bie
Bank #0 Active Read AP* Active Read AP*
Bank #1
Bank #2
Bank #3
*AP is the internal precharge start timing.
NOTE): See Figure 15
1998-01-12 23/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 10. Auto Precharge Write (Burst Length=4)
(CLK = 100MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
.itec 2 2 3 5 5 i i i 5 i 2 tRC i
RAs777/x2/2/7/2Y/7777/77/77/77/77/Aiy/2772V/77777/77/7777/77/7x7777
5tRAs5 i i tRP : i' '.' i' 2 .itRasi." 5 5 tRP .'
@77/2V/77x2I/777/7/777/777/7/72V/777A2777/77/7/7/ ///77/4\’////7L
fi/”§V%2V/////////z//4§WA2WI/ //;/;//./////EW
350/7277?”/2/2///2//2//2//2/A?I/2/A?7/2///2//2//2/2///2//2 (da.itz.'a
sir,,i,.iii,':i:':.ii,':tsi'
-'Rf=i.i'i.i:..i''i::.i-vR,C=
A10 727xR2aW i.." V72 27 2/ 722/ 72 27 72/7xa2bY/72/7/ i.." 't 722/ 727 72/ 2/ 727 "....." 72/7xR2xcx72M
A0231“ /:..'.''rai'._ars.'..i.ao,'.'..isvvrai:._ 72/ 72/ // 727 77777XRAbx/7/7/xmxx7/7 727 s) s.'.;? 27 i.:.? Wy'.'.." j...S RAch:
:Haiiori'y1riv2llivio-i.. 5 i i 2 .."fEt0EWaii:iri2i.iaD-i.
Bank #0 Active Write AP* Active Write AP* Active
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing.
NOTE): See Figure 16
1998-01-12 24/51
TOSHIBA
TC5956416/08/04B FT/BFTL-80,-1O
Figure 11. Auto Refresh cycle
(CLK = 100MHz)
8 9 11 12 13 14 15 16 17 18 19 20 21 22 23
cs'\._l 'i....ii,-/.-.:'.'..
1tRC1 1tRc1
ééflééééééééfif
o-cr''., I/1/ /1/\1I//1/
////////////\ W//////////////x%
o-SSS/i.., W /1/,\1V//7
/s:..,'_..i/s,:.._,'.z"zi.."ro_.r.'r/i".".vv..,'si.:. V///////////////A 'is,
vs-cr:'''..,'-.'.':''-.,.'.'.-::'..'.''-..''.:
///////////1//l Y//1///1//1//1//1//1//1/////I %
BSO,1/1/ //// 41/
/////////////////////////////
A1041W //////7
fl/fl/f/flfl/fl/Y/fl/fl///////////////
A0e1A9rili"v/,..ir.il.il,,.i.
////I’/////Z’/:////////:////I’/17/////
ow/zz/z
"//.r/.)i_.t.)/.)i.'tr//.)i.'//.r//.)-/."//.'/v.''//.
All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle)
1998-01-12 25/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 12. Self Refresh Cycle
(CLK = 100MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
o-ss/ir/iii.)?)-:".):?,".'-;."-."" E Z kX/2/k/f/f/Z/k/A?V2
o-ss/i..:"."::.''":".,:'''.'..:."'?...'':..:'''.'.'....'-.;:.." :/2/ . ws:"'..-.:'.'."'.'...".'...'".'.:' "...'.r"i.ri..:r.'.ri.'.rxi(iiez.'.i.""
vi-tE/ir/a:."..''' V/MW////t/////////////////l ".::vy.r
ss0oi..vvi.v._.j'r/i.'riri..ci.//i:.r"...)i._o" ////’////////////////,XX’//2/
A10/Z/2M W///////1//////////MW
A0fifif‘9l22222/2222122222222222222
DQMfl////////7////ll//////7////7/////////
. . . . . i . . t
EtSE : 5 g . .:' -iic-i:utcssi'. . -:ii-i.utce-:s.:':
tya,-.:;.'-'::,'-.':.:'-...:'-.'.:-'-'."" ??%ng 22/2/4222
oo:::::; "::p:'p':...
I tRc I
All Banks Precharge l Self Refresh Cycle No Operation Cycle
Arbitrar C cle
Self Refresh Entry y y
1998-01-12 26/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 13. Power Down Mode
(CLK = 100MHz)
0 1 2 3 4 5 6 7 8 9 1O 11 12 13 14 15 16 17 18 19 20 21 22 23
E\_IY///1M\_l\l///1/l\_/ .i.i,.ui..pi".""
RTs {/112/1/1/4/2/121/1/11/11/1/11/1/11/11 V/2/ //1 wit
m 15/12/121212/111/?21112/1/U/42W2/A2Wi/
—///v1/v
BS 11A:////1/A§1///2 ",.'.ri.ri...."_c....._iiai,,"''".'...; //////\l/// //A//
A10 1//,XRAaX///1/////A52l////// w.',':."".'.'.,.-'..'..'.-,'':'..":'.','...'.'.'..'.-.,.''.'.-.'.'..'.? //xRAax////1xX/1/
A0;<2>2A9 [//XRAaX////1/ x2/ 1/XCAaX/// /2/ 12/ /,//// /2/ 12/ /2//// /2/ 12/ /2/ ma // "._'.raci.'.'sxtscsi..,
CKE22H Lsr';:..:.'.-.:..':".:'::..'):..'--':.:."'-"..;.'':::.",,:'.: ..
i 2232+ rss-rd. i.' i.,' i; '.. ..' i i.,' 2422+ i.' ',i:--i2css'i.
Doffi fffffaanxs
Active NOP Precharge NOP Active
Active Standby Precharge Standby
Power Down mode Power Down mode
NOTE): The Power Down mode is invoked by asserting CKE "low".
All Input/Output buffers(except the CKE buffer) are turned off in Power Down mode.
When CKE goes high, the No-operation command input must be at next CLK rising edge.
1998-01-12 27/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 14. Burst Read and Single Write (Burst Length=4, CM Latency=3)
(CLK = 100MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
'ttssh:." V2/22§\/2/// c..'.)" o'..'.','-'.''.'.'-'.';'." "i,' ve/ui. "i,' \7/23/ 2/2 2/ 2/2/22/
='isdr, W2A?/2///2/22/2/22?/2//\§ i..' _..'.'.'':'.:.''-'.....""".:.:"..'.'.-..'.:.-..':.''"....."",:'.."
-2RCD22 22:22 iii:.
"tm/a/lr. V222§\/222222//\I/2/x "ii::.'.;'".'.')..";."'-'.'.;-".'.-)"..'"-:.''.-;,..''"
BSOJ V/2/§\//2/2/2//22§V/2/22 i...' 222/22/2/22/
A1ogaaax/2/2/x 22/2 2 /2/222//x W222 'i.' ::.'.ei'rs..'r/ri.r/rzsi.; 22/
A0eearu:il:'svai, fd'" s'.,.'.?-;:"-...)--,'..'.. " w'-.'.: ws'.'.." /o_..r.l/;'..) ws"..'." mmmcmgxxcazv/ wi'.'.." /..ir 22/ wi.: "j..'.'" 2/
DOM 222/2222 'i., 'i., ':...ityjrsisiisaii.rj.'v,a..':i. ".-...i'pi'.lr'i.':.i... "..:'.:ec.'rj.'rc..t(.)
2 +5 :K-i..
DQ ",' ",' ",' ",' ",' , £1110 ail ain airs ",' aw ",' aio a'O
iiii dioiididi,i'.oi,.,i:oi..oi,:
Bank#0 2 I
Bank #1 Active Read Single Write Read
Bank #2
Bank #3
1998-01-12 28/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
PIN FUNCTIONS
CLOCK INPUT: CLK
The CLK input is used as the reference for S-DRAM operations. All operations are synchronized to
the positive edges of CLK.
CLOCK ENABLE: CKE
The CKE input is used to suspend the internal CLK. When the CKE signal is asserted"low", the
internal CLK is suspended and output data is held intact while CKE is asserted "low". When all
banks are in the idle state, the CKE input controls the entry to the Power Down and Self Refresh
modes.
BANK SELECT: BSO, BSI
The TC59S6416BFT/BFTL, TC5986408BFT/BFTL and the TC5986404BFT/BFTL are organized as four-
bank memory cell arrays. The BSO, BSI inputs are latched at the time of assertion of the operation
commands and selects the bank to be used for the operation.
BSO BS1
0 0 Bank#O
1 0 Bank#1
0 1 Bank#2
1 1 Bank#3
ADDRESS INPUTS: A0--A11
The A0 to All inputs are address to access the memory cell array, as following table.
Row Add ress Column Add ress
TC59S6416BFT/BFTL A0 to A11 A0 to A7
TC59S6408BFT/BFTL A0 to A11 A0 to A8
TC59S6404BFT/BFTL A0 to A11 A0 to A9
The row address bits are latched at the Bank Activate command and column address bits are latched
on the Read or Write command. Also, the A0 to All inputs are used to set the data in the Mode
register in a Mode Register Set cycle.
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TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
CHIP SELECT: US
The cg input controls the latching of the commands on the positive edges of CLK when US is
asserted"low". No commands are latched as long as US is held "high".
ROW ADDRESS STROBE: RAS
The E&‘s‘ input defines the operation commands in conjunction with the 237$ and 1Trrt" inputs,
and is latched at the positive edges of CLK. When R-Ag and Clif are asserted "low" and CKS is
asserted "high", either the Bank Activate command or the Precharge command is selected by the
W signal. When W is asserted"high", the Bank Activate command is selected and the bank
designated by BSO, BSI are turned on so that it is in the active state. When 1TrTif is asserted
"low", the Precharge command is selected and the bank designated by BSO, BSI are switched to
the idle state after Precharge operation.
COLUMN ADDRESS STROBE: GAS
The 'tSit?" input defines the operation commands in conjunction with the "tTitT1" and Tirrt" inputs,
and is latched at the positive edges of CLK. When ITM is held "high" and cg is asserted"low",
column access is started by asserting m "low". Then, the Read or Write command is selected by
asserting WE "low" or "high".
WRITE ENABLE: W
The TirE input defines the operation commands in conjunction with the RAS and CAS inputs,
and is latched at the positive edges of CLK. The WE input is used to select the Bank Activate or
Precharge command and Read or Write command.
DATA INPUT/ OUTPUT MASK: DQM or L- DQM and U- DQM
The DQM input enables output in a Read cycle and functions as the input data mask in a
Write cycle. When DQM is asserted "high" at the positive edges of CLK, output data is disabled
after two clock cycles during a Read cycle, and input data is masked at the same clock cycle
during a Write cycle.
In the case of the TC59S6416BFT/BFTL, the LDQM and UDQM inputs function as byte data
control. The LDQM input can control DQO- 7 in a Read or Write cycle and the UDQM can control
DQ8- 15 in a Read or Write cycle.
DATA INPUT/ OUTPUT: DQO - 15
The INO- 15 input and output data are synchronized with the positive edges of CLK. In the
case of TC59S6408BFT/BFTL and TC59S6404BFT/BFTL, these pins are DQO - 7 and DQO - 3
respectively.
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Ogeration Mode
Fully synchronous operations are performed to latch the commands at the positive edges of
CLK. Table 1 shows the truth table for the operation commands.
Table1 Truth Table (Note(1)and (2))
Command Device State CKEM CKEn DOM“) BSO,1 A10 A11,A9-0 C? W as W
Bank Activate Idle@ H x x V V L L H H
Bank Precharge Any H x x V L x L L H L
Precharge All Any H x x x H x L L H L
Write Active (3) H x x V L V L H L L
Write with Aut Precharge Active“) H x x V H V L H L L
Read Active (3) H x x V L V L H L H
Read with Auto Prechrage Active© H x x V H V L H L H
Mode Register Set Idle H x x V V V L L L L
No - Operation Any H x x x x x L H H H
Burst stop Active (4) H x x x x x L H H L
Device Deselect Any H x x x x x H x x x
Auto Refresh Idle H H x x x x L L L H
Self Refresh Entry Idle H L x x x x L L L H
Self Refresh Exit Idle L H x x x x H x x x
(Self Refresh) L H H x
Clock Suspend Mode Entry Active H L x x x x x x x x
Power Down Mode Enrty Idle/Actives) H L x x x x H X x x
L H H x
Clock Suspend Mode Exit Active L H x x x x x x x x
Power Down Mode Exit Any L H x x x x H x x x
(Power Down) L H H x
Data write/Output Enable Active H x L x x x x x x x
Data write/Output Disable Active H x H x x x x x x x
Note (1) V=Valid x =Don't Care L=Low level H= High level
(2) CKEn signal is input level when commands are issued.
CKEn_1 signal is input level one clock cycle before the commands are issued.
(3) These are state designated by the BSO, BS1 signals.
(4) Device state is Full Page Burst operation.
(5) LDQM, UDQM (TC59564168FT/BFTL)
(6) Power Down Mode can not entry in the burst cycle.
When this command assert in the burst cycle, device state is clock suspend mode.
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1. Command Function
Bank Activate command
(m = "L", m = "H", W: "H", BS=Bank, A0 to All =Row Address)
The Bank Activate command activates the bank designated by the BS (Bank Select)
signal. Row addresses are latched on A0 to All when this command is issued and the cell
data is read out of the sense amplifiers. The maximum time that each bank can be held in
the active state is specified as tRAS(max).
Bank Precharge command
(RAS = "L", CAS = "H", ITrE= "L", BS=Bank, A10: "L", A0 to A9, A11 =Don't care)
The Bank Precharge command precharges the bank designated by BS. The precharged
bank is switched from the active state to the idle state.
Precharge All command
(m = "L", Ciig = "H", 't'"'t''"r''ft'C- "L", BS=Don't care, A10: "H", A0 to A9, A11=Don't care)
The Precharge All command precharges all banks simultaneously. All banks are then
switched to the idle state.
Write command
(tTifg = "H", tTEg = "L", WE: "L", BS=Bank, A10: "L", A0 to A9=Column Address)
The Write command performs a Write operation to the bank designated by BS. The
write data is latched at the positive edges of CLK. The length of the write data (Burst
Length) and column access sequence (Addressing Mode)must be in the Mode Resister at
power- up prior to the Write operation.
The A9 input is "Don't care" on the TC5986408BFT/BFTL and the A8 and A9 inputs are
"Don't care" on the TC59S6416BFT/BFTL.
Write with Auto Precharge command
(m = "H", Chg = "L", W: "L", BS=Bank, A10: "H", A0 to A9=Column Address)
The Write with Auto Precharge command performs the Precharge operation automatically
after the Write operation. This command must not be interrupted by any other commands.
The A9 input is "Don't care" at the TC5986408BFT/BFTL and the A8 and A9 inputs are
"Don't care" on the TC59S6416BFT/BFTL.
Read command
ftTirf; = "H", C7r9" = "L", 1TrTff= "H", BS=Bank, A10: "L", A0 to A9=Column Address)
The Read command performs a Read operation to the bank designated by BS. The read
data is issued sequentially synchronized to the positive edges of CLK. The length of read
data (Burst Length), Addressing Mode and m Latency(access time fromCiScornmand in
a clock cycle) must be programmed in the Mode Register at power-up prior to the Write
operation.
The A9 input is "Don't care" on the TC5986408BFT/BFTL and the A8 and A9 inputs are
"Don't care" on the TC59S6416BFT/BFTL.
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Read with Auto Precharge command
(m = "H", Chg = "L", W: "H", BS=Bank, A10: "H", A0 to A9=Column Address)
The Read with Auto Precharge command automatically performs the Precharge operation
after the Read operation. This command must not be interrupted by any other command.
The A9 input is "Don't care" on the TC5986408BFT/BFTL and the A8 and A9 inputs are
"Don't care" on the TC59S6416BFT/BFTL.
Mode Register Set command
Ct1"7"rg = "L" , tT7rg" = "L" , Tirrif= "L" , BS , A0 to All =Register Data)
The Mode Register Set command programs the values of CN? latency, Addressing Mode and
Burst Length in the Mode Register. The default values in the Mode Register after power- up
are undefined, therefore this command must be issued during the power- up sequence. Also,
this command can be issued while all banks are in the idle state.
No - Operation command
(m = "H'' , Wig = "H'' , ITE-- "H")
The No-Operation command simply performs no operation (same command as Device Deselect).
Burst stop command
(m = "H'' , m = "H'' , W: "L")
The Burst stop command is used to stop the burst operation. This command is valid during
a Full Page Burst operation. During other types of Burst operation, the command is illegal.
Device Deselect command
(tTSI" = "H")
The Device Deselect command disables the command decoder so that the RAS, CAS, WE
and Address inputs are ignored. This command is similar to the No-Operation command.
Auto Refresh command
(RAS = "L'' , CAS = "L" , W: "H" , CKE = "H" , BS , A0 to All =Don't care)
The Auto Refresh command is used to refresh the row address provided by the internal
refresh counter. The Refresh operation must be performed 4096 times within 64ms. The next
command can be issued after tRC from the end of the Auto Refresh command. When the Auto
Refresh command is issued, A11 banks must be in the idle state. The Auto Refresh operation
is equivalent to the CM-before-IW; operation in a conventional DRAM.
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1 - 13 Self Refresh Entry command
(m = "L'' , CNif = "L'' , W: "H", CKE = "L'' , BS , A0 to All =Don't care)
The Self Refresh Entry command is used to enter Self Refresh mode. While the device is
in Self Refresh mode, all input and output buffers (except the CKE buffer) are disabled and the
Refresh operation is automatically performed. Self Refresh mode is exited by taking CKE "
high " (the Self Refresh Exit command)
1 - 14 Self Refresh Exit command
(CKE-- "H" , tTSI' = "H" or CKE-- "H" , "rt""ii"t?" = "H" , "tTit-iT-- "H")
This command is used to exit from Self Refresh mode. Any subsequent commands can
be issued after tRC from the end of this command.
1 - 15 Clock Suspend Mode Entry/Power Down Mode Entry command
(CKE = "L")
The internal CLK is suspended for one cycle when this command is issued (when CKE is
asserted "low"). The device state is held intact while the CLK is suspended. On the other
hand, when the device is not operating the Burst cycle, this command performs entry into
Power Down mode. All input and output buffers(except the CKE buffer) are turned off in
Power Down mode.
1 - 16 Clock Suspend Mode Exit/Power Down Mode Exit command
(CKE-- "H")
When the internal CLK has been suspended, operation of the internal CLK is resumed by
providing this command (asserting CKE "high"). When the device is in Power Down mode, the
device exits this mode and all disabled buffers are turned on to the active state. Any
subsequent commands can be issued after one clock cycle from the end of this command.
1 - 17 Data Write/ Output Enable , Data Mask/ Output Disable command
(DQM: "L/H" or LDQM, UDaM="L/H'')
During a Write cycle, the DQM or LDQM, UDQM signal functions as Data Mask and can
control every word of the input data. During a Read cycle, the DQM or LDQM, UDQM signal
functions as the control of output buffers.
The LDQM signal controls DQO to 7 and the UDQM signal controls DQ8to 15.
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2. Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the
Read command is issued after tRCD from the Bank Activate command, the data is read out
sequentially, synchronized to the positive edges of CLK (a Burst Read operation). The initial read
data becomes available after Wig latency from the issuing of the Read command. The (ES latency
must be set in the Mode Register at power-up. In addition, the burst length of read data and
Addressing Mode must be set. Each bank is held in the active state unless the Precharge command
is issued, so that the sence amplifiers can be used as secondary cache.
When the Read with Auto Precharge command is issued, the Prechage operation is performed
automatically after the Read cycle, then the bank is switched to the idle state. This command
cannot be interrupted by any other commands. Also, when the Burst Length is 1 and tRCD(min), the
timing from the "rt"7t'""g" command to the start of the Auto Precharge operation is shorter than
tRAs(min). In this case, tRAs(min)must be satisfied by extending tRCD (Figure 9, 15).
When the Precharge operation is performed on a bank during a Burst Read operation, the Burst
operation is terminated (Figure 20).
When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop
command or Precharge command is issued.
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3. Write Operation
Issuing the Write command after tRCD from the Bank Activate command, the input data is
latched sequentially, synchronizing with the positive edges of CLK after the Write command (Burst
Write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be
set in the Mode Register at power- up.
When the Write with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state. This command
cannot be interrupted by any other command for the entire burst data duration. Also, when the
Burst Length is 1 and tRCD(min), the timing from the Rits command to the start of the Auto
Precharge operation is shorter than tRAs(min). In this case, tRAs(min) must be satisfied by extending
tRCD (Figure 10, 16).
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated (Figure 20).
When the Burst Length is full- page, the input data is repeatedly latched until the Burst Stop
command or the Precharge command is issued.
When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of
the read burst length.
4. Precharge
There are two commands which perform the Precharge operation: Bank Precharge and Precharge
All. When the Bank Precharge command is issued to the active bank, the bank is precharged and
then switched to the idle state. The Bank Precharge command can precharge one bank
independently of the other bank and hold the unprecharged bank in the active state. The
maximum time each bank can be held in the active state is specifed as tRAs (max). Therefore, each
bank must be precharged within tRAs(max) from the Bank Activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks
are not in the active state, the Precharge All command can still be issued. In this case, the
Precharge operation is performed only for the active bank and the precharged bank is then switched
to the idle state.
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5. Page Mode
The Read or Write command can be issued on any clock cycle.
Whenever a Read operation is to be interrupted by a Write command, the output data must be
masked by DQM to avoid I/O conflict. Also, when a Write operation is to be interrupted by a Read
command, only the input data before the Read command is enable and the input data after the Read
command is disabled.
6. Burst Termination
When the Precharge command is issued for a bank in a Burst cycle, the Burst operation is
terminated. When the Burst Read cycle is interrupted by the Precharge command, read operation is
disabled after clock cycle of (tTh-ff latency-l) from the Precharge command (Figure 20). When the
Burst Write cycle is interrupted by the Precharge command, the input circuit is reset at the same
clock cycle at which the Precharge command is issued. In this case, the DQM signal must be
asserted "High" to prevent writing the invalid data to the cell array (Figure 20).
When the Burst Stop command is issued for the bank in a Full-page Burst cycle, the Burst
operation is terminated. When the Burst Stop command is issued during Full-page Burst Read cycle,
read operation is disabled after clock cycle of (m latency-l) from the Burst Stop command. When
the Burst Stop command is issued during a Full-page Burst Write cycle, write operation is disabled
at the same clock cycle at which the Burst Stop command is issued. (Figure 19)
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7. Mode Register Operation
The Mode register designates the operation mode for the Read or Write cycle. This register is
divided into three fields;A Burst Length field to set the length of burst data, an Addressing Mode
selected bits to designate the column access sequence in a Burst cycle, and a tTES" Latency field to set
the access time in clock cycle.
The Mode Register is programmed by the Mode Register Set command when all banks are in the idle
state. The data to be set in the Mode Register is transferred using the A0 to All address inputs. The
initial value of the Mode Register after power - up is undefined; therefore the Mode Register Set
command must be issued before proper operation.
0 Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 1, 2, 4, 8 words, or full-page.
A2 A1 A0 Burst Length
0 0 0 1 word
0 O 1 2 words
0 1 0 4words
O 1 1 8words
1 1 1 Full-Page
0 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the
A3 bit is "o ", Sequential mode is selected. When the A3 bit is " 1 ", Interleave mode is selected.
Both Addressing modes support burst length of 1, 2, 4 and 8 words. Additionally, Sequential mode
supports the full-page burst.
A3 Addressing mode
0 Sequential
1 Interleave
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0 Addressing sequence of Sequential mode
A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as shown in Table 2.
Table 2 Addressing sequence for Sequential mode
DATA Access Address Burst Length
Data 0 n 2 words (Address bits is A0)
Data 1 n +1 , not carried from A0 to A1
Data 2 n + 2 4words (Address bits is A1, A0)
Data 3 n + 3 not carried from A1 to A2
Data 4 n + 4
Data 5 n + 5 8 words (Address bits is A2, A1, A0)
Data 6 n + 6 not carried from A2 to A3
Data 7 n + 7
0 Addressing sequence of Interleave mode
A column access is started from the input column address and is performed by inverting the
address bits in the sequence shown in Table 3.
Table 3 Addressing sequence for Interleave mode
DATA ACCESS ADDRESS Burst Length
DataO A8 A7 A6 A5 A4 A3 A2 A1 A0
- 2words
Data1 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data2 A8 A7 A6 A5 A4 A3 A2 A1 A0 4words
Data3 A8 A7 A6 A5 A4 A3 A2 M gi-O
Data4 A8 A7 A6 A5 A4 A3 M A1 A0
Datas A8 A7 A6 A5 A4 A3 M A1 gi-O Swords
Data6 A8 A7 A6 A5 A4 A3 M M A0
Data7 A8 A7 A6 A5 A4 A3 M M gi-O
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Addressing sequence example (Burst Length=8 and input address is 13.)
DATA Interleave mode Sequential mode
A8 A7 A6 A5 A4 A3 A2 A1 A0 ADD ADD
Data 0 0 0 0 0 0 1 1 0 1 13 13 13 .
Data1 o o o o o 1 1 o o 12 13 +1 14 calculated usmg
Data 2 o o o o o 1 1 1 1 15 13 +2 15 lil, A1 and A0
Data 3 o o o o o 1 1 1 o 14 13 + 3 8 bits.
Data 4 o o o o o 1 o o 1 9 13 + 4 9 not carry from
Data 5 0 0 0 O 0 1 0 0 O 8 13 + 5 10 A2 to A3 bit.
Data 6 0 0 0 0 0 1 0 1 1 11 13 + 6 11
Data 7 0 0 0 0 0 1 O 1 0 10 13 + 7 12
Read Cycle m Latency-- 3
Command
Add ress
ti.ooxi"."vxt"i.vyti.s3xi'o4yisyiUy/o7y:.i'_-
DQO - 7
Data Interleave mode 13 12 15 14 9 8 11 10
Address Sequential mode 13 14 15 8 9 10 11 12
0 Torg Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of “C‘KS‘ Latency depends on the frequency of CLK. The minimum
value which satisfies the following formula must be set in this field.
tCAC (min) s tThS Latency M tCK
A6 A5 A4 m Latency
0 1 0 2 clock
0 1 1 3 clock
0 Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to "O " for normal operation.
0 Reserved bits (A8 , A10 , A11, BS)
These bits are reserved for future operations. They must be set to "0 " for normal operation.
0 Single Write mode (A9)
This bit is used to select the write mode. When the A9 bit is "O", Burst Read and Burst Write
mode are selected. When the A9 bit is "I", Burst Read and Single Write mode are selected.
A9 Write Mode
0 Burst Read and Burst Write
1 Burst Read and Single Write
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8. Refresh Operation
Two types of Refresh operation can be performed on the device:Auto Refresh and Self Refresh.
Auto Refresh is similar to the twif-before-Mg refresh of conventional DRAMs and is performed by
issuing the Auto Refresh command while all banks are in the idle state. By repeating the Auto
Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed
4096 times(rows) within 64ms(Figure 11). The period between the Auto Refresh command and the
next command is specified by tRC.
Self Refresh mode is entered by issuing the Self Refresh command (CKE asserted "low") while all
banks are in the idle state. The device is in Self Refresh mode for as long as CKE is held"low".
In Self Refresh mode all input/output buffers (except the CKE buffer) are disabled, resulting in lower
power dissipation(Figure 12).
9. Power Down Mode
When the device enters the Power Down mode, all input/output buffers (except CKE buffer) are
disabled resulting in lower power dissipation in the idle state. Power Down mode is entered by
asserting CKE "low"while the device is not running a Burst cycle. Taking CKE "high" exit this
mode. When CKE goes high, a No-operation command must be input at next CLK rising edge of
CLK (Figure 13).
10.CLK suspension and Input/ Output Mask
When the device is running a Burst cycle, the internal CLK is suspended by asserting CKE"low''
and is frozen from the next cycle. A Read/Write operation is held intact until the CKE signal is
taken "high".
The Output Disable/Write Mask signa1(DQM) has two functions, controlling the output data in a
Read cycle and performing word mask in a Write cycle. When the DQM is asserted "high" at the
positive edge of CLK, the output data is disabled after two clock cycles in the case of a Read
operation and the write data is masked at the same clock cycle in the case of a Write operation.
The timing relation between the CKE timing and DQM is described in Figure21(a) and 21(b).
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Figure15. Auto Precharge timing (Read cycle)
(1)ciLatency--2 p 1. 2 , 4 5. , 7 8 , 1.0 ll 1.21.3
(a)Burst Length = 1
Command (EE) AP Cr i' Act
Do i... i I-TLV
(b)Burst Length = 2 . . .
Command '::' AP i' Act
Do ':': i..' m QI
(c) Burst Length = 4
Command en: 2 2 .iii.v.." zen
(d)Burst Length = 8 . . : : .' : 'i.' i:." 'i' 'i..' 'i'
Command (RE)':.. i.' i,' i:." i,' i..' i.' (.."iy.'i.i'.)r i.'
Do-"::'"..-.':.).''-:))))))'.-':'-.';)?:'.;
(Em Latency = 3
(a)Burst Length = 1
Command
(b)Burst Length = 2
Command i' iris"-,, i' i' Act
(c) Burst Length = 4
Command
(d)Burst Length = 8 .
Command i.' i' i.' i.' i.' i' i' (AP) i." i." Act
-i''-'i-A:
oo-ii-.::.':"-..'.) i'" QOXQ1XQZXQ3XQ4XQ5XQ6XQ7>— "ii.., 'i:..
Note) 0 represents the Read with Auto Precharge command.
... ''':, represents the start of internal precharging.
. (Cir) ........ represents the Bank Activate command.
. When the Auto Precharge command is asseted, the period from the Bank Activate
command to the start of internal precharging must be at least tRA5(min).
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Figure16. Auto Precharge timing (Write cycle)
mm Latency = 2
0 1 2 3 4 5 6 7 8 9 10 11 12 13
(a)Burst Length = 1
(b)Burst Length = 2
Command i." ..s.%v":, i' Act
Command tiEiirCiir, ..i'
DQ , D0 l
DQ 0.1
(c) Burst Length = 4
(d)Burst Length = 8
(2)CAS Latency = 3
(a)Burst Length = 1
5 tum i' :TRP
-."-t._
oo-ou/xo.:')-.:'-."''-.:;,))';-)'
Command .zZHKI'Dm} .i' i' Act
(b)Burst Length = 2
Command
(c) Burst Length = 4
Command m ':..' 'i' i.,' irii/.), 'i..' Ian
5 tWR i. : tRP
DQ J D k
i tum i i." tRP
(d)Burst Length = 8
N ote)
tyrs-IFE-twifi-C/y
i tWR i 5 tRP
oo-o_o/xo/diy/ox/SX/ix/k-i,
. represents the Write with Auto Precharge command.
0 i' AP "j: represents the start of internal precharging.
0 (AEt)represents the Bank Activate command.
0 When the Auto Precharge command is asseted, the period from the Bank Activate
command to the start of internal precharging must be at least tRA5(min).
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Figure 17. Timing chart for Read-to-Write cycle
In the case of Burst Length = 4
(1 )WS Latency = 2
(a)Command i'
DQM i.' / i.' \
(b)Command
mm Latency = 3
(a)Command
DQM . . I I I I
DQ—I-ID
(b)Command 'i..' 'i.' 'i..'
Note) I The output data must be masked by DQM to avoid " conflict.
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Figure 18. Timing chart for Write-to-Read cycle
In the case of Burst Length = 4
Q 1 ? 3 4 f , , 8 9 10 11 12 13
mm Latency = 2 ' .
(a)Command i..'
(b )Command
(2)WS Latency = 3
(a)Command i.'
DQM i.." : , , :
(b)Command 'i..: '_:..: i a a 5
mm i.' i i..' i,
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Figure 19. Timing chart for Burst Stop cycle (Burst stop command)
0 1 2 3 4 5 6 7 8 9 10 11 12 13
(1 )Read cycle
(MW Latency = 2
Command (Eiti)ii. i...' _... '.:i(ssC.r):i'
oo-i-iii/you);,
(MKS Latency = 3
Command ii' i," i.".. i," BS-T
oQ-i..i-:.iid0)(dxd2)(ti3xto'4)
(2 )Write Cylcle
Command ii' i:." 'i." 'i."
oo-tdo X51 Xth X03 X54)
Note) . represents the Burst stop command.
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Figure20. Timing chart for Burst Stop cycle (Precharge command)
0 1 2 3 4 5 6 7 8 9 10 11 12
In the case of Burst Lenqth = 8 i.' ' i 5 5 5 i i 5 5 5 5 5
(1 )Read cycle 5
mm Latency = 2
Command 'i" 'i' _::..' 'i., pRCG
rr-i...''.-'-':....::-; QOXQ1XQZXQ3XQ4
(b)CiS Latency = 3
Command
o-...'.:":)''.,-:.:.'.:." 00XQ1X02X03X04,
(2)Write Cylcle
mm Latency = 2
Command 'i:., 'i::., 'i::,
i' tum
oo-l 00X D1XDZXD3XD4,
(b)Cis Latency = 3
Command 'i.' 'i.' 'i.' 'i.' PRCG
i i a 2 if-e.: i.."
DQM i.' i' i' i' 2/52\
oo-t o'ox 51xo'zxo'3x 54)
Note) 0 PRCG represents the Precharge command.
1998-01-12 47/51
TOSHIBA
TC5956416/08/04B FT/BFTL-80,-1O
Fiqure21(a). CKE/DQM Input
timinq (Write cycle)
CLK cycle No. 1 2 3 4
External I
Internal
[\ [7 f
DQ D1 D2 D3
DQM MASK
CLK cycle No. 1 4
oir,)er_ai,x
CKE MASK
External LfrN,
Internal LCN.
C::it)=i.".".
DQM MASK CKE MASK
CLK cycle No. 1
External LCN,
Internal -1TN
CKE MASK
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TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Fiqure21(b). CKE, DQM Input timinq (Read cycle)
CLK cycle No. 1 2 3 4 5 6 7
External ,
Internal _/ \
CLK cycle No. 1 2 3 4 5 6 7
External
Internal
CLK cycle No. 1 2 3 4 5 6 7
External
Internal
otoni1yoi2yio3iyo''4ys''syi,y
1998-01-12 49/51
TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
Figure 22. Self Refresh/Power Down Mode Exit Timing
0 Asynchronous Control
Input Buffer turn on time (Power Down mode exit time) is specified by
tCK5(min) + tCK(min).
A) tCK
CKE i." '1
A-i-w..
tCK5(min) + tCK(min)§
Command //:/ Ag NOP 2i'i.immandtr:) $2: X
Input Buffer Enable
B) tCK 2 tCKs(min) + tCK(min)
: tCK _:
CLK / l if l
CKE i..' /'
'.e-i.'
".." tod(min) + tadmin)..
Command // Atdmmand W"
' Input Buffer Enable
NOTE) 0 All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
. representsthe No-Operation command.
. Command represents one command.
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TOSHIBA TC5956416/08/04BFT/BFTL-80,-10
OUTLINE DRAWING (TSOPII 54 - P - 400 - 0.8OB)
Unit in mm
J'i'ssppppssparmwmismiisir/ii'-----
?HHHHWHHHH:HHHHHHHHHHHHHH§_.-
0.71TYP .x- 0.32%33M
1998-01-12 51/51
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