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TC58FVT800FT-10-TC58FVT800FT-12-TC58FVT800FT-85
8 MBIT (1M X 8 BITS / 512K X 16 BITS) CMOS FLASH MEMORY
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
8-MBIT (1M X 8 BITS / 512K x 16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVT800/B800 is a 8,388,608-bit, 3.0-V read-only electrically erasable and programmable
flash memory organized as 1,048,576 words X 8 bits or as 524,288 words X 16 bits. The
TC58FVT800/B800 features commands for Read, Program and Erase operations to allow easy
interfacing with microprocessors. The commands are based on the JEDEC standard. The Program and
Erase operations are automatically executed in the chip. The device has Chip, Block and Multi - Block
Erase ca abilitaz.
The T 58FV 800/B800 is available in either a 44-pin plastic SOP or a 48-pin TSOP package to suit
a variety of design applications.
FEATURES
0 Power Supply
VDD = 2.7V to 3.6V
0 Organization
IM X 8bits / 512K X 16 bits
0 Modes
Auto Program, Auto Chi Erase
Auto Block Erase, Auto ultiple Block Erase
Erase Suspend/Resume, Block Protection
0 Mode Control
Compatible with JEDEC standard commands
o Erase/ Program Cycles
105 Cycles typ.
0 Access Time
85 ns (VDD = 3.0 V to 3.6 V)
100 ns/ 120 ns (VDD = 2.7 V to 3.0V)
0 Power Dissipation
Data Polling/Toggle Bit 250 PA (Standby TTL level)
0 Block Erase Architecture 10 ,uA (Standby CMOS level)
1 X 16 Kbytes / 2 X 8 Kbytes / 30 mA (Read operation)
1 X 32 Kbytes / 15 M 64 Kbytes 40 mA (Program/ Erase Operations)
0 Boot Block Architecture 0 Package
TC58FVT800F/FT - Top Boot Block TC58FVT800F/B800F .' SOP44- P- 600- 1.27
TC58FVB800F/FT - Bottom Boot Block (Weight: 2.0 g typ.)
TC58FVT800FT/B800FT : TSOP48 - P - 1220 - 0.50
PIN ASSIGNMENT (TOP VIEW) (Weight: 0.53 gtyp.)
RDY/BSY c 1 V 44 J_WET A15 E 1 C) 48 Cl A16 PIN NAMES
A18 : 2 43 JWE A14 : 2 47 a BYTE
A17 E 3 42 Cl A8 A13 E 3 46 Cl VSS A0 to A18 Address Input
A7 E 4 41:49 A12 E 4 45 : DQ15/A-
A11 E 5 44 Cl D 7
A6 E 5 40 Cl A10 A10 E 6 43 a D814 DQO to DQ14 Data Input/Output
A5E6 393A11 A9 c 7 42 Cl DQ6
A4 E 7 38 Cl A12 A8 E 8 41 Cl DQ13 DQ15/A-1 Output(lnput)/Addresslnput
A3 E 8 37 3A13 NC E 9 40 Cl DQ5 - V
A2 E 9 36 3A14 = l: 10 39 Cl DQ12 CE Chip Enable Input
E Cl -
A1 E 10 353A15 REE’E’E E 1; 3‘73 Cl 33: OE Output Enable Input
A_OE“ 34'IA1_6 NCE 13 36 aDQ11 7
CE C 12 33 J BYTE LC E 14 35 Cl D03 BYTE Word/Byte Select Input
N/AS l: 13 32 Cl VSS RDY/BSY E 15 34 Cl D010 7 _
OE E 14 31 Cl DQ15/A-1 A18 E 16 g; Cl DQg WE Write Enable Input
A17 C 17 Cl D 7
Doc E 15 30 Cl DQ7 A7 E 18 31 D D81 RDY/BSY Ready/Busy Output
DQ8 E 16 29 Cl DQ14 A6 E 19 30 3 DQ8 -
DQ1 E 17 28:I DQ6 A5 E 20 29 D mo RESET Hardware Reset Input
DQ9 E18 27 Cl DQ13 A4 E 21 28 [y OE
DQ2 c 19 26 Cl DQS A3 E 22 27 CI £5 NC No Connection
DQ10 E 20 25: DQ12 A2 E 23 26 a CE
DQ3 E 21 24 Cl D04 A1 E 24 25 Cl A0 VDD Power Supply
DQ11 E 22 23 Cl VDD TC58FVT800FT/B800FT (TSOP) Vss Ground
TC58FVT800F/B800F (SOP)
961001EBA1
operatin
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
BLOCK DIAG RAM
RDY/BSY
VSS o . Buffer I .................... T
= I/O Buffer
Control Auto Sequence
WE o- . . . .
Circuit Control Circuit
BYTE e
W CY Command
Register Program Erase
Circuit Circuit Data Latch
E CE, OE
Control
E Circuit
Column Decoder & Sense Amp
A0 o:- A A
d _ d R
s 3 3 Memory Cell Array
a l? a d
A18 o- f - ct ,
A-1 o-
Erase Block Decoder
1997-12-10 2/28
TOSHIBA
MODE SELECTION
TC58FVT800/B800F/FT-85,-10,-12
BYTE MODE WORD MODE
MODE CE E W A9 A6 A1 A0 W DQO to DQ7 1) DQO to 0015
Read L L H A9 A6 A1 A0 H Dout Dout
ID Read (Manufacturer Code) L L H Vo L L L H Code Code
ID Read (Device Code) L L H Vo L L H H Code Code
Standby H * * * * * * H High-Z High-Z
Output Disable * H H * * * * * High-Z High-Z
Write L H L A9 A6 A1 A0 H Din Din
Block Protect L Vo L Vo L H L H * *
Verify Block Protect L L H Vo L H L H Code Code
Temporary Block Unprotect * * * * * * * Vo * *
Hardware Reset/Standby * * * * * * * L High-Z High-Z
Notes: *: " or VlL
1) DQ8 to DQ15 are High-Z in Byte mode.
IDCODi_5TABLE
CODE TYPE A18 to A12 A6 A1 A0 CODE (HEX) 1)
Manufacturer Code * Ihr, " " 0098H
Device TC58FVT800 * vIL " " 004FH
Code TC58FVB800 * " " " OOCEH
Verify Block Protect BA 2) " VlH " Data 3)
Notes: *: " or "
1) DQ8 to DQ15 are High-Z in Byte mode
2) BA: Block Address
3) 0001H - Protected Block
OOOOH - Unprotected Block
BYTE = vIL
BYTE = "
: Byte mode
.' Word mode
1997-12-10 3/28
TOSHIBA
COMMAND DEFINITIONS
TC58FVT800/B800F/FT-85,-10,-12
COMMAND Jlfh FIRST BUS SECOND BUS THIRD BUS FOURTH BUS FIFTH BUS SIXTH BUS
SEQUENCE CYCLES WRITE CYCLE WRITE CYCLE WRITE CYCLE READNVRITE CYCLE WRITE CYCLE WRITE CYCLE
REQ'D Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset 1 XXXXH FOH
Read/Reset Word 3 5555H AAH 2AAAH 55H 5555H FOH RA 1) RD2)
Byte AAAAH SSSSH AAAAH
ID Read/ Word 3 5555H AAH 2AAAH 55H 5555H 90H IA” ID“)
Verify Block
Protect Byte AAAAH 5555H AAAAH
Auto Word 4 5555H AAH 2AAAH 55H 5555H AOH PA5) PDS)
Program
Byte AAAAH 5555H AAAAH
Auto Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Chi Erase
p Byte AAAAH 5555H AAAAH AAAAH 5555H AAAAH
Auto Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA7) 30H
Block Erase
Byte AAAAH 5555H AAAAH AAAAH 5555H
Block Word 6 SSSSH AAH 2AAAH 55H 5555H 9AH 5555H AAH 2AAAH 55H 5555H 9AH
Protect
Byte AAAAH 5555H AAAAH AAAAH 5555H AAAAH
Block Erase Suspend Addr: " or VIL, Data: BOH
Block Erase Resume Addr: VIH or VIL, Data: 30H
Notes: The system should generate the following address patterns: 4) ID : ID Data
Word mode: 5555H or 2AAAH to addresses A14 to A0 0098H - Manufacturer Code
Byte mode: AAAAH or 5555H to addresses A14 to A-1 004FH - Device Code(TC58FVT800)
DQ8 to DQ15 are ignored in Word mode. OOCEH - Device Code(TC58FVB800)
0001H - Protected Block
: Read Address
: Read Data
: ID Address(A6,
A1, A0)
00H = Manufacturer Code
01H = Device Code
02H =Verify Block Protect (A18to A12 = Block Address)
0000H - Unprotected Block
5) PA : Program Address
6) PD : Program Data
7) BA : Block Address
Addresses are A18 : A1 in Byte mode (BYTE = Vd
Addresses are A18 : A0 in Word mode (BYTE = VIH)
HARDWARE STATUS FLAGS
STATUS DQ7 DQ6 DQ5 DQ3 RDY/Biy
Auto Programming Dtj7 Toggle 0 0 0
In Progress Auto Erase(Erase Hold Time) 0 Toggle 0 0 0
Auto Erase 0 Toggle 0 1 0
Time Limits Auto Programming Dtj7 Toggle 1 1 0
Exceeded Auto Erase 0 Toggle 1 1 0
Notes: l. DO outputs cell data and RDymiy outputs 1 when the operation has completed.
2. DQO, DQ1 and DQ2 pins are reserved for future use.
3. DQ8 to DQ15 Output 0 or 1 in Word mode.
4. DQO to D02 and DQ4 : Output 0.
TOSHIBA
TC58FVT800/B800F/FT-85,-10,-12
BLOCK ERASE ADDRESS TABLES
TC58FVT800 (Top Boot Block)
BYTE MODE WORD MODE
BLOCK# A18 A17 A16 A15 A14 A13 A12
ADDRESS RANGE SIZE ADDRESS RANGE SIZE
BAO L L L L * * * 00000H to OFFFFH 64 Kbytes 00000H to 07FFFH 32Kwords
BA1 L L L H * * * 10000H to 1FFFFH 64 Kbytes 08000H to OFFFFH 32K words
BA2 L L H L * * * 20000H to 2FFFFH 64 Kbytes 10000H to 17FFFH 32K words
BA3 L L H H * * * 30000H to 3FFFFH 64 Kbytes 18000H to 1FFFFH 32K words
BA4 L H L L * * * 40000H to 4FFFFH 64 Kbytes 20000H to 27FFFH 32K words
BA5 L H L H * * * 50000H to SFFFFH 64 Kbytes 28000H to 2FFFFH 32K words
BA6 L H H L * * * 60000H to 6FFFFH 64 Kbytes 30000H to 37FFFH 32K words
BA7 L H H H * * * 70000H to 7FFFFH 64 Kbytes 38000H to 3BFFFH 32Kwords
BA8 H L L L * * * 80000H to 8FFFFH 64 Kbytes 40000H to 47FFFH 32K words
BA9 H L L H * * * 90000H to 9FFFFH 64 Kbytes 48000H to 4FFFFH 32K words
BA10 H L H L * * * AOOOOH toAFFFFH 64 Kbytes 50000H to 57FFFH 32K words
BA11 H L H H * * * BOOOOH to BFFFFH 64 Kbytes 58000H to 5FFFFH 32K words
BA12 H H L L * * * c0000H to CFFFFH 64 Kbytes 60000H to 67FFFH 32K words
BA13 H H L H * * * D0000H to DFFFFH 64 Kbytes 68000H to 6FFFFH 32K words
BA14 H H H L * * * E0000H to EFFFFH 64 Kbytes 70000H to 77FFFH 32K words
BA15 H H H H L * * FOOOOH to F7FFFH 32 Kbytes 78000H to 7BFFFH 16Kwords
BA16 H H H H H L L F8000H to F9FFFH 8Kbytes 7C000H to 7CFFFH 4Kwords
BA17 H H H H H L H FAOOOH to FBFFFH 8Kbytes 7D000H to 7DFFFH 4K words
§A18 H H H H H H * FCOOOH to FFFFFH 16 Kbvtes 7§000H to 7FFFFH 8K words,
TC58FVB800(Bottom Boot Block)
BYTE MODE WORD MODE
BLOCK# A18 A17 A16 A15 A14 A13 A12
ADDRESS RANGE SIZE ADDRESS RANGE SIZE
BAO L L L L L L * 00000H to 03FFFH 16 Kbytes 00000H to 01FFFH 8K words
BA1 L L L L L H L 04000H to 05FFFH 8Kbytes 02000H to 02FFFH 4K words
BA2 L L L L L H H 06000H to 07FFFH 8Kbytes 03000H to 03FFFH 4K words
BA3 L L L L H * * 08000H to OFFFFH 32 Kbytes 04000H to 07FFFH 16K words
BA4 L L L H * * * 10000H to 1FFFFH 64 Kbytes 08000H to OFFFFH 32K words
BA5 L L H L * * * 20000H to 2FFFFH 64 Kbytes 10000H to 17FFFH 32K words
BA6 L L H H * * * 30000H to 3FFFFH 64 Kbytes 18000H to 1FFFFH 32Kwords
BA7 L H L L * * * 40000H to 4FFFFH 64 Kbytes 20000H to 27FFFH 32Kwords
BA8 L H L H * * * 50000H to 5FFFFH 64 Kbytes 28000H to 2FFFFH 32K words
BA9 L H H L * * * 60000H to 6FFFFH 64 Kbytes 30000H to 37FFFH 32K words
BA10 L H H H * * * 70000H to 7FFFFH 64 Kbytes 38000H to 3FFFFH 32K words
BA11 H L L L * * * 80000H to 8FFFFH 64 Kbytes 40000H to 47FFFH 32K words
BA12 H L L H * * * 90000H to 9FFFFH 64 Kbytes 48000H to 4FFFFH 32K words
BA13 H L H L * * * AOOOOH toAFFFFH 64 Kbytes 50000H to 57FFFH 32Kwords
BA14 H L H H * * * BOOOOH to BFFFFH 64 Kbytes 58000H to 5FFFFH 32Kwords
BA15 H H L L * * * COOOOH to CFFFFH 64 Kbytes 60000H to 67FFFH 32K words
BA16 H H L H * * * DOOOOH to DFFFFH 64 Kbytes 68000H to 6FFFFH 32K words
BA17 H H H L * * * EOOOOH to EFFFFH 64 Kbytes 70000H to 77FFFH 32K words
BA18 H H H H * * * FOOOOH to FFFFFH 64 Kbvtes 78000H to 7FFFFH 32K words
* I " or "
Addresses are A18 :
Addresses are A18 :
A1 in Byte mode (BYTE = VIL)
A0 in Word mode (BYTE = VIH)
1997-12-10 5/28
TOSHIBA
ABSOLUTE MAXIMUM RATINGS
TC58FVT800/B800F/FT-85,-10,-12
SYMBOL PARAMETER RANGE UNIT
VDD VDD Supply Voltage -0.6 to 4.6 V
VIN Input Voltage -th6 to VDD + 0.5 (S4.6) V
VDQ Input/Output Voltage -0.6 to VDD + 0.5 (S4.6) V
Po Power Dissipation 0.6 W
TSOLDER Soldering Temperature (10s) 260 T
TSTG Storage Temperature -55 to 150 ''C
TOPR Operating Temperature -40 to 85 °C
NEW Erase/Program Cycling Capability 100,000 Cycles
VIDH Maximum Input Voltage I) 13.0 V
IOSHORT Output Short Circuit Current 2) 100 mA
1) VIDH supply for more than 10 seconds is not recommended. The device could be damaged.
2) Outputs should be shorted for no more than one second.
No more than one output should be shorted at a time.
CAPACITANCE (Ta = 25°C, f=1 MHZ)
SYMBOL PARAMETER CONDITION TYP. MAX UNIT
CIN Input Pin Capacitance " = 0V 4 8 "
COUT Output Pin Capacitance VOUT = 0V 10 12 "
Ga Control Pin Capacitance VIN = 0V 8 10 "
This parameter is periodically sampled and is not tested for every device.
RECOMMENDED DC OPERATING CONDITIONS (Ta---40 to 85°C)
SYMBOL PARAMETER MIN MAX UNIT
VDD VDD Supply Voltage 2.7 3.6
" Input High Level Voltage 0.7 VDD VDD + 0.5 V
VIL Input Low Level Voltage -0.3 1) 0.8
vo Voltage for ID Read and Block Protect 2) 11.4 12.6
1) -2V (pulse width of 20 ns Max)
2) VIDH supply for more than 10 seconds is not recommended. The device could be damaged.
1997-12-10 6/28
TOSHIBA
TC58FVT800/B800F/FT-85,-10,-12
DC CHARACTERISTICS (Ta = -40 to 85°C, VDD = 2.7 to 3.6V)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
ILl Input Leakage Current 0V s " s VDD - :1
Lo Output Leakage Current 0V E VOUT E VDD - i1
VOH1 Output High Voltage(TTL) IOH = -0.4 mA 2.4 -
IOH = -0.1 mA VDD -0.4 -
V0H2 Output High Voltage(CMOS) V
lor, = -2.5 mA 0.85 X VDD -
VOL Output Low Voltage IOL = 4.0 mA - 0.4
|DDO1 VDD Average Read Current Vm: = Shri / V'L’. IOUT = 0mA - 30
CYCLE = in (min)
IDDOZ VDD Average Program Current VIN = " / VIL, IOUT = 0mA - 40 mA
|DD03 VDD Average Erase Current VIN = " / VIL, IOUT = 0mA - 4O
bos1 VDD Standby Current (TTL) E = RESET = " or RESET = " - 250
- - - - + -
loose VDD Standby Current (CMOS) CE £m- - VDD - 0.2V 10 [1A
or RESET = Vss i 0.2V
lo High Voltage Input Current 11.4V s Vo s 12.6 1) - 200
VLKO Low VDD Lock-out Voltage - - 2.5 V
1) Less than 10seconds
AC TEST CONDITIONS
PARAMETER CONDITION
Input Pulse Level 2.4V / 0.4V
Input Pulse Rise and Fall Time(10% to 90%) 5ns
Timing Measurement Reference Level (Input) 1.5V / 1.5V
Timing Measurement Reference Level (Output) 1.5V / 1.5V
Output Load Cr. (100 pF) + 1 TTL Gate
1997-12-10 7/28
TOSHIBA
TC58FVT800/B800F/FT-85,-10,-12
AC CHARACTERISTICS AND OPERATING CONDITIONS
-85 -10 -12
SYMBOL PARAMETER Ta = -40 to 85 C UNIT
VDD=3.0t0 3.6V VDD = 2.7 to 3.6V
MIN MAX MIN MAX MIN MAX
tRC Read Cycle Time 85 - 100 - 120 - ns
tAcc Address Access Time - 85 - 100 - 120 ns
tcE E Access Time - 85 - 100 - 120 ns
toe E Access Time - 35 - 40 - 50 ns
tCEE E to Output Low-Z 0 - 0 - 0 - ns
tOEE E to Output Low-Z 0 - 0 - 0 - ns
tOEH E Hold Time(Read) 0 - 0 - 0 - ns
tOH Output Data Hold Time 0 - 0 - 0 - ns
tom E to Output High-Z 30 30 - 30 ns
tDF2 E to Output High-Z - 3O - 30 - 30 ns
thD Command Write Cycle Time 85 - 100 - 120 - ns
Us Address Setup Time 0 - 0 - 0 - ns
tAH Address Hold Time 45 - 50 - 50 - ns
tDS Data Setup Time 45 - 50 - 60 - ns
tDH Data Hold Time 0 - 0 - 0 - ns
tWELH W Low Level Hold Time * 45 - 50 - 50 - ns
tWEHH W High Level Hold Time * 20 - 20 - 20 - ns
tCEs E Setup Time to M Active * 0 - 0 - 0 - ns
tCEH E Hold Time from m High Level * 0 - 0 - 0 - ns
toss E Setup to E Active 0 - 0 - 0 - ns
tOEHp E Hold Time (Toggle/Data Polling) 10 - 10 - 10 - ns
tOEHT E High Level Hold Time (Toggle) 20 - 20 - 20 - ns
tppw Auto Program Time 16 ** - 16 ** - 16 ** - pd
tpCEW Auto Chip Erase Time 28 ** - 28 ** - 28 ** - s
thEW Auto Block Erase Time 1.5 ** - 1.5** - 1.5 ** - s
mm VDD Setup Time 500 - 500 - 500 - pd;
tBUSY Program/Erase Valid to RDY/Biy Delay 35 - 40 - 50 - ns
tm, W Low Level Hold Time 500 - 500 - 500 - ns
tREADy W Low Level to Read Mode - 20 - 20 - 20 pd;
tRB RDY/Biy Recovery Time 0 - 0 - 0 - ns
tRH RE/ET Recovery Time 500 - 500 - 500 - ns
tCEBTS E Setup time BYTE Transition 5 - 5 - 5 - ns
tBTD m to Output High-Z - 30 - 30 - 30 ns
tva Vo Transition Time 4 - 4 - 4 - td;
tvps Vo Setup Time 4 - 4 - 4 - pd;
thH E Hold Time (Block Protect) 8 - 8 - 8 - pd;
tppLH m Low Level Hold Time (Block Protect) 100 - 100 - 100 - pd;
tpAS Protect Address Setup Time 0 - 0 - 0 - ns
tpAH Protect Address Hold Time 0 - 0 - 0 - ns
tcEsp E Setup Time (Block Protect) 4 - 4 - 4 - gs
tCEHp E Hold Time (Block Protect) 8 - 8 - 8 - ps
E Control ** : Typ.
1997-12-10 8/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
OPERATING MODES
READ MODE
When the device is set to Read mode, it acts as an asynchronous ROM with an access time of
85/100/120 ns. The device is set to Read mode at power-on or when an Auto - Program/ Erase operation
completes. A software or hardware reset is necessary to return the device to Read mode when an Auto
Program/ Erase operation fails.
STANDBY MODE
There are two methods of entering Standby mode: the first involves using both CE and "rrEgwrr and
the second using only RTilSTtTI1
The first method involves using tTIT" and "rt-rt-grill?'" for mode control. If VDD i 0.2 V (CMOS level) is
applied to tTtf and 'rt-tl-grill?'" when the device is operating in Read mode, the current is reduced below 10
PA. Similarly, if Vm (TTL level) is applied to CE and RESET, the current is reduced below 250 pA.
When using CE for control, make sure that the device is operating in Read mode; otherwise, it is not
possible to enter Standby mode.
The second method involves using only Risth for mode control. IF Vssi0.2 V (CMOS level) is
applied to RE-ET when the device is operating in Read mode, the current is reduced below 10 /dk.
Similarly, if VIL (TTL level) is applied to RE-CET, the current is reduced below 250 PA. The difference
the control method using tTE described above, is that if VIL is applied to RESET when the device is
operating in any mode other than Read mode, it enters Standby mode after stopping the operating
which is currently being executed. This is a hardware reset and is described later.
In standby mode, DQ is put in high-impedance state.
COMMAND WRITE
The TC58FVT800/B800 utilizes the JEDEC command control standard for a single power supply
E2PROM. A command is executed by inputting an address and data into the Command register. The
command is entered by a W Control Write (W pulse with CE = V11, and CyE = VIH) or a CE Control
Write (CE pulse with W = V11, and UE = VIH). The address is latched on the falling edge of either
W or CE. The data is latched on the rising edge of either W or CE. 1/00 to 7 are valid for data
input and 1/08 to 15 are ignored.
A command is when the Reset command is input. The device then enters Read Mode. When an
undefined command is input, the Command register is reset and the device enters Read mode.
RESET {Software Reset)
The device does not enter Read mode automatically when a command such as Auto Program/ Erase or
ID Read is not correctly executed (for example, if Program or Erase fails). The Reset or Read
Command is necessary to return the device to Read mode. The Reset and Read commands must also
be used to reset the Command register.
RESET (Hardware Reset)
A hardware reset is used for aborting Auto mode operations such as Auto Program/Erase and for
resetting the operation mode. The device enters Read mode 20 ps after a 500-ns Low level input pulse
to the RESET pin. Data may be corrupted if the device is reset during an Auto mode operation.
1997-12-10 9/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
After a hardware reset the device enters Read mode when RESET = VIH and Standby mode when
RESET = VIL. The DQ pins are High-Impedance when RESET = VIL. The Read operation sequence
and input of any command are allowed after the device enters Read mode.
ID READ MODE
The ID Read mode is used to establish the device type. The ID Read mode is set either from the
Command mode by inputting a 90H command or from the EPROM mode by applying V11) to the A9
When A0, A1 and A6 = VIL, the data that is read is the manufacturer code (0098H). When A0 =
Vm and A1 and A6 = VIL, the data that is read is the device code (4FH). The access time for an ID
Read is the same as that of a normal Read operation. I/08 to 15 are in High-Impedance state in Byte
mode. A reset command is necessary to return the device to Read mode from command mode. And
applying VIH to the A9 pin is necessary to return the device to Read mode from EPROM mode.
AUTO PROGRAM MODE
The TC58FVT800/B800 can be programmed in either byte or word units. The Auto Program mode is
set using the Program command. The program address is latched on the falling edge of the 1TtTif signal
and data is latched on the rising edge of the fourth bus cycle. Auto programming starts on the rising
edge of the W signal in the fourth bus cycle. The Program and Program Verify commands are
automatically executed by the chip. The device status during programming is determined from the
Hardware Sequence flag.
Programming of a protected block is ignored. The device enters Read mode 3 ps after the rising edge
of the WE signal in the fourth bus cycle.
The device allows the programming of memory cells from 1 to 0. The programming of Memory cells
from 0 to 1 will fail. A cell must be erased to turn it from O to 1.
If an Auto Program operation fails, the device remains in programming state and does not
automatically return to Read mode. The device status can be determined from the setting of the
Hardware Sequence flag. Either a Reset command or a hardware reset is necessary to return the
device to Read mode after a failure.
If a programming operation fails, please do not try to use the block which contains the address to
which data could not be programmed.
Auto ChiE Erase Mode
The Auto Chip Erase mode is set using the Chip Erase command. The Auto Chip Erase operation
starts on the rising edge of WT?' in the sixth bus cycle. All memory cells are automatically
preprogrammed to o, erased and verified as erased by the chip. The device status is determined from
the Hardware Sequence flag.
Command inputs are ignored during an Auto Chip Erase. The hardware reset allows interruption
of an Auto Chip Erase operation. The Auto Chip Erase operation does not complete correctly when
interrupted. Hence a further Erase operation is necessary.
An attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase
operation will not be executed and the device will enter Read mode 100 ps after the rising edge of the
TTE signal in the sixth bus cycle.
If an Auto Chip Erase operation fails, the device remains in, erasing state and does not return to
Read mode. The device status is determined from the Hardware Sequence flag. Either a Reset
command or a hardware reset is necessary to return the device to Read mode after a failure.
1997-12-10 10/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
Auto Block/ Multi Block Erase Mode
The Auto Block and Multi Block Erase modes are set using the Block Erase command. The block
address is latched on the falling edge of the 1Trtf signal in the sixth bus cycle. The Block Erase starts
as soon as the hold time has elapsed after the rising edge of the tTr"fi!- signal. All memory cells in the
selected block are automatically programmed to 0, erased and verified as erased by the chip. The
Multi Block Erase operation allows erasing of multiple blocks. Any additional block addresses or Multi
Block Erase commands must be input within the Erase Hold Time - that is, within 50 ps of any W
signal rising edge. The device status can be determined from the setting of the Hardware Sequence
Commands (except Erase Suspend) are ignored during a Block/Multi Block Erase operation. The
operation can be aborted by a hardware reset. The Auto Erase operation does not complete correctly
when aborted, therefore, a further Erase operation is necessary.
An attempt to erase a protected block is ignored. If all the selected blocks are protected, the Auto
Erase operation is not executed and the device returns to Read mode 100 #s after the rising edge of
the W signal in the last bus cycle.
If an Auto Erase operation fails, the device remains in erasing state and does not return to Read
mode. The device status is determined from the Hardware Sequence flag. Either a Reset command or
a hardware reset is necessary to return the device to Read mode after a failure.
Erase Suspend/Resume Mode
The Erase Suspend mode is used to read data from a block not selected for erasing. The Erase
Suspend command is allowed during a Block Erase operation or during the Block Erase Hold Time; it
is ignored in other operation modes. A Block Erase operation is also suspended if the Suspend
command is input during the Block Erase Hold Time. The device is reset if any command other than
Suspend is input. The suspended device recognizes only Read and Resume commands.
The device enters Suspend mode 15 ps after the Erase Suspend command is input. The device then
enters a pseudo-Read Mode. Data can be read out from an unselected block but is invalid if the
address is set to a block selected for erasing. The device status can be determined from the Hardware
Sequence flag. DQ6 (the toggle bit) stops toggling and RDY/W outputs 1 once the device is set to
pseudo-Read mode. The host processor must track the current device mode since there is no way of
telling whether the device is in pseudo-or ordinary Read mode. The device remains in pseudo-Read
mode even if a Suspend command is input.
The device restarts the Block Erase operation after receiving a Resume command. The device
returns to the status in which the Suspend command was input. The DQ6 output toggles and
RDY/m outputs a 0.
1997-12-10 11/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
BLOCK PROTECT
The TC58FVT800/B800 has a block protection feature to prevent programing and erasing of protected
blocks. Block protection is enabled by either hardware protection (1) or a software command mode (2).
The initial device is shipped with all blocks unprotected.
(1) A blocks is protected when: A9 = UE = VID, CE = VIL, AO/A6 = VIL, A1 = VIH; the block
address is set using A12 to A18. The block protect data is programmed within tppLH of the W
signal going Low.
(2) A block can also be protected using a software command. Block protection is executed by
setting the Tirtl" signal to Low for tppLH while UE = VIL. After the command input in the sixth
bus cycle A12 to A18 = the block address. Block protection can be verified using the Verify
Block Protect command.
TEMPORARY BLOCK UNPROTECTION
The TC58FVT800/B800 has a temporary block unprotection feature which disables block protection
for all protected blocks. Unprotection is enabled by applying VID to the ItTiWtT pin. In this state any
block can be programmed or erased. The device returns to the previous condition after V11) is removed
from the -tThfgTfr'r pin. That is, previously protected blocks are protected again.
VERIFY BLOCK PROTECT
The Verify Block Protect command is used to check whether a block is protected or unprotected.
Verify Block Protect is enabled either through hardware (1) or by a software command (2). In Word
mode 0001H is output when the block is protected and OOOOH is output when it is unprotected. DQ8
to 15 are High-linpedanee in Byte mode.
(1) Verify Block Protection is enabled when: A9 = VID, A0 and A6 = Vu, and A1 = VIH.
A12 to A18 = the block address.
(2) Verify Block Protection can also be enabled using a software command.
1997-12-10 12/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
HARDWARE SEQUENCE FLAG
The TC58FVT800/B800 has a Hardware Sequence flag which allows the device status to be
determined during Auto operation. The output data is read out with the same timing as Read mode at
t2T?" = t"jTi"f" = VIL. RDY/m outputs either High or Low.
The device re-enters the Read mode automatically after Auto operation has completed successfully.
The device status is read out from the Hardware Sequence flag and the operation result is verified by
comparing the read-out data to the original data.
ML? (DATA Polling)
The device status can be determined using the data polling function during an Auto Program or
Auto Erase operation. DA-TA polling begins on the rising edge of W in the last bus cycle. In an
Auto Program operation, DQ7 outputs inverted data during the programming operation and outputs
real data after programming has finished. In an Auto Erase operation, DQ7 outputs 0 during the
Erase operation and outputs 1 when the Erase operation has finished. If an Auto Program operation
fails, DQ7 simply outputs the data.
The latched address is reset after an operation has finished. The polling data is asynchronous with
the tTIT signal.
D 6 (To le Bit)
The device status can be determined by the Toggle Bit function during an Auto Program or Auto
Erase operation. In an Auto Program operation the Toggle bit begins toggling on the rising edge of
W in the last bus cycle. In an Auto Erase operation The Toggle bit begins toggling as soon as the
Erase Hold Time has elapsed after the rising edge of the W signal in the last bus cycle. DQ6
alternately outputs a 0 or a 1 for each attempt (ttE access) while CE = VIL while the device is busy.
When the internal operation has been completed, toggling stops and valid memory cell data can be
read by subsequent reading. If the operation failed, the DQ6 output toggles.
DQ6 toggles for around 3 ps when an attempt is made to execute an Auto Program operation on a
protected block. It then stops toggling. DQ6 toggles for around 100 ps when an attempt is made to
execute an Auto Erase operation on a protected block. It then stops toggling. After toggling stops the
device returns to Read mode.
D 5 (Internal Time-out)
DQ5 outputs a 1 when the Internal Timer has timed out during a Program or Erase operation. This
indicates that the operation has not completed within the allotted time.
An attempt to program 1 into a cell containing 0 will fail (see Auto Program mode). DQ5 outputs 1
in this case. Either a hardware reset or a software Reset command is required to put the device into
Read mode.
1997-12-10 13/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
DQ3 (Block Erase Timer)
The Block Erase operation starts 50 ps (Erase Hold Time) after the rising edge of TtT1ir in the last
command cycle. DQ3 outputs a 0 during the Block Erase Hold Time and a 1 when the Erase
operation starts. Additional Block Erase commands can only be accepted during this Block Erase Hold
Time. Each Block Erase command received within this hold time resets the timer, allowing additional
blocks to be marked for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.
RDY/BSY (READY/BUSY)
TC58FVT800/B800 has a RDY/EW signal to indicate the device status to the host processor. A 0
(Busy state) indicates that an Auto Program or Auto Erase operation is in progress. A 1 (Ready state)
indicates that the operation has finished and that the device can accept a new command. The
RDY/Biy signal outputs a 0 when an operation has failed.
The RDY/BgY signal outputs a 0 after the rising edge of TOf in the last command cycle of a
Program operation and during the Erase Hold Time after the last command cycle of an Erase
operation.
During an Auto Block Erase operation, commands other than Erase Suspend are ignored. The
RDY/rgr"Y""" signal outputs a 1 during an Erase Suspend operation. The output buffer for the RDY/FST
pin is an open drain type circuit, allowing a wired-OR connection. A pull-up resistor needs to be
inserted between VDD and the RDY/FST pin.
DATA PROTECTION
The Tc58FVT800/B800 utilizes a JEDEC standard command sequence which protects data against
accidental alteration due to noise.
Enn Lock-out Voltage
The device is reset when VDD is less than VLKO to protect memory cell data against VDD noise, and
during power-up and power-down. An Auto Program or Erase operation stops when VDD drops below
VLKO. An Erase Suspend operation is reset and an Erase operation stops if the device is in Suspend
mode. An operation will not complete correctly if it is interrupted by VDD Lock-out.
Tirhf Glitch Pulses
Glitches must be suppressed (to less than 5 ns) in order for operation to proceed smoothly.
Protection at Power-on
A command is not recognized on the rising edge of 1'h7t'Tif VDD rises from 0 V to the operating
voltage while W = IrIL,CE = VII, and CyE = VIH. In this case the device is reset and enters Read
1997-12-10 14/28
TOSHIBA
TIMING DIAGRAMS
Read/ ID Read Operation
TC58FVT800/B800F/FT-85,-10,-12
Address )( )(
tAcc t0H
E si) f"
toe tDF1
a A /"
tCEE tDF2
High-Z High-Z
Dout DOUT Valid
ID Read Operation (Hardware)
A0 sih RF'"
A,isi' tAcc
A6 a A'"
12 v ----------- ,
3V - tvps
E si) /2iit A"
High-Z
Notes: 0098H - Manufacturer Code
004FH - Device Code (TC58FVT800)
OOCEH - Device Code (TC58FVB800)
1997-12-10 15/28
TOSHIBA
TC58FVT800/B800F/FT-85,-10,-12
Auto Program Operation (WET Control)
'giits,/js/ieis,
_ ‘ tCEH
tWELH tWEHH
tDs tDH
Notes: Word mode address shown
PA: Program address
PD: Program data
Auto Chip Erase/Auto Block Erase Operation (W Control)
Notes: Word mode address shown
BA:Block address for Auto Block Erase operation
1997-12-10 16/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
DATA Polling during Program/Erase Operation
Command
Add ress
Add ress
PA/BA XF'"
E sh f2 A,,,
a \ 2|! t
tOEHP on
U tPPW/tPCEW/ tPBEW
' Last
Din Command
Notes: PA: Program address
BA: Block address
Toggle Bit during Program/Erase Operation
)( PA/BA )(F"
Command
Add ress
Add ress
tces L tOEHT
tOE st"
. Last
Din Command
Dout6 Toggle Toggle Toggle (ve)
Dout6 stops toggling when the last command has completed.
Notes: PA: Program address
BA: Block address
1997-12-10 17/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12
RDY/BSY during Auto Program/Erase Operation
c7 -l /
Command input sequence
MW ...... 'sc/
RDY/BSY l
During operation
Hardware Reset Operation
RESET l
tREADY
RDY/BTY N /
Read after RESET
Address
High-Z
Data valid
1997-12-10 18/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
BYTE during Read Operation
tCEBTS
DOC to D07 2" Wig J Data output 8B. ..3
DQ8 to DQ14 output
- A r In
DQ15/A 1 output dd ess put
BYTE during Write Operation
ss-s-l-,,,,,"":.,,,?''''",,;,,?'"
1997-12-10 19/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
Block Protect Operation (Hardware)
Block Protect Verify Block Protect
A18toA12 a,gi)( BA XF'"
12 V -_----_----- -
3V -- N
E tVPH
tcgsp 's-ll
High-Z
BA: Block address
* : 0001H indicates that block is protected.
1997-12-10 20/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
Block Protect {Software}
Block Protect Setup I Block Protect Verify Block Protect
/-)r /-)r l-hit-e-l-
_\_/ U L/ L/ L/
Din 9AH AAH 90H
Add ress
BA .' Block address
* : 0001H indicates that block is protected.
1997-12-10 21/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
F LOWC HARTS
Auto Program
( Start )
Auto Program Command Sequence
(see below)
DATA Polling or Toggle Bit
Last Add ress?
Increment Address
Auto Program Completed
Auto Program Command Sequence (Address/Command)
5555H/AAH
2AAAH/55H
5555H/AOH
Program Address/Program Data
Note: Word mode command sequence is shown.
1997-12-10 22/28
TOSHIBA
Auto Erase
TC58FVT800/B800F/FT-85,-10,-12
l Start V
Auto Erase Com
mand Sequence
(see below)
DATA Polling
or Toggle Bit
Auto Erase
Completed
Auto Chip Erase Command Sequence
(Address/Command)
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
Auto Block/Multiple Block
Erase Command Sequence (Address/Command)
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Block Address/30H
Block Address/30H
Block Address/30H
Word mode command sequence is shown.
Additional Block
Erase commands
are optional
1997-12-10 23/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
DQ7 DATA Polling
Read Byte (DOC to DQ7)
Addr. = VA
DQ7 = Data?
Read Byte (DQO to DQ7)
Addr. = VA
DQ7 = Data?
Fail Pass
Byte address for programming.
Any of the addresses within the block being erased during a Block Erase operation.
Don't care during a Chip Erase operation
1) DQ7 must be rechecked even if DOS: 1 because DQ7 may change at the same time as DQ5.
ME Toggle Bit
Read Byte (DOC to DQ7)
Addr. = VA
DQ6 = Toggle?
'-2::zzrrCCiiiisFriiCcccrcrcz--s
Yes 1)
Read Byte (DQO to DQ7)
Addr. = VA
DQ6 = Toggle ?
Fail Pass
Byte address for programming.
Any of the addresses within the block being erased during a Block Erase operation.
Don't care during a Chip Erase operation
Any address not within the current block during an Erase Suspend operation
1) DQ6 must be rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time that
DQ5 changes to 1.
1997-12-10 24/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
Set up Block Address
Block Protect (Hardware)
Addr. = BA
PLSCNT = 1
E=A =Vo, E=v,L
A6,A1, Ao=0, 1,0
Active W Pulse
Time-out 100 ps
A9 = Vo,
vt/E = VIH: E = OE = VIL Increment PLSCNT
Read from Block
Address = BA; A6, A1, A0 = o, 1, 0
Data = 01H? PLSCNT = 25?
Yes Yes
Protect Another Block? Device Failed
Remove Vo from A9
Block Protect Complete
BA: Block address
1997-12-10 25/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
Block Protect {Software}
PLSCNT = 1
Write Block Protect
Command Sequence
= VIH: tte = VIH: m = "
Set up Block Address
Address = BA
Time-out 100 td
= VIH. E = VIH: m = " Increment PLSCNT
Time Out 4 M;
Write ID Read Command Sequence
l Write Reset Command Sequence
Read from Block
Address = BA; A6,A1,A0 = 0,1,0
Data = 01H , @
Yes Yes
Write Reset Command Sequence
Protect Another Block?
Block Protect Complete
Device Failed
BA: Block Address
1997-12-10 26/28
TOSHIBA TC58FVT800/3800F/FT-85,-10,-12
PACKAGE DIMENSIONS
0 Plastic SOP
SOP44-P-600 - 1.27
i1i'aucisusuesaaaiiuriia'ii--
...,i1j'iti'"'"i"-t,i,sC.i,,l,i,,,,i.i2i?i--
21.tELtL'. 0.35:0.1025
_ vi-ii,, ,2, (
"''"'''""''''"''u'LLi,r.1' ———————————— ii:'.' ELI 0.8:02
1997-12-10 27/28
TOSHIBA
TC58FVT800/B800F/FT-85,-10,-12
PACKAGE DIMENSIONS
0 Plastic TSOP
TSOP I 48 -P- 1220 -0.50
Unit: mm
21:: 48 00
iF] c!
E] 'st
Iii N.
113 co,
II: 8 _
fi?, g Fil
'aL'r.a' ‘L m 53
£5 k 0
18.4dc0.1 _ ii, 1.0:o.1_ 40.1:005
20.0:02 ai 1.2MAX I
0.53c0.1
1997-12-10 28/28
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