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TC5816BFT
16 MBIT (2M x 8BITS) CMOS NAND FLASH E2PROM
TOSHIBA TC5816BFT
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
16 MBIT (2 M x SBITS) CMOS NAND FLASH EZPROM
DESCRIPTION
The TC5816 device is a sin 1e 5.0-volt 16 Mbit NAND Electrically Erasable and Programmable Read
Only Memor (NAND Flash EPROM) with s are 64K X 8bits. The device is orianized as 264 byte X
16 pages X 12 blocks. The device has a 264- yte, static register; which allows t e program and read
data to be transferred between the register and the memory cell array in 264-byte increments. The
Erase o eration is implemented in a single block unit (4 K..b,ytes + 128 bytes: 264 bytes M 16 pages),
The C5816 is a serial type of memory device which utilizes the I/O pins for both address and data
input/output as well as command inputs,. The Erase and Pro am o erations are automatically
executed, making the device most suitable for applications sue as so id state file storage, voice
recording, image file memory for still cameras and other systems which require high-density, and non-
volatile memory data storage.
FEATURES
0 Organization 0 Access time
Memory cell array 264 X 8 K X 8 Cell array-Re ister 25 ps max
Register 264 X 8 Serial Read ycle 80 ns min
Page size 264 byte 0 Operating current
Block size (4K + 128) bytes Read (80 ns cycle) 15mA typ
tt Mode Program(ave.) 40mA typ
Read, Reset, Auto Page Program Erase (ave.) 20mA typ
Auto Block Erase, Suspend/Resume, Status Read Standby 100 PA
0 Mode control 0 Package
Serial input/output 400 mil TSOP Type 11
Command control TC5816BFT .' TSOP ll 44/40 - P - 400 - 0.80B
0 Power supply (Weight: 0.48 g typ)
Vcc = 5.0V i 0.5V
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
TC5816BFT
..................................................... l/O 1 t 8 " p rt
i.' Vss l: 1 44 Cl kc j o o
i' CLE I: 2 43 3g 3 E Chip Enable
2% I: 3 42 Cl RE :
5 E I: 4 41 Cl R/B i' m Write Enable
'....yytC.5.....................4.0...ug..N.p..i'
NC I: 6 39 Cl NC E Read Enable
NC I: 7 38 Cl NC
NC I: 8 37 Cl NC CLE Command Latch Enable
NC I: 9 36 Cl NC
NC I: 10 35 Cl NC ALE Address Latch Enable
12 33 W Write Protect
NC I: 13 32 Cl NC _
'lf E :2 :3 gmg GND Ground Input
giI-gEH-E "ill,-------),'- tcl-tii,-..., VCC/VSS Power Supply/Ground (5.0 V/GND)
51/02 E19 26 31/07-
§I/o3 E 20 25 Cl 1/06
51/04 I: 21 24 31/05
:i..)./.ss...rC. o2..2...................2..3..p..y.c.c...j.
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-07-01 1/36
BLOCK DIAGRAM
VCC VSS
j"Status-register i t
I/O10_ Address register I I = Column buffer
i I/O Control
to : . . -p) = Column decoder
: circuit '
IIO 8ci-F -rl Command register I _ Data register
" e Sense amp 4-
a o-F , B
W f R d
CLE o-F a f o e
ALE o-r Logic antrpl g t 'ff f, Memory
W control arcunt f g g 'il. cell array
R" o-e , r
vrtp CY-F f
R/IT o
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
Vcc Power Supply - 0.6 to 7.0 V
" Input Voltage - 0.6 to 7.0 V
VI/o Input/Output Voltage - 0.6V to Vcc + 0.5V (E 7.0V) V
PD Power Dissipation 0.5 W
TSOLDER Soldering Temperature (10s) 260 "C
TSTG Storage Temperature - 55 to 150 "C
TOPR Operating Temperature 0 to 70 T
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT
Cm Input " = 0V - 5 10 "
Cour Output VOUT = 0V - 5 10 "
* This parameter is periodically sampled and is not tested for every component.
TOSHIBA TC5816BFT
VALID BLOCK fl)
TC5816
SYMBOL PARAMETER UNIT
MIN TYP MAX
NVB Valid Block Number 502 508 512 Blocks
(1) The TC5816 occasionally contains unusable blocks. Refer to Application Note (17) toward the
end of this document.
DC RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN TYP MAX UNIT
Vcc Power Supply 4.5 5.0 5.5 V
" High Level Input Voltage 2.2 - Vcc + 0.5 V
" Low Level Input Voltage - 0.3* - 0.8 V
* - 2V (pulse width E 20 ns)
DC CHARACTERISTICS (Ta = 0° to 70°C, Vcc = 5.0 V i 0.5 V)
SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT
u. Input Leak Current VIN = 0V to Vcc - - i 10 prA
lLo Output Leak Current VOUT = 0.4V to Vcc - - i 10 ,uA
Iccol Operating Current (Serial Read) E = VIL, lout = 0 mA,tcycle = 80 ns - 15 30 mA
lccoz Operating Current (Command Input) tcycle = 80 ns - 15 30 mA
Iccos Operating Current (Data Input) tcyde = 80 ns - 40 60 mA
Iccop Operating Current (Address Input) tcyde = 80 ns - 15 30 mA
lccos Programming Current - - 40 60 mA
Icco6 Erasing Current - - 20 40 mA
Iccs1 Standby Current E = VIH - - 1 mA
lccsz Standby Current E = Vcc - 0.2V - - 100 p/k
VOH High Level Output Voltage IOH = - 400pA 2.4 - - V
VOL Low Level Output Voltage IOL = 2.1 mA - - 0.4 V
IOL(R/§) Output Current of (R/iT) Pin VOL = 0.4V - 8 - mA
TOSHIBA TC5816BFT
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = (Y' to 70°C, Vcc = 5.0V i 0.5V) (1)
SYMBOL PARAMETER MIN MAX UNIT NOTE
tCLs CLE Set-Up Time 20 - ns
tcLH CLE Hold Time 40 - ns
tcs E Set-Up Time 20 - ns
tCH E Hold Time 40 - ns
twp Write Pulse Width 40 - ns
tALS ALE Set-Up Time 20 -. ns
tALH ALE Hold Time 40 - ns
tDs Data Set-Up Time 30 - ns
tDH Data Hold Time 20 - ns
twc Write Cycle Time 80 - ns (2)
tWH W High Hold Time 20 - ns
tww W High to m Falling Edge 100 - ns
tRR Ready to E Falling Edge 20 - ns
tec Read Cycle Time 80 - ns
tREA E Access Time (Serial Data Access) - 45 ns
tCEH E High Time for the Last Address in Serial Read Cycle 250 - ns (4)
tREAID w Access Time (ID Read) - 45 ns
tRHz E High to Output High Impedance - 30 ns
km E High to Output High Impedance - 20 ns
tREH E High Hold Time 20 - ns
th Output High Impedance to E Rising Edge (Status Read) 0 - ns
tRSTO R-E Access Time (Status Read) - 45 ns
tCSTO E Access Time (Status Read) - 55 ns
tRHW M High to W Low 0 - ns
tWHC W High to E Low (Status Read) 50 - ns
tWHR W High to W Low (Status Read) 50 - ns
tAm ALE Low to E Low (ID Read) 200 - ns
tCR E Low to E Low (ID Read) 200 - ns
tR Memory Cell Array to Starting Address - 25 M;
tws W High to Busy - 200 ns
tAR2 ALE Low to E Low (Read Cycle) 150 - ns
tRB E Last Clock Rising Edge to Busy (in Sequential Read) - 200 ns
tCRY E High to Ready (in Case of Interception by E in Read Mode) - 600+tr(R/iT) ns (3)
tRST Device Reset Time (Read/Program/Erase/after Suspend) - 10/20/500/10 ,as
AC TEST CONDITIONS
Input level : 2.4 V / 0.6 V
Input comparison level : 2.2 V/0.8 V
Output data comparison level : 2.0V/ 0.8V
Output load : 1 TTL & CL (100 pF)
1998-07-01 4/36
TOSHIBA TC5816BFT
(1) Transition time (tT) = 5 ns
(2) When CLE, ALE and UE are input at the clock pulse, twc will exceed 80 ns
Set-Up Time + Hold Time + twe + txx + 4_tT
20 ns 40 ns 40 ns 20 ns
-txx-'
E S 2 S
tT tr, " h
W N if', '-/'"
8 Hold Time "s .
Set-Up twp Set-Up Time
(3) The UE High to Ready time depends on the pull-up resistor tied to the MT pin. (Refer to
Application Note (10) toward the end of this document.)
(4) If the delay between RE and CE is less than 200 ns and tCEH is greater than or equal to 250 ns,
readingvill -sty.
If the RE-to-CE delay is less than 30 ns, the device will not return to the Busy state.
tCEH 2 250 ns
* *: " or "
262 263 ID, Ci): 0 to 30 ns -9 Busy signal is not output.
R/E \Busy/
PROGRAMMING AND ERASING CHARACTERISTICS (Ta = ty' to 70°C, Vcc = 5.0V i 0.5V)
SYMBOL PARAMETER MIN TYP MAX UNIT NOTE
tpROG Average Programming Time 200 to 500 3000 M;
N Number of Programming Cycles on Same Page 10 (1)
tBERASE Block Erasing Time 4.5 100 ms
tSR Suspend Input to Ready 500 M;
NW/E Number of Write/Erase Cycles 1 x 105 cycles (2)
(1) Refer to Application Note (15) toward the end of this document.
(2) Refer to Application Note (18) toward the end of this document.
1998-07-01 5/36
TOSHIBA TC5816BFT
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address /Data
ALE tF"
E Set-Up Time Hold Time
tos tDH
I/O1to8 - t
Command Input Cycle Timing Diagram
) tCLS tCLH \
CE N cs CH I
m ire/
tALs tALH
ALE %‘ tr"
tos tDH
I/O1to8 Ai)l tir'"
'rp?f/y, I " or "
1998-07-01 6/36
TOSHIBA
TC581 til? FT
Address Input Cycle Timing Diagram
twc twc
CE tiit
th tWH
tWP _ twe twe
WE i Z S 2 S
4 tALS tALH
ALE 2 \
I tos tDH tos tDH tos tDH
HO 1 to 8
A A0 to A7 :A8 to A15 F" [AIS to A20
Data Input Cycle Timing Diagram
tALs t
twp twp twp
tos tDH tos tDH
A a tor,
I/O1to8 _ DINO sd; DIN1 (ES) DIN263 W
fgift : " or "
1998-07-01 7/36
TOSHIBA TC5816BFT
Serial Read Cycle Timing Diagram
I/O1to8
Status Read Cycle Timing Diagram
- tCLs
CLE / '
tCLS tCLH
tcs JV
3 —\F’ F'" % I
- —j twp t
WE ( 2 WHC tCSTO ECHZ
RE S -
t t th L
DS DH _ tRHZ
tRSTO S
- tatus -
I/O1to8 —] 70H W'" wi'] - output J
if2j5f. I " or "
1998-07-01 8/36
TOSHIBA TC5816BFT
Read Cycle (1) Timing Diagram
CLE tc tCLH R
tcs CH tcs 4
CE ltr' 61% tl tl / Al
7 - '-,f - - -
WE I , l Z I I l il tR I tCRY
tALS tAroL tAR2
tALH J.
tWB l tRC
RE L/N/Tc-s/N)
tos tDH tos tDH tos tDH tos tDH
- - l"' 0 - 0 tREA
A0 to A8 to A16 t t Jour Dom ..... ou -
I/O1to8 00H (t2)t A7 WAS A20! N ) Ei)
Column address
Read Cycle (1) Timing Diagram : Interrupted by CE
CLE tc tCLH R
t tCH tcs
- cs 9 'V
I I twc
- - 'f _ - -
WE N l \ il N I 2 tR I
ffe, tacc tAR2 tCHZ
ng l 4 tec
E L/N/N/N)
tos tDH tDS tDH tos tDH tos tDH tRHZ
- - l0 0 0 _ tREA ,
A0 to A8 to A16 t t l DOUT DOUT -
Column address
MT \r_/ iij5)j2, : " or "
1998-07-01 9/36
TOSHIBA TC5816BFT
Read Cycle (2) Timing Diagram
EN!“ tc"., 2, a a ,,
CLE tcLs tCLH '
"MVA."'"
Tf . A ''
m H LC\lc/ te
tALS - ’
4 tWB tARz
ALE 2 W p''
tan, 4 tec
E U V”
tos tor, Jr: tDH -
- tt tREA
V01 A0 to A8 to A16 to \ - w
to 8 50 ty'" si/is A15 A20 / OUT - OUT
Column address 256 + M 256 + M +1 263
R/B ) 7"
Sequential Read Timing Diagram
LE / '
tt bt bb "
FF " \\ ''
"t F'1gi1 El fl '' bb
- -f, Sk \\
WE \ / L/VIL-
'' bb bb bb
' " ll lk
tl/O; At 00H W AA; 7toXA:1A8 to A1A6 Oto
Column Page te
address address
R/E l ii i
Page M Page M + 1 "
access access 7% : " or VIL
1998-07-01 10/36
Auto Program Operation Timing Diagram
TC5816BFT
tCLS n
CLE / tiii'it'ti'i/ '
tcs bb
CE 'N - - ll g 'Ctr'iit1 EI
tcs tCH
7 - - i''"
WE U ssiLr)c/Njt,u,, \J’LFW ES? L?
0 4 t tPROG
tALH ALS ''
ALE 2 I tum tit'iA
a W" \ /
tos tDH tos tDH tDS ..
0 _ tDH tDS tDH
I/OI 'A0 to A8 to A16 to H F
to8 80H ti)t A7 - A15 A20 \
Status
output
Auto Block Erase Timing Diagram
: If data is being output, do not allow any input.
CLE t S / W" A \ EEE
E tcu; V % a V
tALS tALH tvvs tBERASE
ALE Z R V Ah V
W W" V \ /
tDs tDH
l/OI A8 to A16 to MSg44SietgiAS Status
12g%ig%WeeEgg%' 7 H
to 8 60H A1 5 A20 DOH 828j8?8A8W8i8 pm»; :.: 0 out C ut
Auto Block Erase
Set-Up
command
f/gg' : " or "
is Busy /
Erase Start
command
Status Read
command
: If data is being output, do not allow any input.
TOSHIBA
Suspend/Resume on Block Erase Operation Timing Diagram
TC5816BFT
- ’3 (a)
CLE tCLs S l W" % t \ ('" A,', a
- t CLH '
tCLH tCLH CLS c'l
E A, tCLs % % 1% /{3
tcs ‘tWP tcs tCH ’ '
- -e, - - t - '
WE S FLFLFU W A/ 33“? W42
tALS tALH tALS
tALH - - tALH x3
ALE l ' I 2 f" s'',',',
RE W" % t t WV',',
tos tDH tDs tDH DS DH '
£20; 260H @9331? BOH I (e')')
_ tSR )l
R/B WA?
CLE 2EEi2c/tcLs-tcLHI / \
WE Eiiiiiiiiiiii7-'ic) ,
II JALS tALH
tRHW|"’I
't7 ll / 5iii7 "u/
tos tDH tDs LB: tRSTO
- o _ r
if; CiiiiEiiEE)-t DOH f-l 70H Flirt/tpi)-
R/B ll / 1_/
(a): Continued
"tiii) : " or "
: If data is being output, do not allow any input.
1998-07-01 12/36
TOSHIBA TC5816BFT
ID Read Operation Timing Diagram
tCH JCLS
c-e-'") %% Eil)
WE i tCR
tALS - _
tALH tCH tAR 1
ALE , j
E tos SEE I
:20; -t' 90H f-CD--! 98H ' I 61th '
i tREAID .i.' tREAID ,
Addiress Malier Devicé code
input code
tire, : " or "
1998-07-01 13/36
TOSHIBA TC5816BFT
PIN FUNCTIONS
The TC5816 is a serial access memory which utilizes time-sharing input of address information. The
device pin-outs are configured as shown in Figure I.
Command Latch Enable: CLE
The CLE input signal is used to control the acquisition of the V
. ' . . Vss l: 1 44 Cl Vcc
operation mode command into the internal command register. The -
command is latehed_ipto the command register from the I/O port on the CLE E 2 43 Cl CE
rising edge of the WE signal while CLE is high. ALE E 3 42 3E
m I: 4 41 Cl MT
Address Latch Enable: ALE vrtp I: 5 40 Cl GND
The ALE signal is used to control the acquisition of either address Ct.: TOP 'e.
information or input data into the internal address/data r_egister. VIEW
()itlr.ess information is latched on the rising edge of WE if ALE is I/OI I: 18 27 CII/O 8
Input data is latched if ALE is low. I/02 l: 19 26 Cl I/O?
IIO3 l: 20 25 Cl I/O6
Chip Enable: C-E I/O4 I: 21 24 Cl |/05
The device goiinto a low powerLgtandby mode during a Read Vss I: 22 23 Cl Vcc
operation when CE goes high. Tlle CE signal is ignored when the
device is in the Busy state (R/B = L), such as during a Progr_am or Figure 1. TC5816 Pinout
Erase operation, and will not go into Standby mode even if a CE high
signal is input.
Write Enable: "W'''rt"
The W signal is used to control the acquisition of data from the I/O port.
Read Enable: TtTil"
The Tff?" signal controls serial data output. Data is available tREA after the falling edge of RE.
The internal column address counter is also incremented (Address + 1) on this falling edge.
I/O Port: I/O 1 to 8
The I/O 1 to 8pins are used as the port for transferring address, command and input/output data
information to or from the device.
Write Protect .' W
The WP signal is used to protest. the device from accidental rogramming or erasing. The internal
voltage regulator is reset when WP is low. This signal is usua ly used for protecting the data during
the power on/off sequence when input signals are invalid.
Ready/Busy: MT
The MT outpu_t signal is used to indicate the operating condition of the device. The R53: signal is in
a blisy state (R/B = L) durin the Program, Erase and Read operations and will return to a ready state
(R/B = H) afrer completion o the operation. The output buffer' for this signal is an open drain.
1998-07-01 14/36
TOSHIBA
TC5816BFT
Schematic Cell Layout and Address Assignment
The program operation is implemented in page units while the erase operation is carried out in block
units.
512 blocks
_______;_____ .______4_
Figure 2. TC5816 Schematic Cell Layout
Table 1. Add ressi ng
A page consists of 264 bytes in which 256 bytes are for
main memory and 8bytes are for redundancy or other uses.
1 Page = 264 bytes
1 Block = 264 bytes X 16 pages = (4K + 128) bytes
Total Device Density = 264 bytes M 16 pages M 512 blocks
= 16.5 Mbits (2.0625 Mbytes)
The address is acquired through the I/O port over
three consecutive clock cycles as shown in Table 1.
l/OI IIO 2 l/O 3 IIO 4 IIO 5 IIO 6 IIO 7 IIO 8
First cycle A0 A1 A2 A3 A4 A5 A6 A7
Second cycle A8 A9 A10 A11 A12 A13 A14 A15
Third cycle A16 A17 A18 A19 A20 * L * L * L
*: |/06 to 8 must be set low in the third cycle.
Operation Mode: Logic and Command Tables
A0 to A7
A8 to A20
\A8 to A11
: column address
: page address
(A12 to A20:
block address )
: NAND address in block
The operation modes such as Program, Erase, Read, Erase Suspend and Reset are controlled by the
eleven different command operations shown in Table 2. The address, command input and data
input/output are controlled by the CLE, ALE, CE, 117Trf, TIT?" and ttrf'' signals, as shown in Table 2.
Table 2. Logic Table
CLE ALE E W E W
Command Input H L L U H *
Data Input L L L _l_/F H *
Address Input L H L U H *
Serial Data Output L L L H U *
During Programming (Busy) * * * * * H
During Erasing (Busy) * * * * * H
Program, Erase Inhibit * * * * * L
H: VIH, L: VIL, *: " or "
TOSHIBA TC5816BFT
Table 3. Command table (HEX data)
FIRST CYCLE SECOND CYCLE AccET),B/d ESW'AND
Serial Data Input 80 -
Read Mode (1) 00 - . .
Read Mode (2) 50 - ?giaanis$lg:)ment of HEX data
Reset FF - C)
Auto Program 10 - Serial data input: 80H
Auto Block Erase 60 D0
Suspend in Erasing BO - O A "h r A "h
Resume Do - |1|0|0|0|0|0|0l0|
Status Read 70 - O l/O8 7 6 5 4 3 2 l/Ol
ID Read 90 -
Once the device is set into Read mode by the "00H" or "50H" command, additional Read
'it,t1a1eahhgie, not needed for sequential page read operations. Table 4 shows the operation states
or ea o e.
Table 4. Read mode operation states
CLE ALE E m E POI to |/08 POWER
Output Select L L L H L Data output Active
Output Deselect L L L H H High impedance Active
Standby L L H H * High impedance Standby
DEVICE OPERATION
Read Mode tl)
Read mode (1) is set by issuing a "00H" command to the command register. Refer to Figure 3
below for timing details and a block diagram.
CLE Cl
c-s-lg/gil/EI/E
ALE_/—\
A data transfer operation from the cell array to the
register starts on the rising edge of W in the third cycle
263 (after the address information has been latched.) The device
will bein Busy state during this transfer period. The E signal
Nc must stay low after the third address input and during Busy
Select page» state.
N Cell, array After the transfer period the device returns to Ready state.
J Serial data can be output synchronously with the E clock
from the starting pointer designated in the address input
Figure 3. Read mode (1) operation cycle.
1998-07-01 16/36
TOSHIBA TC5816BFT
Read Mode 12!
Read mode (2) has the same timing as Read mode (1) but is used to access information in the extra
8-byte redundancy area of the page. The starting pointer is therefore assigned between bytes 256 and
CLE Cl
c-r-l m m m
m UUUU
sus-C/u'-'"'")"),
" m-- CHD-CHD- ........
A0 to A2
255 263
11 V A Addresses A0 to A2 are used to set the starting pointer for
N. the redundant memory cell, while A3 to A7 are ignored.
Once the "50H" command is set, the pointer moves to the
redundant cell locations and only those 8 cells can be addressed,
regardless of the A3 to A7 address.
(The "00H" command is necessary to move the pointer back to
the 0 to 255 the main memory cell locations.)
Figure 4. Output Select (2) operation
Se uential Read (1) (2)
This mode allows sequential reading without the additional address input.
(iiiiirs,
(iiiiiir-" 's-s----" Data output Data output
- Address in ut e--------?:-------, e-------";-----,
RIB -h""'-"'''sn2h' (-hfi-" (-hfi-', i"
Busy Busy Busy
0 fr 263 fr
Sequential Read (1) Sequential Read (2)
Figure 5. Sequential Read operation
Sequential Read mode (1) outputs addresses 0 to 263 while Sequential Read mode (2) outputs
the redundant address locations only. When the pointer reaches the last address, the device
continues to output the last data from this address on each It-E clock signal.
1998-07-01 17/36
TOSHIBA TC5816BFT
Status Read
The TC5816 automatically implements the execution and verification of the Program and Erase
operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine
the pass/fail result of a Program or Erase operation, and determine if the device is in Suspend or
Protect mode. The device status is output through the I/O port using the "rt""t"f" clock after a "70H"
command input. The resulting information is outlined in Table 5.
Table 5. Status output table
STATUS OUTPUT
I/O1 Pass/Fail Pass: "o'' Fail: "l" The Pass/Fail status on l/OI is only valid
" " when the device is in the Ready state.
V02 Not used 0 The device will always indicate Fail Status
l/O3 Not used "0" while in the Busy state in the Program and
Erase operations.
l/O4 Not used "0"
" 5 Not used "o''
|/06 Suspend Suspended: "1" Not Suspended: "o"
l/O? Ready/Busy Ready: "1" Busy: "0"
l/O8 Write Protect Protect: "0" Not Protect: "1"
An application example with multiple devices is shown in Figure 6.
E1 c% G3 CEN CE + 1
ALE Device Device Device Device
WE 2 3 N N+1
HO 1 to 8
" l 70H ) g k (rwi) g k
qStatus on c, Status on
Device 1 Device N
Figure 6. Status Read Timing Application Example
SYSTEM DESIGN NOTE: If the R/IT pin signals of multiple devices are common-wired, as shown in the
diagram, the Status Read Function can be used to determine the status of each individually selected device.
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TOSHIBA TC5816BFT
Auto Page Program
The TC5816 implements the Automatic Page Program operation by receiving a "10H" program
command after the address and data have been input. The sequence of command, address and data
input is shown below. (Refer to the detailed timing chart.)
Data Input Address Data Input Program Status Read
command input 0 to 263 command command
R/E ( f R/E automatically returns to Ready after completion.
Program / , Read &Verification The data is transferred (programmed) from the register to the selected
page on the rising edge of WE following the "10H" command input. After
ls, y programming the programmed data is transferred back to the register to
Selected be automatically verified by the device. If the program does not succeed,
the above Program/Verify operation is repeated by the device until success
is achieved or until the maximum loop number set in the device is
reached.
Figure 7. Auto Page Program Operation
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of W after the Erase start command
"DOH" which follows the Erase Set-Up command "60H". This two-cycle process for Erase operations
acts as an extra layer of protection from accidental erasure of data due to external noise. The device
automatically executes the Erase and Verify operations.
CD Ciii') 70 tttC/i,), Pass
Block address '
input : 2cycles i'
RIB Erase Start Busy Status Read
command command
Figure 8. Auto Block Erase
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TOSHIBA TC5816BFT
Suspend / Resume
Because a Block Erase operation can keep the device in the Busy state for an extended period of
time, the TC5816 has the ability to suspend the Erase operation in order to allow Program or Read
operations to be performed on the device. The block diagram and command sequence for this operation
are shown as below. (Refer to the detailed timing chart)
|:| |:|
Select
Resume command input
Resume the Erase operation
Suspend command
Suspend the
Erase operation
Block address Suspend operation
m ( l t? AN
Figure 9. Suspend/Resume Operation
The CD-CD Suspend/Resume cycle can be repeated up to 20 times duringa Block Erase
operation. After the Resume command has been input, the Erase operation continues from the point at
which it left off and does not have to be restarted.
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TOSHIBA TC5816BFT
The Reset mode stops all operations. For example, in the case of a Program or Erase operation, the
regulated voltage is discharged to 0 volts and the device will go into Wait state.
The address and data register are set as follows after a Reset:
. Address Register .' All "o''
. Data Register .' All "I"
. Operation Mode : Wait State
The response after an "FFH" Reset command input during each operation is as follows:
. When a Reset (FFH) command is input during programming. Figure 10.
(80) ‘10, ,FF, .00,
Internal Vpp , /Nss,,
Register set
tRST (max 20 Mr) i'
A''"'''-'):'
. When a Reset (FFH) command is input during erasing. Figure 11.
( DO ) ( FF , CD-
Internal erase voltage-i..'"------,,
i' i.' Register set i.'
R/E I g ii''''"-"'"':?
tRST (max 500 ss)
. When a Reset (FFH) command is input during a Read operation. Figure 12.
f"7,Css
W ' i." l
iM-F,"
thT (max 10 [15)
. When a Reset (FFH) command is input after Suspend. Figure 13.
a) BO CT'": FF /
5 This Reset cancels Suspend status.
Internal erase vm i.'
R/iT I I " f
tRST (max 10 IMS)
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TOSHIBA TC5816BFT
When a Status Read command (70H) is input after a Reset. Figure 14.
UL'.,,,,,,? V-'''"------------- " status : Pass/ Fail -ypass
- Ready/ Busy -9 Ready
R/B I I
-CD-CD-
' I/O status : Ready/ Busy -9 Busy
When more than one Reset commands are input in succession. Figure 15.
(1) (2) (3)
, 10 _ , FF k , FF _ CD-
'sd2..9 'su.9
The second (CED) command is invalid,
but the third (CED command is valid.
ID READ
The TC5816 contains an ID code to identify the device type and the manufacturer. The ID codes are
read out using the following timing conditions:
CLE l (
tREAID
IIO 90H 00
ID Read command Address "OO" Maker code Device code
Figure 16. ID Read timing
Table 6. Code table
IIO 8 IIO 7 I/O 6 " 5 l/O 4 " 3 IIO 2 IIO 1 HEX DATA
Maker code 1 0 0 1 1 0 0 0 98H
Device code 0 1 1 0 0 1 0 0 64H
Refer to the specifications for the tREAID, tce and tAR1 access timings.
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TOSHIBA TC5816BFT
DEVICE PHYSICS:
Program Operation
Figure 17 shows the NAND memory cell level details of the programming mechanism. The Program
operation is used to write "O" data into an erased memory cell CI'' data cell) using a tunneling
mechanism. An example Program operation to program "o" data into TRI and "I'' data into TR2 is as
follows:
(1) A high level is applied to Select line 1 and a low level is applied to Select line 2 so that the
device is connected to the Bit line and disconnected from the ground line.
(2) Vpp (ras 20V) is applied to the selected word line and an inhibit voltage of VPI (a 10 V) is
applied to the unselected word lines.
(3) 0 volts is applied to the bit line tied to cell transistor TRI and the inhibit voltage VDPI
(ra 10 V) is applied to the bit line tied to TR2.
(4) Vpp is applied between the control gate and the channel in TRI, as shown in Figure 18, which
causes electrons to be injected from the channel to the floating gate by a tunneling mechanism.
(5) The injected electrons are captured in the floating gate surrounded by an oxide layer and will
remain, even after power is cut off, until they are removed by an Erase operation.
(6) Although 20 volts is applied to the control gate of TR2, the voltage difference between the
control gate and the channel is only 10V because the voltage of the channel is 10 V. Therefore,
tunneling does not take place (i.e. the electron is not injected into the floating gate.)
(7) Tunneling does not take place in the unselected pages because of the 10V (VPI) applied to the
unselected word lines which makes the voltage difference between the control gate and channel
only 10 volts.
Thus the floating gate of the "o" cell is charged to "Minus" and that of the "I'' cell is charged
to "Plus".
Vpp}? Bit line VDPI (rr. 10V) TRI V ( 20 V)
PP 'tt
Select line 1 f 1 i
(:10V) VPI L": L.“ (Word line 1) [a
VPI E: riii (Word line 2) I 0V
VPI H H (Word line 3)
(re. 20 V) VPP tii) tii)- (Word line 4) N
VPI TR1 :H TR2 :1: (Word line 5)
VPI E:' El.“ (Word line 6)
VPI E.” Jr:',", (Word line 7) TR2 Vpp (a 20 V)
VPI r.” Pl (Word. line 8)
s L, L, i' . Ll,
VPl ll H (Word line 16)
Select line 2 7E.) j) T, VDPl(=10V)
Select line 1 t t
I-rl-!
Figure 17. TC5816 Program Device Physics
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TOSHIBA TC5816BFT
Erase Operation
Figure 18 shows the NAND memory cell level details of the Erase mechanism. The Erase operation
is used to turn the "o'' (programmed) cells back to "l" in a block. The captured electrons are pulled
out from the floating gate to the substrate by a tunneling mechanism. 0 volts is applied to the control
gate and Vpp (sas 20V) is applied to the substrate so that a 20-volt potential is created and the
electrons in the floating gate are pulled out by the tunneling mechanism.
open open
we---''"" Bit line 'ss
Select line
16word lines 0V
(1 block)
I-'open
VPP (= 20 V)
Select line
Vpp (a 20V) Vpp (rs 20V)
Figure 18. TC5816 Erase Device Physics
Read Operation
After programming the state of the memory cell is either Threshold " "
"o" (minus charge on the floating gate) or "I'' (plus charge on value 0 Data cell
. . . . V ) VTH
the floating gate). Each state IS indicated as the "threshold ( TH Distribution
voltage (Vth)" which is a characterization parameter of the +
MOS transistor as shown in Figure 19. The threshold voltage
of a transistor with data "O" is distributed in the "plus"
region while a transistor with data "I" is distributed in the 0
"minus" region. The distribution band depends on the
fluctuation of the transistor. "1" Data cell
Distribution
Figure 19. VTH Distribution for "0" and "I" data cells
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TOSHIBA TC5816BFT
Figure 20 shows memory cell level details of the Read operation mechanism:
(1) A high voltage is applied to Select lines 1 and 2 in the block which includes the selected page,
so that the 16 NAND memory cells are connected to the Bit line and ground.
(2) 0 volts is applied to the control gates of the selected page and a high level voltage is applied
to the control gates of the unselected pages.
(3) In Figure 20, transistor TR2 with data "I'' turns on, transistor TR1 with data "O'' turns off,
and all other unselected transistors turn on.
(4) The precharged bit line tied to TR2 is discharged through TR2 as cell current flows to ground,
while the precharged bit line tied to TR1 remains high because current does not flow. The sense
amplifiers tied to the bit lines thus sense the voltage levels as "I" and "O'' respectively.
-" Bit line 's,
Select line 1
t ON t ON
H L}. ON -, C-w, ON
H :H ON E‘H ON
H fire: El.” ON
"o" Eh,'" "I"
Selected page L H ll
H TR1 tfif fi,'] TR2 tii-fell
H q'',, ON E'H ON
H Eh,",, ON q; ON
H 5:: ON 5:: ON
H Ian ON IE}: ON
Select line 2 l A 5
g' ON r----" gl ON
Cell current
Figure 20. TC5816 Read Device Physics
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TOSHIBA TC5816BFT
APPLICATION NOTES AND COMMENTS
(1) Prohibition of unspecified commands
The operation commands are listed in Table 3. Data input as a command other than the specified
commands in Table 3 is prohibited. Stored data may be corrupted if an unspecified command is
entered during the command cycle.
(2) Pointer control for "00H", "50H"
The TC5816 has two Read modes to set the destination of the pointer in either the main memory
area of a page or the redundancy area. The pointer can be designated at any location from 0 to 255
in Read mode (1) and from 256 to 263 in Read mode (2). Figure 21 shows a block diagram of the
modes' operations.
0 255 256 263
00H _ .
50H _ Pointer control Figure 21. Pointer control
The pointer is set to region "A" by the "00H" command and to region "B" by the "50H" command.
(Example)
The "00H" command needs to be input to set the pointer back to region "A'' when the pointer is
in region "B".
00H , 50H k , 80H '
"s-------------" vc'-'.'?-,- s------------).',".'...'-''" "-v--'
Address Start point Address Start point Address DlN
A area B area
Start point
fTCts fC7Cts f7,7Cs B area
00H 50H 00H 80H
's-v-" c-v-NCCU"---
Address l Address l Address I Address D
Start point Start point Start point Start point
A area B area A area A area
Figure 22. Example for Pointer Set
If the start point is set in region "B" using the "50H" command, so as to program region "B"
only, the contents of the data resister must be set to "l" in advance using the "FFH" command.
(FFH) , H, , H, _ . 1 H
50 80 0
Address D
Start point
B area
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TOSHIBA TC5816BFT
(3) Acceptable commands after Serial Input command "80H"
Once the Serial Input command ("80H") has been input, do not input any command other than
the Program Execution command ("10H") or the Reset command ("FFH") during programming.
CiD Q?
m -1luliC1u .
"s-s..---"
Address 5
Internal Vpp input I i' 'ts
R/E l I
Figure 23.
If a command other than "10H" or ''FFH'' is input, the Program operation is not performed.
For this operation,
Other command Programming cannot be executed. the "FFH" command is needed.
(4) Status Read during a Read operation
Command CD
a -I EI l
WE Ll \-,ph-l\-l
MT l ' I
E I l l L/N/T ......
Address N Status _-l,
Read command Status Status output
input Read
Figure 24.
The device status can be read out by inputting the Status Read command "70H" in Read mode.
Once the device has been set to Status Read mode by a "70H" command, the device will not return to
Read mode.
Therefore, Status Read during a Read operation is prohibited.
However, when the Read command ''00H" is input during [A], Status mode is reset and then the device
returns to Read mode. In this case, data output starts from address N without the need for address input.
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TOSHIBA TC5816BFT
(5) Suspend command "BOH"
The following issues need to be observed when the device is interrupted by a "BOH" command
during block erasing.
ftio', 'DO', fBo', f70',
Recovery time (tSR)
Figure 25.
The device status changes from Busy to Ready when "BOH" is input. However, the following two cases
cannot be distinguished from one another.
- After a "B0H" command input, Busy-' Ready
- After an Erase operation is completed with a "DOH" command, Busy- Ready
Therefore, the device status needs to be checked to see whether or not the "BOH" command has been
accepted by issuing a "70H" command after the device goes to Ready.
The device responds as follows when a "DOH" command (Resume) is input instead of "70H".
- "BOB'' has been accepted
Erase operation is executed. (The device is Busy.)
- "BOH" has not been accepted. (Erase operation has been completed)
"DOH" command cannot be accepted. (The device is Ready.)
The two cases above can be checked by monitoring the MT signal.
(6) When auto programming fails.
80 10 70 HO 80 10
(Ciiiiy_, s-.-Nd-o.-M kd.':--'"-.,--- s-ISL",,-.'
Address Data Address Data
M input N input
If the programming result for page address M is "Fail", do not try to program the page to
address N in another block. Because the previous input data is lost, the same sequence of
"80H" command, address and data input is necessary.
Figure 26.
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TOSHIBA TC5816BFT
(7) Data transfer
The data in page address M cannot be automatically tranferred to page address N. If the
following sequence is executed, the data will be inverted. (i.e. "I'' data will become "o" and "o'' will
become "I''.)
(00} C80', f10', C70',
Address Address
M N Program
Inverted data will be transferred.
Figure 27.
(8) Block Erase After Suspend command "BOH"
-tCiiD ' D0 _ ' BO _ ' 60 E
address Erase Start Suspend I
A Block Erase command is prohibited when the device has
been suspended by the input of a "BOH" command during a
Block Erase operation. Only a Program or Read operation is
allowed during this Erase Suspend interruption.
(9) Interruption of block erasure
After the input of a "BOB" command, neither a Program nor a Read operation is allowed for the
block which is currently being erased.
60 V\ DO ' , BO "s----------,.-------------" D0
address
Interruption of block A is prohibited.
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TOSHIBA TC5816BFT
(10) Rm.. Termination for the Ready/Busy pin (R/B)
A pull-up resistor must be used for termination because the R/g buffer consists of an open drain
circuit.
CC Ready
J Vcc R . . .
De ice - 5 : B s . 3
VI -1- R/B i E U y T, 3 E
" I CL '..' i . I
Vcc = 5.0V
V53 1.5 ps Ta = 25°C 15 ns
CL = 100 pF
Fi 28 t
Igure . t, 1.0 pS 10 ns tf
This data may vary from device to device. 05/15 5 ns
We recommend that you use this data as a 2
reference when selecting a resistor value. I I I I
0 llG2 2kn 3kn 4KQ
(11) Status after Power On
Although the device is set to Read mode after power-up, the following sequence is needed because
all input signals may not be stable at power on.
Operating mode .' Read mode (1)
Address register : All "o''
Data register : Indeterminate
High voltage generation circuit: Off state
Power on sequence
Power on ( FF ', ( oo ',
Reset Read mode (1)
(12) Power On/Off Sequence:
The Tirp signal is useful for protecting against data corruption at power on/off. The following
timing is recommended:
4.5 V: C
VIL i' i' VIL
::u- . -r:..'
' Operation .
Figure 29. TC5816 Power On/Off Sequence
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TOSHIBA TC5816BFT
(13) Note regarding the T1rrl Signal
The Erase and Program operations are automatically reset when W15 goes low. The T7P signal
must be kept high before the input of a "80H''/"60H" command, the Program and Erase commands.
If Wgoes high after a Program ("80H") or Erase ("60H") command, the Program or Erase
operation cannot be guaranteed.
Program
tww (min 100 ns)
Figure 30.
WF ........ -
WW ........ -l_/-
-I-i- .........
R/B l l
tww (min 100 ns)
Figure 31.
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TOSHIBA TC5816BFT
(14) When four address cycles are input
Although the device may acquire the fourth address, it is ignored inside the chip.
Read ogeration
ALE ( )
vo-(E)y-( H H {—
Address input ignored
Internal read operation starts when m goes high in the third cycle.
Figure 32.
Programming ogeration
vo-er-ily-t H H H H H H Y--
"s--------------" "s--------------"
Address input 1 Data input
ignored
Figure 33.
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TOSHIBA TC5816BFT
(15) Number of programming cycle on the same page (Partial Page Program)
A page can be divided into up to 10 segments. Each segment can be programmed individually as
shown below.
The first programming Data pattern1
The second programmin
f pattern 2
Data pattern 10
The tenth programming
Result Data pattern] M........................................................ Data pattern 10
pattern 2
Figure 34.
Note: The input data for unprogrammed or previously programmed page segments must be
(i.e. Set all page bytes outside the segment to be programmed to "1".)
(16) Note regarding the R-E Signal
The internal column address counter is incremented synchronously with the Rl"?" clock in Read
mode. Therefore, once the device has been set to Read mode by the "00H" or "50H" command, the
internal column address counter is incremented by the It-E clock independent of the timing of the
address input. If the It-E clocks are input before address input and the pointer reaches the last
column address, an internal read operation (array-' register) will occur and the device will be in the
Busy state. (Refer to Figure 35.)
Address input
Figure 35.
Hence, the "tTh")" clocks must be input after address input.
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TOSHIBA TC5816BFT
(17) Invalid block (bad block)
The TC5816 device occasionally contains unusable blocks. Therefore, the following issues must be
recognized:
Check whether the device has any bad blocks after installation of the
device in the system. Do not try to access bad blocks. A bad block does
-> Bad Block not affect the performance of good blocks as it is isolated from the Bit
line by the Select gate. Valid numbers of blocks are as follows:
MIN TYP MAX UNIT
Valid Good Block Number 502 508 512 Block
- Bad Block
Figure 36 shows the bad block test flow.
(18) Failure Phenomena for Program and Erase Operations.
The device may fail during program or erase operation.
The following possible failure modes should be considered when implementing a highly reliable
system.
FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE
Block Erase Failure Status Read after Erase -9 Block Replacement
Page Program Failure Status Read after Prog. - Block Replacement
Single Bit* Program Failure (1) Block Verify after Prog. -9 Retry
'I'-y'0' (2) ECC
* : (1) or (2)
o ECC : Error Correcting code - Hamming Code etc.
Example '. 1 bit correction & 2bit detection.
It Block Replacement
Program
error occurs
When an error happens in Block A, try to
Buffer
memory
reprogram the data into another (Block B) by
1 Block A loading from an external buffer. Then, prevent
further system accesses to Block A ( by creating
a 'bad block' table or an another appropriate
Block B scheme.)
When an error occurs for an erase operation, prevent future accesses to this bad block
(again by creating a table within the system or other appropriate scheme).
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TOSHIBA TC5816BFT
BAD BLOCK TEST FLOW
f .' Checker board pattern
C : Inverted checker board pattern
Blank Check Pass Blank check : 1 Block read (FFH)
Bad Block
BNo.=BNo.+1l-
rau-:-crriiCiflEiici-N-o
Block No = 1
C-PattProc
Read (00H) Fail
Pass BNO. = BNo.+1li-
Block Fail No
Erase Bad
Pass . Block B No. = 512
6 Page Fail
IC-Patt Prog Yes
Read (00H) Fail
Block Fail
B No. = 512
Test End
Figure 36.
1998-07-01 35/36
TOSHIBA TC5816BFT
PACKAGE DIMENSIONS
Plastic TSOP
TSOP If 44/40 -P - 400 - 0.80B
UNITS: mm
44 35 32 23
HHHHHHHHHH HHHHHHHHHH1 " d
10.16i0.1
11.76.'*;0.2
HHHHH HHH HHHHHHHHHH L "sl
1 10 13 22
0.805TYe A 0'3i0'05"
" 18.81MAX
, , r. yet
L 18.41t0.1 _ $3. g ‘48.
1998-07-01 36/36
www.ic-phoenix.com
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