TC55WD818FF-150 ,524,288-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
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TC55WD818FF-150
524,288-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
TOSHIBA TC55WD818FF-133,-150,-167
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
DESCRIPTION
The TC55WD818FF is a synchronous static random access memory(SRAM) organized as 524,288 words by 18
bits. NtRAMTM(no-turnaround) SRAM offers high bandwidth by e1iminating_dead cycles during the
transition from a read to a write and vice versa. All inputs except Output Enable OE and the Snooze pin ZZ
are synchronized with the rising edge of the CLK input. A Read operation is initiated b the ADV Address
Advanced Input signal ; the input from the address Fins and all control pins except the E and ZZ pins are
loaded into the internal registers on the rising edge 0 CLK in the cycle in which ADV is asserted. The output
data is available two clock c cles later. Write operations are internally self-timed and are initiated bly the
rising edgesfCLK in the eye e in which ADV is asserted. The input from' the address pins and all contro pins
except the OE and ZZ pins are loaded into the internal registers on the rising edge of CLK in the cycle in which
ADV is asserted. In ut data is loaded in the third cycle after the cycle in which ADV is asserted. Byte Write
Enables(BW1 to BW2) allow from one to four Byte Write operations to be performed. A 2-bit burst address
counter and control logic are integrated into this SRAM. The TC55WD818FF uses a single power supply
(2.5V) and is available in a 100-pin low-profile plastic QFP(LQFP).
FEATURES
o Organized as 524 288 wor.ds. by 18 bits '
0 Fast cycle tupe Jt 6ns minimipn(16'r MHz maximum)
0 Fast access time of 3.5 ns n.wriny1T.(fror,n clock edge to data output)
0 yty.ty,rnarpun,d, operation with pipelipe data output .
o 2-bit burst address cou,nttr.(surip6rt for interleaved or linear burst sequences)
0 giorryely:y.1pus self-timed Write
0 Byte Write control
0 Snooze mode pin(ZZ) for power down
0 I.e.VTTL-cornpitible interfice
0 Single power yyop.ly (2.5 V) . . .
0 Available in 100-p1n LQFP package (LQFPlOO-P-1420-0.65K ; p1tch:0.65 mm, height:1.6 mm, weight:0.56
grams(typica1))
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
CLK Clock Input
A0 to A18 Address Inputs
99 7 95 93 91 89 87 85 83 81 CE,CE_2, CE2 Chip Enable Inputs
NE i? £698 96 94 92 90 88 86 84 82 tll? @333 E Output Enable
VDSS 431 $9... vSDQ WE Write Enable Input
V55? Et g g: KSCSQ BW1 to BW2 Byte Write Enable
NC EE 7 74 IE I/O9
1/010 EE 8 73 II l/O8 ADV Address Advance Input
l/O11 -rr 9 72 --- l/OT -
vsso --- 10 71 --- vsso CKE Clock Enable
123283211; €833 iiBEQ 22 s I t
"11:32:12 292219: nooze npu
VDD s,':,': 15 66:: VDD l/OI to I/O18 Data Inputs/Outputs
Ig? ... 1‘75 22... ‘2’? MODE Mode Select Input
£380]? tt 1% E? I: :6ng NC Not Connected
vssé 21 eo--- vssoQ NU Not Usable
l/OI 22 59 " l/O2
1/017 " 23 58 " l/OI VDD Power Supply for Core
"o/tal,' 33:: “E V P s I f o t t B ff
VSSQrzR26 55... VSS DDQ ower uppy or u pu u er
"E g; 33:: XED Vss Ground for Core
“E I: 'il 32 34 36 38 40 42 44 46 48 503% (,e lf VSSQ Ground for Output Buffer
31 33 35 37 39 41 43 45 47 49
tllflflflllllflflflflllllflflflflllllflf Note: NtRAMTM and No-Turnaround Random Access Memory are trademarks
2gtns;tt--C_tt2uJu)ti-Cutns;ttfyur ' . . .
CY<<<<<
fl >> <<<<<<< supported by Samsung and NEC.
000707EBA2
O TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction
or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizin TOSHIBA
products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a mal unction or
failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent
TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor
Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
0 The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office
equipment, measurina equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for
usage in equipment t at requires extraordinarily high quality and/or reliability or a malfunction or failure of which m.ay cause loss of human life or
bodily injury CUnintended Usage"). Unintended Usage include atomic ener y control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, me ical instruments, all types of safety devices, etc.. Unintended Usage of
TOSHIBA products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the ap lications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
2002-09-20 1/18
TOSHIBA
BLOCK DIAGRAM
TC55VVD
818FF-133,-150,-167
Memory
Cell Array
512 K x 18 bits
(9,437,184 bits)
" >,EOutput Register
Din Register 2
A0 to lfl _
A18 . Address _
E Register l? /A1
F Binary
MODE Cou.nter. and
Address Address
Register 1 Register 2
_ADV ' Read/Write "
BW1 to k .
BW2 " Control Logic &
W , Coherency
. Control Logic
til-Jia)-
, Din Register)
rnn'l n
NN l'|'|
-; Data-Out Control
2002-09-20 2/18
TOSHIBA
TC55WD818FF-133,-150,-167
PIN DESCRIPTIONS
PIN NUMBER SYMBOL TYPE DESCRIPTION
89 CLK Input Clock Input
(NA) All synchronous input signals are registered on
the rising edge of CLK. When the chip is
enabled, address inputs and control pins except
for E and 22 must meet the specified setup
and hold times with respect to the CLK rising
37, 36, 35, 34, 33, 32, A0 to A18 Input Address Inputs
100, 99,82, 81, 44, 45, (synchronous) These address inputs are registered on the rising
46, 47, 48, 49, 50, 83, 80 edge of CLK. When the chip is enabled,
address inputs must meet the specified setup
and hold times with respect to the CLK rising
98 E Input Chip Enable Input
(synchronous) This active-Low signal controls the chip status
(enabled or disabled). It is sampled only when
a new external address is loaded.
92 m Input Chip Enable Input
(synchronous) This active-Low signal controls the chip status
(enabled or disabled). It is sampled only when
a new external address is loaded.
97 CE2 Input Chip Enable Input
(synchronous) This active-high signal controls the chip status
(enabled or disabled). It is sampled only when
a new external address is loaded.
86 a Input Output Enable Input
(asynchronous) This active-Low signal controls all 18 bits of the
" output buffer.
88 W Input Write Enable Input
(synchronous) This active-Low input controls Read/Write
operations.
93, 94 W to m Input Byte Write Enable
(synchronous) These active-Low inputs control Byte Write
operations when a Write cycle is active. A Byte
Write pin controls l/O pins as follows.
B)/j1:I/O1 to |/09
Wn/ow to |/O18
85 ADV Input Address Advance Input
(synchronous) This is used to load the internal registers with
the input from the address and control signals
when it is Low on the rising edge of CLK.
When it is High, the internal burst address
counter is incremented. The external address
inputs are ignored when this signal is High.
87 m Input Clock Enable
(synchronous) When High, CLK input is ignored and outputs
retain the same state.
2002-09-20 3/18
TOSHIBA
TC55WD818FF-133,-150,-167
PIN NUMBER SYMBOL TYPE DESCRIPTION
64 22 Input Snooze Input
(asynchronous) This active-High signal is used to place the
device into Sleep Mode(Low-Power Standby
Mode). When Low, the device remains in the
Active state. When High, the device goes into
the Sleep state and memory data is retained.
After this signal has been de-asserted, the
device will wake up when a read or write
operation is initiated by ADV.
58, 59, 62, 63, 68, 69, 72, l/OI to |/O18 IIO Data Input/Output
73, 74, 8, 9, 12, 13, 18, 19, (synchronous)
22, 23, 24
31 MODE Input Mode Select Input
(synchronous) This signal selects the burst sequence. When
High, the burst sequence is interleaved. When
Low, it is linear.
l, 2, 3, 6, 7, 25, 28, 29, 30, NC NC Not Connected
39, 42, 43, 51, 52, 53, 56,
57, 75, 78, 79, 84, 95, 96
38 NU Input Not Usable
(asynchronous)
14,15,16, 41, 65, 66, 91 VDD Supply Power Supply for Core
4, 11, 20, 27,54, 61, VDDQ Supply Power Supply for Output Buffers
70, 77
17, 40, 67, 90 Vss Ground Ground for Core
5, 10, 21, 26, 55, 60, VSSQ Ground Ground for Output Buffers
2002-09-20 4/18
TOSHIBA TC55WD818FF-133,-150,-167
OPERATING MODE
(1) Synchronous Input Truth Table
OPERATION m ADV CE W Addr. Used m 22 (2 cycllé?|ater)
Read (begin burst) H L Select x External L L Output
Read (continue bu rst) x H x x Internal L L Output
Write (begin burst) L L Select L External L L Input
Write (continue burst) x H x L Internal L L Input
NOPNVrite Abort (begin burst) L L Select H x L L Hi-Z
Write Abort (conti nue bu rst) x H x H Internal L L Hi-Z
Deselected x L Deselect x x L L Hi-Z
Deselect Continue (Note 2) x H x x x L L Hi-Z
Ignore Clock Edge (Note 3) x x x x x H L Previous value
Snooze x x x x x x H Hi-Z
Notes: 1. H means logical High and L means logical Low. X means Don't care.
2. A Deselect Continue cycle can only be entered if a Deselect cycle is executed before it.
3. When the Ignore Clock Edge command is asserted during a Read operation, the out ut data
for the prev1ous cycle still appear on the I/O pins. When the command is asserted uring a
Write operation, the I/O pins remain at Hi-Z and the Write operation is not executed.
4. All synchronous Inputs must exhibit adequate setup and hold times either side of the rising
edge of the CLK pin.
5. ZZ input is asynchronous, but is included in this table.
(2) Write Enable Truth Table
OPERATION B 1 B 2 l/OI to IIO9 l/O10to |/O18
Output Output
Input Input
Input Hi-Z
Hi-Z Input
H H Hi-Z Hi-Z
Notes: 1. H means logical High and L means logical Low. X means Don't care.
2. The status for I/O pins described in this column appears two clock cycles after the cycle in
which the Read or Write command is asserted.
(3) Asynchronous Inputs Truth Table
OPERATION E I/O
Read Dout
Write Din, Hi-Z
Stop clock (Note 2) Hi-Z
Notes: 1. H means logical High and L means logical Low. X means Don't care.
2. The Stop CLK Mode achieves Low-Power Standby by stopping the input clock.
3. The Snooze Mode achieves Low-Power Standby by asserting the ZZ pin.
The cycle immediately prior to a snooze brought about by the ZZ pin must be a Read Mode or
Deselect Mode cycle.
5. Memory data is retained during Snooze Mode cycles.
(4) Burst Sequence
MODE PIN BURST OPERATION
L Linear burst order
H or NC Interleaved burst order
2002-09-20 5/18
TOSHIBA TC55WD818FF-133,-150,-167
a) Linear Burst Sequence (MODE input=Vss)
Bit Order: A18, .................. A1, A0
1st Address 2nd Address 3rd Address 4th Address
(external) (internal) (internal) (internal)
xx ...... xxoo xx ...... XX01 XX ...... XX10 XX ...... XXI 1
xx ...... XX01 xx ...... XX10 XX ...... XXI 1 xx ...... xxoo
xx ...... XX10 xx ...... XXI 1 XX ...... xxoo XX ...... XX01
xx ...... XXI 1 xx ...... xxoo xx ...... XX01 XX ...... XX10
b) Interleaved Burst Sequence (MODE input=VDD or NC)
Bit Order: A18 ................... A1, A0
1st Address 2nd Address 3rd Address 4th Address
(external) (internal) (internal) (internal)
XX ...... xxoo xx _..... XX01 XX ...... XX10 XX ...... XXI 1
xx ...... XX01 xx ...... xxoo XX ...... XXI 1 XX ...... XX10
xx ...... XX10 xx ...... XXI 1 xx ...... xxoo XX ...... XX01
XX ...... XXI 1 XX ...... XX10 XX ...... XX01 XX ...... xxoo
DEVICE OPERATION
(1) Read Operation
CYCLE ADDRESS m BW ADV E E m " OPERATION
n A0 H x L L x L x Address & control valid
n + 1 x x x x x x L x
n + 2 x x x x x L x Q0 Read out A0
Note 1: H means logical High and L means logical Low. X means Don't care. a is data output.
(2) Burst Read Operation
CYCLE ADDRESS " W ADV E E m 1/0 OPERATION
n A0 H x L L x L x Address & control valid
n + 1 x x x H x x L x
n + 2 x x x H x L L Q0 Read out A0
n+3 x x M H x L L QO+1 Read outA0+1
n+4 x x H x L L QO+2 Read outA0+2
n+5 A1 H x L L L QO+3 Read out A0+3
n + 6 x x x H x L L Q0 Read out A0
n + 7 x x x H x L L Q1 Read out A1
n+8 A2 H M L L L L Q1+1 Read out A1+1
n+9 A3 H x L L L L Q1+2 Read out A1+2
n + 10 x x x x x L L Q2 Read out A2
Note I: H means logical High and L means logical Low. X means Don't care. a is data output.
2002-09-20 6/18
TOSHIBA
(3) Write Operation
TC55WD818FF-133,-150,-167
CYCLE ADDRESS W W ADV E E CKE I/O OPERATION
n A0 L L L x L x Address & control valid
n + 1 x x x x x x L x
n + 2 x x x x x x L D0 Write to A0
Note I: H means logical High and L means logical Low.
(4) Burst Write Operation
CYCLE ADDRESS
n+10 X
Note 1: H means logical High and L means logical Low.
r—I—III—IIIII—
(5) Read Operation with Clock Enable
X means Don't care. D is data input.
OPERATION
Address & control valid
Write A0
Write A0 + 1
Write A0 + 2
Write A0 + 3
Write A0
Write A1
Write A1 + 1
Write A1 + 2
L D2 Write A2
X means Don't care. D is data input.
CYCLE ADDRESS " Bt/it ADV E E m PO OPERATION
n A0 H x L L x L x Address & control valid
n +1 x x x x x x H x Ignore cycle
n+2 A1 H x L x L x Address & control valid
n+3 x x x x x L H Q0 Ignore clock, Q0 is on bus
n+4 x x x x x L H Q0 Ignore clock, Q0 is on bus
n + 5 A2 H x L L L L Q0 Read out A0
n + 6 A3 H x L L L L Q1 Read out A1
n + 7 x x x x x L L Q2 Read out A2
Note 1: H means logical High and L means logical Low. X means Don't care. Q is data output.
2002-09-20 7/18
TOSHIBA
(6) Write Operation with Clock Enable
TC55WD818FF-133,-150,-167
CYCLE ADDRESS 1tVE W ADV E E m I/O OPERATION
n A0 L L L L x L x Address & control valid
n +1 x x x x x x H x Ignore clock
n+2 A1 L L x L x Address & control valid
n + 3 x x x x x x H x Ignore clock
n + 4 x x M x x x H x Ignore clock
n + 5 A2 L L L L x L D0 Address & control valid
n + 6 A3 L L L L x L D1 Write A1
n + 7 x x x x x x L D2 Write A2
Note I: H means logical High and L means logical Low. X means Don't care. D is data input.
(7) Read Operation with Chip Enable
CYCLE ADDRESS W W ADV E E m I/O OPERATION
n A0 H x L L x L x Address & control valid
n + 1 x x x L H x L x Deselect
n + 2 A1 x L L L L QO Read A0
n + 3 x x x L H x L 2 Deselect
n + 4 x x M L H L L Q1 Read A1
n + 5 A2 H x L L x L 2 Deselect
n + 6 x x x L H x L 2 Deselect
n + 7 x x x L H L L Q2 Read A2
Note I: H means logical High and L means logical Low. M means Don't care. Q is data output.
Z means Hi-Z.
(8) Write Operation with Chip Enable
CYCLE ADDRESS " W ADV E o-E W I/O OPERATION
n A0 L L L L x L x Address & control valid
n + 1 x x x L H x L x Deselect
n + 2 A1 L L L x L DO Write A0
n + 3 x x x L H x L 2 Deselect
n + 4 x x x L H x L D1 Write A1
n + 5 A2 L L L L x L 2 Deselect
n + 6 x x x L H x L 2 Deselect
n + 7 x x M L H x L D2 Write A2
Note I: H means logical High and L means logical Low. X means Don't care. D is data input.
Z means Hi-Z.
2002-09-20 8/18
TOSHIBA TC55WD818FF-133,-150,-167
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage -0.5 to 3.6 V
VDDQ Output Buffer Power Supply Voltage - 0.5 to VDD+ 0.5 (S3.6V max) V
" Input Terminal Voltage -0.5* to 3.6 V
VI/o Input/Output Terminal Voltage - 0.5 * to VDDQ + 0.5** (E 3.6V max) V
PD Power Dissipation 1.5 W
Tsolder Soldering Temperature(10s) 260 ''C
Tstrg Storage Temperature -65 to 150 "C
Topr Operating Temperature - 10 to 85 ''C
*: -1.0V with a pulse width of 20% of th(min) (3 ns max)
**: Vmoa+ 1.0V with a pulse width of 20% of th(min) (3 ns max)
RECOMMENDED DC OPERATING CONDITIONS(Ta=O to 70°C)
SYMBOL PARAMETER MIN TYP. MAX UNIT
VDD Power Supply Voltage 2.375 2.5 2.625 V
VDDQ Output Buffer Power Supply Voltage 2.375 2.5 2.625 V
VlH Input High Voltage 1.7 - VDD + 0.3** V
Nhril Input High Voltage for MODE pin VDD-0.3 VDD VDD+O.3 V
" Input Low Voltage - 0.3 * - 0.7 V
V|L1 Input Low Voltage for MODE and NU pins -0.3 0.0 0.3 V
*: -0.7V with a pulse width of 20% of th(min) (3 ns max)
**: VDDQ+0.7V with a pulse width of 20% of th(min) (3 ns max)
Note: NU pin must be low or not connected.
You must not apply a voltage of more than 0.7V to the NU.
2002-09-20 9/18
TOSHIBA TC55WD818FF-133,-150,-167
DC CHARACTERISTICS (Ta = o to 70°C, VDD = VDDQ = 2.5 v i 5%)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP. MAX UNIT
IIL Input Leakage Current VIN = 0 to VDD - 1 - 1 PA
Input Current
I V = V . V - 1 - 1 A
NU (NU pin) IN 0 to 0.3 Al
I O t t L k C t Device Deselected or Output Deselected, 1 1 A
LO u pu ea age urren VOUT=0 to VDDQ - - ,u
. IOH = - 1 mA 2.0 - -
VOH Output High Voltage
IOH = - 100 prA VDDQ - 0.2 - - V
IOL-- 1 mA - - 0.4
VOL Output Low Voltage
IOL = 100 PA - - 0.2
167MHz - - 350
I =0mA, all in uts=V -0.2V/0.2V
IDD01 Operating Current OUT p DD 150MHz - - 330 mA
Cl kit .
oc Kc(min) 133MHz - - 310
C) . C Device Deselected 167MHz - - 150
eratin urrent .
IDDOZ 'il', ) g IOUT=0mA, all inputs=VDo-0.2 V/0.2V 150MHz - - 140 mA
Clock2tkc(min) 133MHz - - 130
St n C ent .
|DDS1 a dby urr Clock=Vss, all mputs=VlH or Ihr. - - 60 mA
(TTL level)
Standb Current
'DDSZ y Clock = vss, all inputs = VDD - 0.2 V or 0.2 V - - 10 mA
(MOS level)
22; VDD - 0.2 v
1,3053 5:3”de surge“ all inputs=VDo-0.2V or 0.2V - - 10 mA
( nooze ty e) Clock2te:c(min)
CKEzle
Standb C rrent
1.3.354 m f, d” All inputs=VDD- 0.2V or 0.2V - - 10 mA
( o e) Clock2tkc(min)
Note: Operating Current(IDD01) is specified with 50% Read cycles and 50% Write cycles.
CAPACITANCE (Ta = 25°C, f= 1.0 MHz)
SYMBOL PARAMETER TEST CONDITIONS MAX UNIT
CIN Input Capacitance VIN = GND 5 pF
CI/O Input/Output Capacitance VI/O = GND 7 pF
CNU Input Capacitance of NU VIN=GND 10 pF
Note: This parameter is sampled periodically and is not tested for every device.
2002-09-20 10/18
TOSHIBA TC55WD818FF-133,-150,-167
AC CHARACTERISTICS (Ta = o to 70°C, VDD = VDDQ = 2.5 v , 5%)
SYMBOL PARAMETER TC55WD818FF-167 TC55WD818FF-150 TC55WD818FF-133 UNIT
MIN MAX MIN MAX MIN MAX
ha: CLK Cycle Time 6 - 6.6 - 7.5 -
tKH CLK High Pulse Width 2 - 2 - 2.3 -
tKL CLK Low Pulse Width 2 - 2 - 2.3 -
tKQV CLK High to Output Valid - 3.5 - 3.8 - 4.2
tKQX CLK High to Output Invalid 1 - 1 - 1 -
tKQLZ CLK High to Output Low-Z 1.5 - 1.5 - 1.5 -
tKQHZ CLK High to Output High-Z 1.5 3 1.5 3 1.5 3
teov E Low to Output Valid - 3.5 - 3.8 - 4.2
tGQLZ E Low to Output Low-Z 0 - 0 - 0 -
tGQHZ tN High to Output High-Z 1.5 4 1.5 4 1.5 4.2
tas Address Setup Time from CLK 1.5 - 2 - 2 -
tos Data Setup Time from CLK 1.5 - 1 5 - 1 7 -
tws W Setup Time from CLK 1.5 - 2 - 2 -
tCES CE Setup Time from CLK 1.5 - 2 - 2 -
tADVS ADV Setup Time from CLK 1.5 - 2 - 2 - ns
ths W Setup Time from CLK 1.5 - 2 - 2 -
tCKES m Setup Time from CLK 1.5 - 2 - 2 -
tAH Address Hold Time from CLK 0.5 - 0.5 - 0.5 -
tDH Data Hold Time from CLK 0.5 - 0.5 - 0.5 -
tWH W Hold Time from CLK 0.5 - 0.5 - 0.5 -
tCEH CE Hold Time from CLK 0.5 - 0.5 - 0.5 -
tADVH ADV Hold Time from CLK 0.5 - 0.5 - 0.5 -
tBWH W Hold Time from CLK 0.5 - 0.5 - 0.5 -
tCKEH m Hold Time from CLK 0.5 - 0.5 - 0.5 -
tzz 22 High to Input Ignored 0 Zth 0 Zth 0 Zth
tZZR 22 Low to Input Sampled 0 2th 0 2th 0 2th
tZZHZ 22 High to Output High-Z o 2th o 2th o 2th
tZZLz 22 Low to Output Low-Z 0 - 0 - 0 -
AC TEST CONDITIONS F_ig._I : AC test load
Input Pulse Level 2.5 V/0.0 v l/O Zo = 50 n
Input Pulse Rise and Fall Time 1 V/ns(20%/80%) 500
Input Timing Measurement 1.25V CL=20 "
Reference Level 7;;125 V
Output Timing Measurement 1.25V .
Reference Level Lig._2 : AC test load (for Enable/Disable spec)
Output Load Fi:S1S:::jvnFi: 2 2-5 V
l/Opin
CL = 5 " 217 a
2002-09-20 11/18
TOSHIBA
TC55WD818FF-133,-150,-167
TIMING DIAGRAMS
READ CYCLE
Read Read Read
Read Read Continue Continue Deselect Read Continue
i t I _ _
iick-cr 2
: tKH tKL S
'it''-'''
CLK . \ j':.....' \ 7t \ 7: \_F\_F\
uri-ri, tAH :' .
Address A4irA..io A§1W //// w,,:.,.:', ti; ”(sz "i...'" "j,
tADvs H: tADVH i' tADVS H tADVH i.' ..'
ADI/ZA As'.,,; 'tt_..::'','-';;'':);.'.'.'., vcssii.,, '//tr)r,.i/i1i,ri1ir'
m t'si-_:._..."itvv"' /i:,, W 44 44 wc',.)? 4: "(4/ As''.',:'.:,-, 44/
"VT-s-Ish-tg?. //§// c''':.,-, 4/ wo...."':....;; 4/ 4/ __.'..'" "e...'..'..'"
CKE lcv":..'..."-',)":,';':.:':'' 4 4/4 4421 ".i..vreir,","." 4/4 4/41 4/4 _..'''"
CE 4 'i., /siro? 454 'i., 'ig'"
a (r" 4: . . .i.'
i i.." i' 360:: i.' te: X W X i' :
I/O it a 400 Q1 )@(Q1+1 )®(Q1+2 étKQLZ 402
'ltr/ig, Don't care
‘ m: Indeterminate
2002-09-20 12/18
TOSHIBA TC55WD818FF-133,-150,-167
WRITE CYCLE
Write Write Write
Write Write Continue Continue Deselect Write Continue
2 t 2 . . . _ .
kck-cr s
E tKH tKL E
:Q—} .
. \ j'.:,...; \ 7‘ \ j.;.., \_7‘_\_%_\
Address gXSW/“W /:/ //7/ /j,.r,p'" MAZW tii.'" /:/
ADV i".i:.:"FC'is'i,.:. 'ti.,.'.,:.'::'--':':'.'.:':':''.'.--'.-:,'',:.''., 2A2/V2/2‘2/A
XA2/2 22/ _.''.'.r.'zziss'.'.i_..'..-s..c'..i..e? 2/
Bv-i-ii-viii',:-:.":..:-; "Cr:::.. 2A5 2A: 'i..:.iv" /////A 2A52A§2
tCKES tCKEH i i'
CKE _iEsi-'.:i/-)crEr'_.,_.: scsi:., /%A5 :W /%5 J"Abri:../"xA.i:./'"
c-EtcEii(.._i;erHs..l:_-,r.:') A $2 v.', 22/
c-st/l/tl/r,),);.),),,))).
i.' tos
005 ii; 01; )@(D1+§1)@(D1+§2
Don), care
. . . . . . . . 2
5NSN5NSN .
Rew%' Ind ete rm I n ate
2002-09-20 13/18
TOSHIBA
WRITE/READ CYCLE
Add ress
TC55WD818FF-133,-150,-167
Read Write
Write Read Write Read Continue Write Continue Read
2 tKC i . V . . .
. 1tTo, te..:
j..:..;.'...) ,'.:.'r.-i.i.l.'_svr.".'...:l._.:-.i'._:.s)vy::'..::..t
. tASHHtAH .
AaA..iioxtiiisii:')
i' tons
A...._)xsyc,,_3xr" / //XA4)/ /s'.ia" /XASX/ /
w-ir-r tADVH i'
XA..':."',,'-:.. 2/22 // i i i i
2E2W/S24H392A7/ "/>A 'i.vr" /tBS.W: ltBHW// /% '.'igssi.'. // // /
222%2/ // mi::...,. % WA 'i..2''"
2/ // 2/) / __:;.'.',..:,",,',",,::::.:)..'-..."'.'.). . Pr).:'...," _:'.,,
Don't care
ig? , Indeterminate
2002-09-20 14/18
TOSHIBA TC55WD818FF-133,-150,-167
CLOCK IGNORE/DESELECT CYCLE
Clock Clock Deselect Deselect
Read Read Ignore Read Write Ignore Read Deselect Continue Continue
/s..r..',vzit
Address . I E E si.i_rrai.:'.oervs.'.:.i,
_ri,':'i,iii,ii:_,."..ii),i'/',ii)fk:::r.:..._..1" . .
ADV i' §///%%/W%%//W%
VV—E;i/W///%/////W////////
Eths "r, tBWHE
W1—t2///////////~;§//////////
i..' tCKEs tCKEH i
tcssq-b tCEH i i tCESVyHrtCEH 5
Cy? _'i'lc..:._..:ii','t','c",ri4l'.__..:i' WA ....il:igizr,,:i'' / /...r.:lcs...:r._'. ':',,i.i.i,cisi..,'...__.i;Er/...._.i.r" //
I/o _:-:'',,,,,;
: .' KQL;
i' 3 tKQv tKoLz:.'i,te,
ii'iiiiiiiti' Don' t care
, Indete rminate
2002-09-20 15/18
TOSHIBA TC55WD818FF-133,-150,-167
SNOOZE CYCLE
ltKH tKL i
"W'-''') :
:.' 5 5))? 5
zz_/5 i,' 55M 5‘L
Etzz i tZZR
Allinputs " i.' ie, i ',.' hh i :...' ...' i.." '...'
(exceptZZ pin)Desele't°:r Read / //(Ah/ // " iDeselector Read W iNormalX :.' X
tZZHZ i 11:2sz i
2 , r .
: . ..:' ))
Dout : 5 ..:' ((
Don't care
Indeterminate
Notes: 1. The 2cycles immediately prior to a Snooze brought about by the ZZ pin must be Read or
Deselect cycles.
2. Memory data is retained during Snooze cycles.
2002-09-20 16/18
TOSHIBA
TC55WD818FF-133,-150,-167
NOTE : 1. Do not apply opposite data polarity to the I/O pins when they are in the output state.
2. Output enable and output disable times are specified as follows using the output load
shown in Fig. 1.
(a) tKQLz, tKQHz
CLK _/_\_2
(See Note 1)
rec/t_,
(See Note 1)
[_\_]Z_
7it5i7 XJ
CCEEZZ E)( )(f
/////XX/
I. Input states are defined in the Synchronous Input Truth Table.
2. If the device was previously deselected, when the device is selected, the
output remains in a high impedance state in the present clock cycle
regardless of CT? because of the output enable delay register.
Valid data appears in the second clock cycle when UE is low.
3. When the device is deselected, the output goes into a high impedance
state in the next clock cycle regardless of (TE.
(b) tGQLz, tGQHz
D DATA OUT
tao" th2V ii KQHZ 0.2V
A VALID DATA OUT x u;
(See Note 2) y, "
0.2V See Note 3) 0.2V
2002-09-20 17/18
TOSHIBA TC55WD818FF-133,-150,-167
PACKAGE DIMENSIONS
Plastic LQFP (LQFP100-P-1420-0.65K)
Unit: mm
22.0k0.2
20.0i0.1
rcls_Eg:z- E50
o cas ala
cm :1:
Eu: :1:
Eu: :1]:
ED: :1:
LIL IEI
T" Chl
Iflz, 'i'lil $1 9;}
:2: IIEU o c!
ELI: Zn] v C)
El]: ma T" Y"
CI :1:
E1]: :1:
ED: ala
Si C) gil
100% f“: 31
’k1HEHHHE i"ea1?"e"1"""l'e)-------
O 575 0.32+O'08 -
. TYP li' -0.07 ['y'irgLjjidfii
V. (ii?
Weight: 0.56 g (typ.)
2002-09-20 18/18
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