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TC55VEM416BXGN55 , 1,048,576-WORD BY 16-BIT FULL CMOS STATIC RAM
TC55VL818FF-83 ,524,288-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAMFEATURES • Organized as 524,288 words by 18 bits • Fast cycle time of 12 ns minimum (83 MHz maximum ..
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TC9432AF ,Digital Servo Single Chip Processor Built in 1 Bit DA ConverterFunctional Description Remarks 1 TEST0 I Test mode terminal. Normally, keep at open. With pull-up r ..
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TC9434AFN ,SUMM-DELTA MODULATION DA CONVERTER WITH BUILT-IN 8-TIMES OVERSAMPLING DIGITAL FILTER/DIGITAL BASS BOOST/ANALOG FILTERFEATURESSSOP24-P-300-0.65AO Built-in 8-times oversampling digital filter.Weight : 0.14g (Typ.)o Low ..
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TC55VD836FF-133-TC55VD836FF-143
262,144-WORD BY 32-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
TC55VD836FF-133,-143,-150 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 99 97 95 93 91 89 87 85 83 81
100 98 96 94 92 90 88 86 84 82 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 32 34 36 38 40 42 44 46 48 50
31 33 35 37 39 41 43 45 47 49
/CE
CE2
/CE
/CK
/OE
ADV
I/OP2 I/O16 I/O15 VDDQ VSSQ I/O14 I/O13 I/O12 I/O11 VSSQ VDDQ I/O10 I/O9 VSS VDD VDD ZZ I/O8 I/O7 VDDQ VSSQ I/O6 I/O5 I/O4 I/O3 VSSQ VDDQ I/O2 I/O1 I/OP1
I/OP3 I/O17 I/O18 VDDQ VSSQ I/O19 I/O20 I/O21 I/O22 VSSQ VDDQ I/O23 I/O24 VDD VDD VDD VSS I/O25 I/O26 VDDQ VSSQ I/O27 I/O28 I/O29 I/O30 VSSQ VDDQ I/O31 I/O32 I/OP4
MODA4A3A2A1A0NCNC TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 36-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
DESCRIPTION The TC55VD836FF is a synchronous static random access memory (SRAM) organized as 262,144 words by 36
bits. NtRAMTM (no-turnaround SRAM) offers high bandwidth by eliminating dead cycles during the transition from
a read to a write and vice versa. All inputs except Output Enable OE and the Snooze pin ZZ are synchronized with the rising edge of the CLK input. A Read operation is initiated by the ADV Address Advanced Input signal ;
the input from the address pins and all control pins except the OE and ZZ pins are loaded into the internal
registers on the rising edge of CLK in the cycle in which ADV is asserted. The output data is available two clock cycles later. Write operations are internally self-timed and are initiated by the rising edge of CLK in the cycle in
which ADV is asserted. The input from the address pins and all control pins except the OE and ZZ pins are loaded
into the internal registers on the rising edge of CLK in the cycle in which ADV is asserted. Input data is loaded in the third cycle after the cycle in which ADV is asserted. Byte Write Enables ( BW1 to BW4 ) allow from one to four
Byte Write operations to be performed. A 2-bit burst address counter and control logic are integrated into this
SRAM. The TC55VD836FF uses a single power supply (3.3 V) or dual power supplies (3.3 V for core and 2.5 V for output buffer) and is available in a 100-pin low-profile plastic QFP (LQFP).
FEATURES Organized as 262,144 words by 36 bits • Fast cycle time of 6.6 ns minimum (150 MHz maximum) • Fast access time of 3.8 ns maximum (from clock edge to data output) • No-turnaround operation with pipeline data output • 2-bit burst address counter (support for interleaved or linear burst sequences) • Synchronous self-timed Write • Byte Write control • Snooze mode pin (ZZ) for power down • LVTTL-compatible interface • Single power supply (3.3 V) or Dual power supplies (3.3 V for core and 2.5 V for output buffer) • Available in 100-pin LQFP package (LQFP100-P-1420-0.65K ; pitch:0.65 mm, height:1.6 mm, weight:0.56 grams (typical))
PIN ASSIGNMENT (TOP VIEW) PIN NAMES Note : NtRAMTM and No-Turnaround Random Access Memory are
trademarks of Samsung Electronics Co., Ltd..
