TC55VD1618FF150 ,1,048,576-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
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TC55VD836FF-133 ,262,144-WORD BY 32-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAMTC55VD836FF-133,-143,-150 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD B ..
TC55VD836FF-143 ,262,144-WORD BY 32-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAMFEATURES • Organized as 262,144 words by 36 bits • Fast cycle time of 6.6 ns minimum (150 MHz maxim ..
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TC9434AFN ,SUMM-DELTA MODULATION DA CONVERTER WITH BUILT-IN 8-TIMES OVERSAMPLING DIGITAL FILTER/DIGITAL BASS BOOST/ANALOG FILTERFEATURESSSOP24-P-300-0.65AO Built-in 8-times oversampling digital filter.Weight : 0.14g (Typ.)o Low ..
TC9434AFN ,SUMM-DELTA MODULATION DA CONVERTER WITH BUILT-IN 8-TIMES OVERSAMPLING DIGITAL FILTER/DIGITAL BASS BOOST/ANALOG FILTERFEATURESSSOP24-P-300-0.65AO Built-in 8-times oversampling digital filter.Weight : 0.14g (Typ.)o Low ..
TC9434AFN ,SUMM-DELTA MODULATION DA CONVERTER WITH BUILT-IN 8-TIMES OVERSAMPLING DIGITAL FILTER/DIGITAL BASS BOOST/ANALOG FILTERTC9434AFNT(‘QARAAFN'lvllIII‘E-A MODULATION DA CONVERTER WITH BUILT-IN 8-TIMESThe TC9434AFN is secon ..
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TC55VD1618FF150
1,048,576-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
TOSHIBA TC55VD1618FF-133,-150,-167
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1,048,576-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
DESCRIPTION
The TC55VD1618FF is a synchronous static random access t,etg1/iE(e,Ael'il), organized as 1,048,576 words by
18 bits. NtRAMTM(no-turnaround) SRAM offers high bandwidt by elimirfatin dead c cles during the
transition from a read to a write and vice versa. All inputs except Output Enable and t e Snooze pin ZZ
are synchronized with the rising edge of the CLK input. A Read operation is initiated b the ADV Address
Advanced In ut signal ; the input from the address ins and all control pins exce t the E and ZZ pins are
loaded into t e internal registers on the rising edge 0 CLK in the cycle in which A V is asserted. The output
data is available two clock C cles later. Write operations are internally self-timed and are initiated b the
rising edgeLfCLK in the eye e in which ADV is asserted. The input from the address Eins and all contro ins
exce t the OE and ZZ pins are loaded into the internal registers; on the risin edge of C K in the cycle in w ich
AD is asserted. In ut data is loaded in the third 0 cle after the cycle in w ich ADV is asserted. Byte Write
Enables(BW1 to BWZ) allow from one to .tsyo Byte rite otierations to be erformed. A .2-bit burst address
counter and control logic are integrated into this SRAM. he TC55VD1 18FF uses a sméle power supPly
(3.3V) or dual ower supplies(3.3V for core and 2.5V for output buffer) and is available in a 1 O-pin 1ow-prio ire
plastic QFP(L&FP).
FEATURES
0 Organized as 1,048,576 words by 18 bits .
0 Fast cycle tlrhe of 6ns minimu.m(167 MHz maximum)
0 Fast access time of " ns nyyrinyu,n.(froy clock edge to data output)
0 y?-.ty,rnarpun,d, operation with pipelipe data output .
o 2-bit burst address cou,nty'.(.suripdrt for interleaved or linear burst sequences)
0 Synchronous self-timed Write
0 Byte Write control
0 Snooze mode pin (Z?) for power down
0 Id.Vr,rL-eompitible interface .
0 Single power supp}y(3.3 V) or Dual fflJ'f/if suthes(3.3V for core and 2.5V for.output buffer) .
0 Available in 100-p1n LQFP package ( QFPlOO- -1420-0.65B ; piteh:0.65 mm, height.'1.6 mm, weight:0.91
grams(typical))
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
wnlw3uu§§3833wlam§twm CLK Clock Input
<
999795 93 91 89 87 85 8.-831 E,F_2,CE2 Chip Enable Inputs
NE i? £698 96 94 92 90 88 86 84 82 tll? m8 E Output Enable
V935 2 $9... USDQ WE Write Enable Input
V55? ET i', 1%i KSCSQ W to m Byte Write Enable
NC EE 7 74 EE l/OPI
l/O9 EE a 73 II l/O8 ADV Address Advance Input
l/O10 -rr 9 72 --- l/OT -
vsso --- 10 71 --- vsso CKE Clock Enable
.3919 :2: 1; a3: i329 ZZ s I t
l/O12 EE 13 68"- l/O5 nooze npu
338 :2: Ili,' Mgi VSDSD l/OI to I/O16 Data Inputs/Outputs
V352 tt 19 22:2: ‘2’?” l/OPI to IIOPZ Parity Data Inputs/Outputs
581131 tt " 23:: 5813‘ MODE Mode Select Input
@218 i) géu- £53? NC Not Connected
l/016 " 23 58'" I/01 NU Not Usable
"OPE :35 g 33333 NE v P s I f c
vsso --- 26 55 --- VSS DD ower upp y or ore
"E g; 33:: XED VDDQ Power Supply for Output Buffer
NE e,'.) $33132333435363738394041424344454647484950¥:: lf Vss Ground for Core
V f B ff
tllflflflllllllflflflllllllflflllllllllf SSQ Ground orOutput u er
2gtns;tttNs-C)DunntDu)uhi-rNtictttuQ Note: NtRAMTM and No-Turnaround Random Access Memory are trademarks
fji<<<<<000707EBA2
O TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction
or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizin TOSHIBA
products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a mal unction or
failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent
TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor
Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
0 The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office
equipment, measurina equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for
usage in equipment t at requires extraordinarily high quality and/or reliability or a malfunction or failure of which m.ay cause loss of human life or
bodily injury CUnintended Usage"). Unintended Usage include atomic ener y control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, me ical instruments, all types of safety devices, etc.. Unintended Usage of
TOSHIBA products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the ap lications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
2002-09-19 1/20
TOSHIBA
TC55VD1618FF-133,-150,-167
BLOCK DIAGRAM
Memory
Cell Array
1 M x 18 bits
(18,874,368 bits)
Din Register 2
A0 to ?fl -F
A19 . Address _
E Register l? /A1
F Binary
MODE Counter and
Address . Address
Register 1 F Register 2
_ADV ' Read/Write "
BW1 to k .
BW2 r Control Logic &
ItttE , Coherency
. Control Logic
til-Jia)-
, Din Register)
utput Register
18 I,.,-......."
' Data-Out Control
rnn'l n
NN l'|'|
-; Data-Out Control
IIO, IIOP
2002-09-19 2/20
TOSHIBA
TC55VD1618FF-133,-150,-167
PIN DESCRIPTIONS
PIN NUMBER SYMBOL TYPE DESCRIPTION
89 CLK Input Clock Input
(NA) All synchronous input signals are registered on
the rising edge of CLK. When the chip is
enabled, address inputs and control pins except
for E and 22 must meet the specified setup
and hold times with respect to the CLK rising
37, 36, 35, 34, 33, 32, A0 to A19 Input Address Inputs
100, 99,82, 81, 44, 45, (synchronous) These address inputs are registered on the rising
46, 47, 48, 49, 50, 83, 80, edge of CLK. When the chip is enabled,
84 address inputs must meet the specified setup
and hold times with respect to the CLK rising
98 E Input Chip Enable Input
(synchronous) This active-Low signal controls the chip status
(enabled or disabled). It is sampled only when
a new external address is loaded.
92 m Input Chip Enable Input
(synchronous) This active-Low signal controls the chip status
(enabled or disabled). It is sampled only when
a new external address is loaded.
97 CE2 Input Chip Enable Input
(synchronous) This active-high signal controls the chip status
(enabled or disabled). It is sampled only when
a new external address is loaded.
86 a Input Output Enable Input
(asynchronous) This active-Low signal controls all 36 bits of the
" output buffer.
88 W Input Write Enable Input
(synchronous) This active-Low input controls Read/Write
operations.
93, 94 W to m Input Byte Write Enable
(synchronous) These active-Low inputs control Byte Write
operations when a Write cycle is active. A Byte
Write pin controls l/O pins as follows.
B)/j1:I/O1 to l/O8, l/OPI
Bvjt2:I/O9 to |/O16, l/OP2
85 ADV Input Address Advance Input
(synchronous) This is used to load the internal registers with
the input from the address and control signals
when it is Low on the rising edge of CLK.
When it is High, the internal burst address
counter is incremented. The external address
inputs are ignored when this signal is High.
87 m Input Clock Enable
(synchronous) When High, CLK input is ignored and outputs
retain the same state.
2002-09-19 3/20
TOSHIBA
TC55VD1618FF-133,-150,-167
PIN NUMBER SYMBOL TYPE DESCRIPTION
64 22 Input Snooze Input
(asynchronous) This active-High signal is used to place the
device into Sleep Mode(Low-Power Standby
Mode). When Low, the device remains in the
Active state. When High, the device goes into
the Sleep state and memory data is retained.
After this signal has been de-asserted, the
device will wake up when a read or write
operation is initiated by ADV.
58, 59, 62, 63, 68, 69, 72, l/OI to I/O16 IIO Data Input/Output
73, 8, 9, 12, 13, 18, 19, 22, (synchronous)
74,24 l/OPI to |/OP2 IIO Parity Data Input/Output
(synchronous)
31 MODE Input Mode Select Input
(synchronous) This signal selects the burst sequence. When
High, the burst sequence is interleaved. When
Low, it is linear.
l, 2, 3, 6, 7, 25, 28, 29, 30, NC NC Not Connected
39, 42, 43, 51, 52, 53, 56,
57, 75, 78, 79, 95, 96
38 NU Input Not Usable
(asynchronous)
14, 15, 16, 41, 65, 66, 91 VDD Supply Power Supply for Core
4, 11, 20, 27, 54, 61, VDDQ Supply Power Supply for Output Buffers
70, 77
17, 40, 67, 90 Vss Ground Ground for Core
5, 10, 21, 26, 55, 60, VSSQ Ground Ground for Output Buffers
2002-09-19 4/20
TOSHIBA TC55VD1618FF-133,-150,-167
OPERATING MODE
(1) Synchronous Input Truth Table
OPERATION m ADV CE W Addr. Used m 22 (2 cycllé3|ater)
Read (begin burst) H L Select x External L L Output
Read (continue burst) x H x x Internal L L Output
Write (begin burst) L L Select L External L L Input
Write (continue burst) x H x L Internal L L Input
NOP/Write Abort (begin burst) L L Select H x L L Hi-Z
Write Abort (conti nue bu rst) M H x H Internal L L Hi-Z
Deselected x L Deselect x x L L Hi-Z
Deselect Continue (Note 2) x H x x x L L Hi-Z
Ignore Clock Edge (Note 3) x x x x x H L Previous value
Snooze x x x x x x H Hi-Z
Notes: 1. H means logical High and L means logical Low. X means Don't care.
2. A Deselect Continue cycle can only be entered if a Deselect cycle is executed before it.
3. When the Ignore Clock Edge command is asserted during a Read operation, the output data
for the previous cKcle still appear on the I/O pins. When the command is asserted during a
Write operation, t e I/O pins remain at Hi-Z and the Write operation is not executed.
4. All synchronous Inputs must exhibit adequate setup and hold times either side of the rising
edge of the CLK pin.
5. ZZ input is asynchronous, but is included in this table.
(2) Write Enable Truth Table
- - I/OI to I/O8 |/09 to l/O16
l/OPI l/OP2
Output Output
OPERATION B 1 B 2
Input Input
Input Hi-Z
Hi-Z Input
H H Hi-Z Hi-Z
Notes: 1. H means logical High and L means logical Low. M means Don't care.
2. The status for I/O pins described in this column appears two clock cycles after the cycle in
which the Read or Write command is asserted.
(3) Asynchronous Inputs Truth Table
OPERATION E
Stop clock (Note 2)
Notes: 1. H means logical High and L means logical Low. X means Don't care.
2. The Stop CLK Mode achieves Low-Power Standby by stopping the input clock.
3. The Snooze Mode achieves Low-Power Standby by asserting the ZZ pin.
4. The cycle immediately prior to a snooze brought about by the ZZ pin must be a Read Mode or
Deselect Mode cycle.
5. Memory data is retained during Snooze Mode cycles.
(4) Burst Sequence
MODE PIN BURST OPERATION
L Linear burst order
H or NC Interleaved burst order
2002-09-19 5/20
TOSHIBA TC55VD1618FF-133,-150,-167
a) Linear Burst Sequence (MODE input=Vss)
Bit Order: A19, .................. A1, A0
1st Address 2nd Address 3rd Address 4th Address
(external) (internal) (internal) (internal)
xx ...... xxoo xx ...... XX01 XX ...... XX10 XX ...... XXI 1
xx ...... XX01 xx ...... XX10 XX ...... XXI 1 xx ...... xxoo
xx ...... XX10 xx ...... XXI 1 XX ...... xxoo XX ...... XX01
xx ...... XXI 1 xx ...... xxoo xx ...... XX01 XX ...... XX10
b) Interleaved Burst Sequence (MODE input=VDD or NC)
Bit Order: A19 ................... A1, A0
1st Address 2nd Address 3rd Address 4th Address
(external) (internal) (internal) (internal)
XX ...... xxoo xx _..... XX01 XX ...... XX10 XX ...... XXI 1
xx ...... XX01 xx ...... xxoo XX ...... XXI 1 XX ...... XX10
xx ...... XX10 xx ...... XXI 1 xx ...... xxoo XX ...... XX01
XX ...... XXI 1 XX ...... XX10 XX ...... XX01 XX ...... xxoo
DEVICE OPERATION
(1) Read Operation
CYCLE ADDRESS m BW ADV E E m " OPERATION
n A0 H x L L x L x Address & control valid
n + 1 x x x x x x L x
n + 2 x x x x x L L Q0 Read out A0
Note 1: H means logical High and L means logical Low. X means Don't care. a is data output.
(2) Burst Read Operation
CYCLE ADDRESS " W ADV E E m 1/0 OPERATION
n A0 H x L L x L x Address & control valid
n + 1 x x x H x x L x
n + 2 x x x H x L L Q0 Read out A0
n+3 x x M H x L L QO+1 Read outA0+1
n+4 x x H x L L QO+2 Read outA0+2
n+5 A1 H x L L L QO+3 Read out A0+3
n + 6 x x x H x L L Q0 Read out A0
n + 7 x x x H x L L Q1 Read out A1
n+8 A2 H M L L L L Q1+1 Read out A1+1
n+9 A3 H x L L L L Q1+2 Read out A1+2
n + 10 x x x x x L L Q2 Read out A2
Note I: H means logical High and L means logical Low. X means Don't care. a is data output.
2002-09-19 6/20
TOSHIBA
(3) Write Operation
TC55VD1618FF-133,-150,-167
CYCLE ADDRESS W W ADV E E CKE I/O OPERATION
n A0 L L L x L x Address & control valid
n + 1 x x x x x x L x
n + 2 x x x x x x L D0 Write to A0
Note I: H means logical High and L means logical Low.
(4) Burst Write Operation
CYCLE ADDRESS
n+10 X
Note 1: H means logical High and L means logical Low.
r—I—III—IIIII—
(5) Read Operation with Clock Enable
X means Don't care. D is data input.
OPERATION
Address & control valid
Write A0
Write A0 + 1
Write A0 + 2
Write A0 + 3
Write A0
Write A1
Write A1 + 1
Write A1 + 2
L D2 Write A2
X means Don't care. D is data input.
CYCLE ADDRESS " Bt/it ADV E E m PO OPERATION
n A0 H x L L x L x Address & control valid
n +1 x x x x x x H x Ignore cycle
n+2 A1 H x L x L x Address & control valid
n+3 x x x x x L H Q0 Ignore clock, Q0 is on bus
n+4 x x x x x L H Q0 Ignore clock, Q0 is on bus
n + 5 A2 H x L L L L Q0 Read out A0
n + 6 A3 H x L L L L Q1 Read out A1
n + 7 x x x x x L L Q2 Read out A2
Note 1: H means logical High and L means logical Low. X means Don't care. Q is data output.
2002-09-19 7/20
TOSHIBA
(6) Write Operation with Clock Enable
TC55VD1618FF-133,-150,-167
CYCLE ADDRESS 1tVE W ADV E E m I/O OPERATION
n A0 L L L L x L x Address & control valid
n +1 x x x x x x H x Ignore clock
n+2 A1 L L x L x Address & control valid
n + 3 x x x x x x H x Ignore clock
n + 4 x x M x x x H x Ignore clock
n + 5 A2 L L L L x L D0 Address & control valid
n + 6 A3 L L L L x L D1 Write A1
n + 7 x x x x x x L D2 Write A2
Note I: H means logical High and L means logical Low. X means Don't care. D is data input.
(7) Read Operation with Chip Enable
CYCLE ADDRESS W W ADV E E m I/O OPERATION
n A0 H x L L x L x Address & control valid
n + 1 x x x L H x L x Deselect
n + 2 A1 x L L L L QO Read A0
n + 3 x x x L H x L 2 Deselect
n + 4 x x M L H L L Q1 Read A1
n + 5 A2 H x L L x L 2 Deselect
n + 6 x x x L H x L 2 Deselect
n + 7 x x x L H L L Q2 Read A2
Note I: H means logical High and L means logical Low. M means Don't care. Q is data output.
Z means Hi-Z.
(8) Write Operation with Chip Enable
CYCLE ADDRESS " W ADV E o-E W I/O OPERATION
n A0 L L L L x L x Address & control valid
n + 1 x x x L H x L x Deselect
n + 2 A1 L L L x L DO Write A0
n + 3 x x x L H x L 2 Deselect
n + 4 x x x L H x L D1 Write A1
n + 5 A2 L L L L x L 2 Deselect
n + 6 x x x L H x L 2 Deselect
n + 7 x x M L H x L D2 Write A2
Note I: H means logical High and L means logical Low. X means Don't care. D is data input.
Z means Hi-Z.
2002-09-19 8/20
TOSHIBA TC55VD1618FF-133,-150,-167
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage -0.5 to 4.6 V
VDDQ Output Buffer Power Supply Voltage - 0.5 to VDD+ 0.5 (S4.6V max) V
" Input Terminal Voltage -0.5 * to 4.6 V
VI/o Input/Output Terminal Voltage - 0.5 * to VDDQ+0.5** (S4.61/ max) V
PD Power Dissipation 1.6 W
Tsolder Soldering Temperature(10s) 260 ''C
Tstrg Storage Temperature -65 to 150 "C
Topr Operating Temperature - 10 to 85 ''C
*: -1.0V with a pulse width of 20% of th(min) (3 ns max)
**: Vmoa+ 1.0V with a pulse width of 20% of th(min) (3 ns max)
RECOMMENDED DC OPERATING CONDITIONS(Ta=0 to 70°C)
SYMBOL PARAMETER MIN TYP. MAX UNIT
VDD Power Supply Voltage 3.135 3.3 3.465 V
VDDQ Output Buffer Power Supply Voltage 3.135 3.3 3.465 V
VlH Input High Voltage 2.0 - VDD + 0.3** V
Nhril Input High Voltage for MODE pin VDD-0.3 VDD VDD+O.3 V
" Input Low Voltage - 0.3 * - 0.8 V
V|L1 Input Low Voltage for MODE and NU pins -0.3 0.0 0.3 V
*: -0.7V with a pulse width of 20% of th(min) (3 ns max)
**: VDDQ+0.7V with a pulse width of 20% of th(min) (3 ns max)
Note: NU pin must be low or not connected.
You must not apply a voltage of more than 0.8V to the NU.
2002-09-19 9/20
TOSHIBA TC55VD1618FF-133,-150,-167
DC CHARACTERISTICS (Ta = o to 70°C, VDD = VDDQ = 3.3 v i 5%)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP. MAX UNIT
IIL Input Leakage Current VIN = 0 to VDD -1 - 1 PA
Input Current
I V = V . V -1 - 1 A
NU (NU pin) IN 0 to 0.3 '
D . D I t t t D I t
he Output Leakage Current evnce ese ec ed or Ou pu ese ec ed, -1 - 1 PA
VOUT=0 to VDDQ
. IOH = - 8 mA 2.4 - -
VOH Output High Voltage
IOH = - 100 prA vDDQ - 0.2 - - v
IOL = 8 mA - - 0.4
VOL Output Low Voltage
IOL = 100 PA - - 0.2
. 167MHz - - 410
. IOUT=0mA, all inputs=VDo-0.2 V/0.2V
IDD01 Operating Current 150MHz - - 390 mA
Clock2tKc(min) 133MHz - - 370
O eratin Current Device Deselected 167MHz - - 200
IDDOZ Cl', ) g IOUT=0 mA, all inputs=Vioo-0.2 V/0.2 v 150MHz - - 180 mA
I Clock2tkc(min) 133MHz - - 150
St db C t .
IDDS1 an y urren Clock=Vss, all Inputs=VlH or VIL - - 65 mA
(TTL level)
Standb C rrent .
IDDSZ y u Clock = Vss, all Inputs = VDD - 0.2 v or 0.2 v - - 10 mA
(MOS level)
22; VDD - 0.2 v
loose Sgtandby :Aurgent all inputs=Vss-th2V or 0.2V - - 20 mA
( no0ze o e) Clock2te(min)
CKEgle
1.3054 5%‘33’ :urrent All inputs = VDD - 0.2 v or 0.2 v - - 20 mA
( o e) Clock2te(min)
Note: Operating Current(IDD01) is specified with 50% Read cycles and 50% Write cycles.
CAPACITANCE (Ta = 25°C, f= 1.0 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
C Input Capacitance VIN = GND 7 pF
Input Capacitance for MODE, ZZ, NU pin V|N=GND 10 pF
CI/o Input/Output Capacitance VI/o = GND 9 pF
Note: This parameter is periodically sampled and is not 100% tested.
2002-09-19 10/20
TOSHIBA TC55VD1618FF-133,-150,-167
AC CHARACTERISTICS (Ta = o to 70°C, VDD = VDDQ = 3.3 v , 5%)
SYMBOL PARAMETER TC55VD1618FF-167 TC55VD1618FF-150 TC55VD1618FF-133 UNIT
MIN MAX MIN MAX MIN MAX
ha: CLK Cycle Time 6 - 6.6 - 7.5 -
tKH CLK High Pulse Width 2.2 - 2.5 - 3 -
tKL CLK Low Pulse Width 2.2 - 2.5 - 3 -
tKQV CLK High to Output Valid - 3.6 - 3.8 - 4.2
tKQX CLK High to Output Invalid 1.5 - 1.5 - 1.5 -
tKQLZ CLK High to Output Low-Z 1.5 - 1.5 - 1.5 -
tKQHZ CLK High to Output High-Z 1.5 3.5 1.5 3.5 1.5 3.5
teov E Low to Output Valid - 3.6 - 3.8 - 4.2
tGQLZ E Low to Output Low-Z 1.5 - 1.5 - 1.5 -
tGQHZ tN High to Output High-Z 1.5 3.8 1.5 4 1.5 4.2
tAs Address Setup Time from CLK 1.5 - 1.5 - 1.5 -
tDS Data Setup Time from CLK 1.5 - 1.5 - 1.5 -
tws W Setup Time from CLK 1.5 - 1.5 - 1.5 -
tcss CE Setup Time from CLK 1.5 - 1.5 - 1.5 - ns
tADVS ADV Setup Time from CLK 1.5 - 1.5 - 1.5 -
ths W Setup Time from CLK 1.5 - 1.5 - 1.5 -
tCKES m Setup Time from CLK 1.5 - 1.5 - 1.5 -
tAH Address Hold Time from CLK 0.5 - 0.5 - 0.5 -
tDH Data Hold Time from CLK 0.5 - 0.5 - 0.5 -
tWH m Hold Time from CLK 0.5 - 0.5 - 0.5 -
tCEH CE Hold Time from CLK 0.5 - 0.5 - 0.5 -
tADVH ADV Hold Time from CLK 0.5 - 0.5 - 0.5 -
tBWH W Hold Time from CLK 0.5 - 0.5 - 0.5 -
tCKEH m Hold Time from CLK 0.5 - 0.5 - 0.5 -
tzs ZZ Standby Time 5 - 5 - 5 -
tZR 22 Recovery Time 5 - 5 - 5 -
tZHZ 22 to Output in High-Z - 2 - 2 - 2 cycle
AC TEST CONDITIONS Lig._1 : AC test load
Input Pulse Level 3.0 V/0.0 V " 20 = 50 Q
Input Pulse Rise and Fall Time 1 V/ns(20%/80%) 509
Input Timing Measurement 1.5V CL=20 "
Reference Level J1su
Output Timing Measurement 1.5V .
Reference Level Lig._2 : AC test load (for Enable/Disable spec)
Output Load Fi:51S::;vnFiign. 2 3. V
l/Opin
CL = 5 " 217 Q
2002-09-19 11/20
TOSHIBA
TC55VD1618FF-133,-150,-167
TIMING DIAGRAMS
READ CYCLE
Read Read Read
Read Read Continue Continue Deselect Read Continue
i t I _ _
iick-cr 2
: tKH tKL S
'it''-'''
CLK . \ j':.....' \ 7t \ 7: \_F\_F\
uri-ri, tAH :' .
Address A4irA..io A§1W //// w,,:.,.:', ti; ”(sz "i...'" "j,
tADvs H: tADVH i' tADVS H tADVH i.' ..'
ADI/ZA As'.,,; 'tt_..::'','-';;'':);.'.'.'., vcssii.,, '//tr)r,.i/i1i,ri1ir'
m t'si-_:._..."itvv"' /i:,, W 44 44 wc',.)? 4: "(4/ As''.',:'.:,-, 44/
"VT-s-Ish-tg?. //§// c''':.,-, 4/ wo...."':....;; 4/ 4/ __.'..'" "e...'..'..'"
CKE lcv":..'..."-',)":,';':.:':'' 4 4/4 4421 ".i..vreir,","." 4/4 4/41 4/4 _..'''"
CE 4 'i., /siro? 454 'i., 'ig'"
a (r" 4: . . .i.'
i i.." i' 360:: i.' te: X W X i' :
I/O it a 400 Q1 )@(Q1+1 )®(Q1+2 étKQLZ 402
'ltr/ig, Don't care
‘ m: Indeterminate
2002-09-19 12/20
TOSHIBA TC55VD1618FF-133,-150,-167
WRITE CYCLE
Write Write Write
Write Write Continue Continue Deselect Write Continue
2 t 2 . . . _ .
kck-cr s
E tKH tKL E
:Q—} .
. \ j'.:,...; \ 7‘ \ j.;.., \_7‘_\_%_\
Address gXSW/“W /:/ //7/ /j,.r,p'" MAZW tii.'" /:/
ADV i".i:.:"FC'is'i,.:. 'ti.,.'.,:.'::'--':':'.'.:':':''.'.--'.-:,'',:.''., 2A2/V2/2‘2/A
XA2/2 22/ _.''.'.r.'zziss'.'.i_..'..-s..c'..i..e? 2/
Bv-i-ii-viii',:-:.":..:-; "Cr:::.. 2A5 2A: 'i..:.iv" /////A 2A52A§2
tCKES tCKEH i i'
CKE _iEsi-'.:i/-)crEr'_.,_.: scsi:., /%A5 :W /%5 J"Abri:../"xA.i:./'"
c-EtcEii(.._i;erHs..l:_-,r.:') A $2 v.', 22/
c-st/l/tl/r,),);.),),,))).
i.' tos
005 ii; 01; )@(D1+§1)@(D1+§2
Don), care
. . . . . . . . 2
5NSN5NSN .
Rew%' Ind ete rm I n ate
2002-09-19 13/20
TOSHIBA
WRITE/READ CYCLE
Add ress
TC55VD1618FF-133,-150,-167
Read Write
Write Read Write Read Continue Write Continue Read
2 tKC i . V . . .
. 1tTo, te..:
j..:..;.'...) ,'.:.'r.-i.i.l.'_svr.".'...:l._.:-.i'._:.s)vy::'..::..t
. tASHHtAH .
AaA..iioxtiiisii:')
i' tons
A...._)xsyc,,_3xr" / //XA4)/ /s'.ia" /XASX/ /
w-ir-r tADVH i'
XA..':."',,'-:.. 2/22 // i i i i
2E2W/S24H392A7/ "/>A 'i.vr" /tBS.W: ltBHW// /% '.'igssi.'. // // /
222%2/ // mi::...,. % WA 'i..2''"
2/ // 2/) / __:;.'.',..:,",,',",,::::.:)..'-..."'.'.). . Pr).:'...," _:'.,,
Don't care
ig? , Indeterminate
2002-09-19 14/20
TOSHIBA TC55VD1618FF-133,-150,-167
CLOCK IGNORE/DESELECT CYCLE
Clock Clock Deselect Deselect
Read Read Ignore Read Write Ignore Read Deselect Continue Continue
/s..r..',vzit
Address . I E E si.i_rrai.:'.oervs.'.:.i,
_ri,':'i,iii,ii:_,."..ii),i'/',ii)fk:::r.:..._..1" . .
ADV i' §///%%/W%%//W%
VV—E;i/W///%/////W////////
Eths "r, tBWHE
W1—t2///////////~;§//////////
i..' tCKEs tCKEH i
tcssq-b tCEH i i tCESVyHrtCEH 5
Cy? _'i'lc..:._..:ii','t','c",ri4l'.__..:i' WA ....il:igizr,,:i'' / /...r.:lcs...:r._'. ':',,i.i.i,cisi..,'...__.i;Er/...._.i.r" //
I/o _:-:'',,,,,;
: .' KQL;
i' 3 tKQv tKoLz:.'i,te,
ii'iiiiiiiti' Don' t care
, Indete rminate
2002-09-19 15/20
TOSHIBA TC55VD1618FF-133,-150,-167
SNOOZE CYCLE
_4ts-:cp i
E tKH tKL i
i..' i' i n i
it 5 5 it i
-r-idz-' a a D 52R 5
zz_/§ i..". i.'. ((
Allinputs Desele:to§rReadW//E/ /f/%// " ?DeselectorRéead W ?Normalx _.:: X
(except 22 pin) .
tZHz E
Dout a g i' (t i..' i,,' i, i.. ':..',aiiii
Don), care
Indeterminate
Notes: 1. The 2cycles immediately prior to a Snooze brought about by the ZZ pin must be Read or
Deselect cycles.
2. Memory data is retained during Snooze cycles.
2002-09-19 16/20
TOSHIBA
TC55VD1618FF-133,-150,-167
NOTE : 1. Do not apply opposite data polarity to the I/O pins when they are in the output state.
2. Output enable and output disable times are specified as follows using the output load
shown in Fig. 1.
(a) tKQLz, tKQHz
CLK _/_\_/_\_2
ADV Iv'''"
(See Note 1)
rec/t_,
(See Note 1)
[_\_]Z_
ca, E)( )(f WX X/
CE2 Jd
tKQLz tKQHZ
Dout "'\ 0.2V y, 0.2V
l VALID DATA OUT y 3:
(See Note 2) y, "
0.2V See Note 3) 0.2V
. Input states are defined in the Synchronous Input Truth Table.
. If the device was previously deselected, when the device is selected, the
output remains in a high impedance state in the present clock cycle
regardless of CT? because of the output enable delay_register.
Valid data appears in the second clock cycle when OE is low.
(b) tGQLz, tGQHz, tZHz
o-E, 22
D DATA OUT
4 tZHZ
. When the device is deselected, the output goes into a high impedance
state in the next clock cycle regardless of (TE.
2002-09-19 17/20
TOSHIBA TC55VD1618FF-133,-150,-167
Cl VDDQ=2.5V Interface specification
RECOMMENDED DC OPERATING CONDITIONS(Ta=0 to 70°C)
SYMBOL PARAMETER MIN TYP. MAX UNIT
VDD Power Supply Voltage 3.135 3.3 3.465 V
VDDQ Output Buffer Power Supply Voltage 2.375 2.5 2.9 V
Input High Voltage for Address and Control pins 1.7 - VDD+0.3**
" Input High Voltage for IIO pins 1.7 - VDDQ+0.3*** V
Nhril Input High Voltage for MODE pin VDD-0.3 VDD VDD+O.3
" Input Low Voltage - 0.3 * - 0.7
VII Input Low Voltage for MODE and NU pins -0.3 0.0 0.3
*: -0.7V with a pulse width of 20% of th(min) (3 ns max)
**: VDD+0.7 V with a pulse width of 20% of th(min) (3 ns max)
***: VDDQ+0.7V with a pulse width of 20% of tKC(min) (3 ns max)
NOTE: NU pin must be low or not connected.
You must not apply a voltage of more than 0.8V to the NU.
DC CHARACTERISTICS (Ta = O to 70°C, VDD = 3.3 V i 5%, VDDQ = 2.375 V to 2.9 V)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP. MAX UNIT
IIL Input Leakage Current VIN = 0 to VDD -1 - 1 PA
Input Current
= . - 1 - 1 A
INU (NU pin) I/m 0V to 0 3V p
I O t t L k C t Device Deselected or Output Deselected, 1 1 A
u u ea a e urren - -
LO p g VOUT=0 to VDDQ #
. IOH = - 1 mA 2.0 - -
VOH Output High Voltage
IOH = - 100 psA VDDQ - 0.2 - - v
kw= 1 mA - - 0.4
VOL Output Low Voltage
ICL = 100 PA - - 0.2
. 167MHz - - 410
. IOUT=0mA, all inputs=VDo-0.2 V/0.2V
bool Operating Current > . 150MHz - - 390 mA
Clock2te(min) 133MHz - - 370
C) eratin Current Device Deselected 167MHz - - 200
IDDO2 .07] g low: 0 mA, all inputs = VDD - 0.2 wo.2 v 150MHz - - 180 mA
(i e) Clockithmin) 133MHz - - 150
IDDSZ S andby urren Clock=Vss, all inputs=VDD- 0.2V or 0.2V - - 10 mA
(MOS level)
Standby Current ZZTVDD 0.2V
IDDS3 all inputs=Vss-th2V or 0.2V - - 20 mA
(Snooze Mode) Clock2tKc(min)
CKEzle
IDDS4 Sta_ndby Current All inputs-- VOD - 0.2 v or 0.2 v - - 20 mA
(CKE Mode) Clock2tkc(min)
Note: Operating Current(IDD01) is specified with 50% Read cycles and 50% Write cycles.
2002-09-19 18/20
TOSHIBA TC55VD1618FF-133,-150,-167
AC CHARACTERISTICS (Ta = 0 to 70°C, VDD = 3.3 V i 5%, VDDQ = 2.375 V to 2.9 V)
SYMBOL PARAMETER TC55VD1618FF-167 TC55VD1618FF-150 TC55VD1618FF-133 UNIT
MIN MAX MIN MAX MIN MAX
ha: CLK Cycle Time 6 - 6.6 - 7.5 -
tKH CLK High Pulse Width 2.2 - 2.5 - 3 -
tKL CLK Low Pulse Width 2.2 - 2.5 - 3 -
tKQV CLK High to Output Valid - 3.6 - 3.8 - 4.2
tKQX CLK High to Output Invalid 1.5 - 1.5 - 1.5 -
tKQLZ CLK High to Output Low-Z 1.5 - 1.5 - 1.5 -
tKQHZ CLK High to Output High-Z 1.5 3.5 1.5 3.5 1.5 3.5
teov E Low to Output Valid - 3.6 - 3.8 - 4.2
tGQLZ E Low to Output Low-Z 1.5 - 1.5 - 1.5 -
tGQHZ tN High to Output High-Z 1.5 3.8 1.5 4 1.5 4.2
tAs Address Setup Time from CLK 1.5 - 1.5 - 1.5 -
tDS Data Setup Time from CLK 1.5 - 1.5 - 1.5 -
tws W Setup Time from CLK 1.5 - 1.5 - 1.5 -
tcss CE Setup Time from CLK 1.5 - 1.5 - 1.5 - ns
tADVS ADV Setup Time from CLK 1.5 - 1.5 - 1.5 -
ths W Setup Time from CLK 1.5 - 1.5 - 1.5 -
tCKES m Setup Time from CLK 1.5 - 1.5 - 1.5 -
tAH Address Hold Time from CLK 0.5 - 0.5 - 0.5 -
tDH Data Hold Time from CLK 0.5 - 0.5 - 0.5 -
tWH m Hold Time from CLK 0.5 - 0.5 - 0.5 -
tCEH CE Hold Time from CLK 0.5 - 0.5 - 0.5 -
tADVH ADV Hold Time from CLK 0.5 - 0.5 - 0.5 -
tBWH W Hold Time from CLK 0.5 - 0.5 - 0.5 -
tCKEH m Hold Time from CLK 0.5 - 0.5 - 0.5 -
tzs ZZ Standby Time 5 - 5 - 5 -
tZR 22 Recovery Time 5 - 5 - 5 -
tZHZ 22 to Output in High-Z - 2 - 2 - 2 cycle
AC TEST CONDITIONS Lig._1 : AC test load
Input Pulse Level 2.5 wo.o v " Zo = 50 Q
Input Pulse Rise and Fall Time 1 V/ns(20%/80%) 509
Input Timing Measurement 1.25V CL=20 "
Reference Level [L125 V
Output Timing Measurement 1.25V .
Reference Level Lig._2 : AC test load (for Enable/Disable spec)
Output Load Fi:51S::;vnFiign. 2 2. V
l/Opin
CL = 5 " 217 Q
2002-09-19 19/20
TOSHIBA TC55VD1618FF-133,-150,-167
PACKAGE DIMENSIONS
Plastic LQFP (LQFP100-P-1420-0.65B)
Unit: mm
t 22.0i0.2
.0 20.0A0.1 l
o o-Y- "
'- N E: cu
d ci bit ci
+l -H .=' -H
CD. o. bxf o
E S E: si
arlrJrlrJLarlrILIrJ0LgrJLlrlrJrJ__, --___-- H7
( . 9:032:008
0.575TYP -daaa-rtse7u-,j.-1-a,
l 21.0:02 I
0.1i'0.05 b
0.45~o.75§ CD
1.0:02
Weight: 0.91 g (typ.)
2002-09-19 20/20
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